This document provides a set of design
guidelines, recommendations, and a list of factors to consider for designs that use
Stratix® 10 FPGAs.
It is important to follow Intel recommendations throughout the design process for
Stratix® 10 designs. This
document also assists you with planning the FPGA and system early in the design process, which
is crucial to successfully meet design requirements.
Note: This document does not include all
Stratix® 10 device
details and features. For more information about
Stratix® 10 devices and
features, refer to the respective
Stratix® 10 User Guides.
The material references the
Stratix® 10 device architecture as well as
aspects of the
Quartus® Prime software and third-party tools that you might use
in your design. The guidelines presented in this document can improve productivity and avoid
common design pitfalls.
Early power estimation, thermal management option, planning for
configuration scheme, planning for on-chip debugging
Pin Connection Considerations for Board Design
Power-up, power pins, PLL connections, decoupling capacitors,
configuration pins, signal integrity, board-level
I/O and Clock Planning
Pin assignments, early pin planning, I/O features and
connections, memory interfaces, clock and PLL selection,
simultaneous switching noise (SSN)
Coding styles and design recommendations, Platform Designer, planning for hierarchical or team-based
Design Implementation, Analysis, Optimization, and
Synthesis tool, device utilization, messages, timing constraints
and analysis, area and timing optimization, compilation time,
verification, power analysis and optimization
Stratix® 10 Device Design Flow
In systems that contain an
device, the FPGA typically plays a large role in the overall system and affects the rest of
the system design. It is important to start the design process by creating detailed design
specifications for the system and the FPGA, and determining the FPGA input and output
interfaces to the rest of the system.
Table 2. Design Specifications Checklist
Create detailed design specifications and a test plan if appropriate.
Plan clock resources and I/O interfaces early with a block
Create detailed design specifications that define the system before you create your logic
design or complete your system design, by performing the following:
Specify the I/O interfaces for the FPGA
Identify the different clock domains
Include a block diagram of basic design functions
Include intellectual property (IP) blocks
Note: Taking the time to create
these specifications improves design efficiency, but this stage is often skipped by FPGA
Create a functional verification/test plan
Consider a common design directory structure
Create a functional verification plan to ensure the team knows how to verify the system.
Creating a test plan at this stage can also help you design for testability and design for
manufacturability. For example, do you want to perform built-in-self test (BIST) functions to
drive interfaces? If so, you could use a UART interface with a
processor inside the FPGA device. You might require the ability to validate all the design
If your design includes multiple designers, it is useful to consider a common design
directory structure. This eases the design integration stages.
Select IP that affects system design, especially I/O interfaces.
If you plan to evaluate
Intel® FPGA IP, ensure that
your board design supports JTAG connections.
Intel and its third-party IP partners offer a large selection of
off-the-shelf IP cores optimized for Intel devices. You can easily
implement these parameterized blocks of IP in your design, reducing your system implementation
and verification time, and allowing you to concentrate on adding proprietary value.
IP selection often affects system design, especially if the FPGA interfaces with other
devices in the system. Consider which I/O interfaces or other blocks in your system design can
be implemented using IP cores, and plan to incorporate these cores in your FPGA design.
Intel® FPGA IP Evaluation Mode feature available for many IP cores allows
you to program the FPGA to verify your design in hardware before you purchase the IP license.
The evaluation supports an untethered mode, in which the design runs for a limited time, or a
tethered mode. The tethered mode requires an Intel
serial JTAG cable connected between the JTAG port on your board and a host computer running
Quartus® Prime Programmer for the duration of the hardware
Take advantage of Platform Designer
for system and processor designs.
Platform Designer is a system integration tool
included as part of the
Quartus® Prime software. Platform Designer captures system-level hardware designs at a high level
of abstraction and automates the task of defining and integrating customized Hardware
Description Language (HDL) components. These components include IP cores, verification IP, and
other design modules. Platform Designer facilitates design reuse
by packaging and integrating your custom components with Intel and third-party IP components. Platform Designer automatically creates interconnect logic from the high-level
connectivity you specify, thereby eliminating the error-prone and time-consuming task of
writing HDL to specify system-level connections.
Platform Designer is more powerful if you design
your custom components using standard interfaces. By using standard interfaces, your
components inter-operate with the components in the Platform Designer Library. In addition, you can take advantage of bus functional models
(BFMs), monitors, and other verification IP to verify your design.
Device selection is the first step in the
Stratix® 10 design process—choosing the device family variant, device density,
features, package, and speed grade that best suit your design requirements.
Table 7. Logic, Memory, and Multiplier Density Checklist
Estimate the required logic, memory, and multiplier
Reserve device resources for future development and
Stratix® 10 devices offer a range of densities that provide different
amounts of device logic resources, including memory, multipliers, and adaptive logic module
(ALM) logic cells. Determining the required logic density can be a challenging part of the
design planning process. Devices with more logic resources can implement larger and
potentially more complex designs, but generally have a higher cost. Smaller devices have lower
static power utilization.
Stratix® 10 devices support vertical migration,
which provides flexibility.
You may observe 10% – 15% increase in resource utilization when you migrate
your design from existing devices to
Stratix® 10 devices.
Review the resource utilization to find out which device density fits the design. Consider
that the coding style, device architecture, and optimization options used in the
Quartus® Prime software can significantly affect a design’s resource
utilization and timing performance.
Select a device that meets your design requirements with some safety margin in case you want
to add more logic later in the design cycle, upgrade, or expand your design. You might also
want additional space in the device to ease design floorplan creation for an incremental or
team-based design. Consider reserving resources for debugging.
Consider the I/O pins you need to reserve for debugging.
Verify that the number of LVDS channels are enough.
Determine the required number of I/O pins for your application, considering
the design’s interface requirements with other system blocks.
Larger densities and package pin counts offer more full-duplex LVDS channels for different
signaling; ensure that your device density-package combination includes enough LVDS channels.
Other factors can also affect the number of I/O pins required for a design, including
simultaneous switching noise (SSN) concerns, pin placement guidelines, pins used as dedicated
inputs, I/O standard availability for each I/O bank, differences between I/O standards and
speed for row and column I/O banks, and package migration options.
You can compile any existing designs in the
software to determine how many I/O pins are used. Also consider reserving I/O pins for
Determine the device speed grade that you require.
The device speed grade affects the device timing performance and timing
closure, as well as power utilization. One way to determine which speed grade your design
requires is to consider the supported clock rates for specific I/O interfaces.
You can use the fastest speed grade during prototyping to reduce compilation
time (because less time is spent optimizing the design to meet timing requirements), and then
move to a slower speed grade for production to reduce cost if the design meets its timing
Consider vertical device migration availability and
Refer to the
External Memory InterfacesIntel
Stratix 10 FPGA IP User Guide for the external memory
interface (EMIF) pin pairing.
Stratix® 10 devices support vertical migration within the
same package, which enables you to migrate to different density devices whose dedicated input
pins, configuration pins, and power pins are the same for a given package. This feature allows
future upgrades or changes to your design without any changes to the board layout, because you
can replace the FPGA on the board with a different density
Stratix® 10 device.
Determine whether you want the option of migrating your design to another
device density. Choose your device density and package to accommodate any possible future
device migration to allow flexibility when the design nears completion. You should specify any
potential migration options in the
Quartus® Prime software at the
beginning of your design cycle or as soon as the device migration selection is possible in the
Quartus® Prime software. Selecting a migration device can
impact the design’s pin placement, because the Fitter ensures your design is compatible with
the selected devices. It is possible to add migration devices later in the design cycle, but
it requires extra effort to check pin assignments, and can require design or board layout
changes to fit into the new target device. It is easier to consider these issues early in the
design cycle than at the end, when the design is near completion and ready for migration.
Quartus® Prime Pin Planner highlights pins that change
function in the migration device when compared to the currently selected device.
System information related to the FPGA should be planned early in the design process, before
designers have completed the design in the
software. Early planning allows the FPGA team to provide early information to PCB board and
Early Power Estimation
Table 11. Early Power Estimation Checklist
Estimate power consumption with the Early Power Estimator (EPE)
spreadsheet to plan the cooling solution and power supplies before the logic design is
FPGA power consumption is an important design consideration and must be estimated accurately
to develop an appropriate power budget to design the power supplies, voltage regulators,
decouplers, heat sink, and cooling system. Power estimation and analysis have two significant
Thermal planning—The cooling solution must sufficiently dissipate the heat generated by
the device. In particular, the computed junction temperature must fall within normal device
Power supply planning—The power supplies must provide adequate current to support device
Power consumption in FPGA devices is dependent on the logic design. This
dependence can make power estimation challenging during the early board specification and
layout stages. The Intel EPE tool allows you to
estimate power utilization before the design is complete by processing information about the
device and the device resources that will be used in the design, as well as the operating
frequency, toggle rates, and environmental considerations. You can use the tool to obtain
thermal design parameters, with which you can perform detailed thermal simulation and cooling
If you do not have an existing design, estimate the number of device
resources used in your design and enter it manually. The EPE tool accuracy depends on your
inputs and your estimation of the device resources. If this information changes (during or
after your design is complete), your power estimation results are less accurate. If you have
an existing design or a partially-completed compiled design, use the Generate Early Power Estimator File command in the
Quartus® Prime software to provide input to the spreadsheet.
The EPE spreadsheet includes the Import Data macro, which parses the
information in the
Quartus® Prime-generated power estimation file
(.csv), or alternatively from an older version of the EPE, and
transfers it into the EPE tool. If you do not want to use the macro, you can transfer the data
into the EPE tool manually. You should enter additional resources to be used in the final
design manually if the existing
Quartus® Prime project represents
only a portion of your full design. You can edit the inputs to the EPE tool and add additional
device resources or adjust the parameters after importing the power estimation file
When the design is complete, the Power Analyzer tool in the
Quartus® Prime software provides more accurate estimation of power,
ensuring that thermal and supply budgets are not violated. For the most accurate power
estimation, use gate-level simulation results with an output file (.vcd) from a third-party simulation tool.
Note: To obtain the EPE tool, contact
your local sales representative.
Obtain thermal design power and thermal parameters from EPE.
Perform thermal simulation to determine a proper cooling solution.
Stratix® 10 is a multi-chip module, depending on package
configuration and design information, power distribution on all dies can be quite different.
This feature makes the
Stratix® 10 thermal characteristics
design dependent. EPE takes into consideration of your design input, and generates unique
thermal parameters for your design in the Thermal Page. You can get power consumption for each
die, thermal resistance for all dies (ψJC), cooling solution requirement
(ψCA), and maximum allowed package case temperature (Tcase).
The thermal analysis of the
device requires you use a Compact Thermal Model (contact your local
Intel® representatives to obtain the model) and perform simulation in a
Computational Fluid Dynamics (CFD) tool. The result of the CFD analysis gives the Tcase which should be lower than the required value in the EPE Thermal
Page. With the simulated Tcase, ψJC, and
total package power, you can obtain the actual junction temperature Tj, which needs to stay below your requirement, for example, 95˚C. You can adjust your
cooling solution (heat sink design, airflow, and so on) to optimize your thermal design.
Set up the temperature sensing diode (TSD) in your design to
measure the device junction temperature for thermal management.
Include offset values form EPE calculation to TSD reading.
Stratix® 10 devices have internal and external
temperature sensing capabilities. You can measure the junction temperature, TJ,
with the following methods:
Using internal TSD by instantiating the Temperature SensorIntel
Stratix 10 FPGA IP core.
Using external thermal diode designed to interface with third-party sensor chip. Ensure
the third-party sensor chip matches the external TSD specifications as documented in the
Stratix® 10 Device Datasheet.
Monitoring the actual junction temperature is crucial for thermal management.
Stratix® 10 devices include TSD on each die with embedded
analog-to-digital converter (ADC) circuitry. You can access the digital temperature readout
through the Temperature Sensor IP core.
Stratix® 10 TSD can self-monitor the device junction temperature and can be used with external circuitry for activities such as controlling air flow to the FPGA. This requires including the TSD circuitry by instantiating a Temperature Sensor IP core.
The flexibility in
Stratix® 10 design can lead to
non-uniform power distribution on transceiver dies. Therefore, the hotspot on the transceiver
dies may not necessarily be at the TSD location. This results in a temperature difference
between TSD readout and real junction temperature. EPE calculates this difference and reports
an offset value for each TSD. You need to add the offset values to your TSD reading to get the
actual junction temperature.
Stratix® 10 devices have an on-chip
voltage sensor. The sensor provides a 8-bit digital representation of the analog signal being
observed. This feature can be used for live monitoring of critical on-chip power supplies and
external analog voltage.
Table 15. Planning for Device Configuration Checklist
Consider whether you require multiple configuration
Follow the configuration guidelines and additional clock
requirements if your design is using PCIe, transceiver channels, HPS, High Bandwidth
Memory (HBM2) IP core, or SmartVID. Refer to the
Stratix® 10 Configuration User Guide and
Stratix® 10 Power Management User
Guide for the guidelines.
Intel strongly recommends using the
Stratix® 10 Reset Release IP in your design to provide a
known initialized state for your logic to begin operation. The Reset Release IP is
available in the
Quartus® Prime software version 19.1 and
later. Refer to the
Configuration User Guide for the guidelines.
Stratix® 10 devices are based on SRAM
cells. You must download configuration data to the
Stratix® 10 device each time the device powers up, because SRAM is volatile.
Consider whether you require multiple configuration schemes, such as one for debugging or
testing and another for the production environment.
Choosing the device configuration method early allows system and board designers to determine
what companion devices, if any, are required for the system. Your board layout also depends on
the configuration method you plan to use for the programmable device, because different
schemes require different connections.
Stratix® 10 devices offer advanced
configuration features, depending on your configuration scheme.
Stratix® 10 devices also include optional configuration pins and a
reconfiguration option that you should choose early in the design process (and set up in the
Quartus® Prime software), so you have all the information
required for your board and system design.
If you want to use the AS configuration mode with large device
densities, confirm there is a configuration device available that is large enough for
your target FPGA density.
Intel low-voltage quad-serial configuration (EPCQ-L)
devices are used in the AS configuration scheme.
Serial configuration devices can be programmed using a
Intel® FPGA Download Cable II or
Intel® FPGA Ethernet Cable II download cable with the
Quartus® Prime software through the active serial interface.
Alternatively, you can use supported third-party programmers such as BP
Microsystems and System General, or a microprocessor with the SRunner software driver. SRunner
is a software driver developed for embedded serial configuration device programming that
designers can customize to fit in different embedded systems.
Serial configuration devices do not directly support the JTAG interface; however, you can
program the device with JTAG download cables using the
Stratix® 10 FPGA as a bridge between the JTAG interface and the configuration
device, allowing both devices to use the same JTAG interface.
Programming the EPCQ-L from JTAG using the
FPGA as a bridge is slower than using the standard AS interface.
Quartus® Prime programmer supports configuration of the
Stratix® 10 devices directly using JTAG interfaces with
Intel programming download cables. You can download
design changes directly to the device with Intel
download cables, making prototyping easy and enabling you to make multiple design iterations
in quick succession. You can use the same download cable to program configuration devices on
the board and use JTAG debugging tools such as the Signal Tap Embedded Logic Analyzer.
Ensure your configuration scheme and board support the required
features: design security, remote upgrades, single event upset (SEU)
This section describes
Stratix® 10 configuration features
and how they affect your design process.
Configuration Bitstream Compression
Configuration bitstream compression is always enabled in
Stratix® 10 configuration. The
Quartus® Prime software generates configuration files with compressed configuration
data. This compressed file reduces the storage requirements in the configuration device or
flash memory, and decreases the time required to transmit the configuration bitstream to the
Stratix® 10 device.
Due to compressed configuration bitstream, passive configuration schemes
Avalon®-ST ×8, ×16, and ×32 might require the external
configuration host to pause sending configuration data by deasserting the AVST_READY signal.
Design Security Using Configuration Bitstream Encryption
The design security feature ensures that
Stratix® 10 designs are protected from copying, reverse engineering, and
Stratix® 10 devices have the ability to
decrypt configuration bitstreams using the AES algorithm, an industry standard encryption
algorithm that is FIPS-197 certified.
devices have a design security feature which utilizes a 256-bit security key.
The design security feature is available in the all configuration schemes
supported in the
Stratix® 10 devices.
Dedicated circuitry is built into
Stratix® 10 devices for error detection and correction. When enabled, this
feature checks for SEUs continuously and automatically. This allows you to confirm that the
configuration data stored in an
Stratix® 10 device is
correct and alerts the system to a configuration error.
When using the SEU mitigation features, an SDM pin is used to implement
the SEU_ERROR function. This pin flags errors for your
system to take appropriate actions. Prior to compiling your design, enable the SEU_ERROR function and select an unused SDM pin to implement the
SEU_ERROR function in the
Quartus® Prime software.
Quartus® Prime Configuration Settings
configuration options when you plan your board and system design.
There are several configuration options that you can set in the
Quartus® Prime Standard Edition software before compilation to generate
configuration or programming files. Your board and system design are affected by these
settings and pins, so consider them in the planning stages. Set the options on the General
category of the Device and Pin Options dialog box.
Optional Configuration Pins
Table 21. Optional Configuration Pins Checklist
Plan the board design to support optional configuration pins as
You can enable the following optional configuration pins:
OSC_CLK_1—Must be connected to a 25 MHz,
100 MHz, or 125 MHz source if used.
Stratix® 10 devices use OSC_CLK_1 pin as
the reference clock for transceiver calibration. You must provide a stable and free running
clock input at this pin.
Plan the dual purpose pins that can function as configuration
pins and user I/O pins.
The below configuration pins used for the
and ×32 configuration schemes can optionally be used as user I/O pins after configuration has
completed. Enable the pins to function as dual purpose pins in the
Quartus® Prime software prior to compilation, if desired.
On-chip debugging is an optional step in the design flow, and different
debugging tools work better for different systems and different designers. Evaluate on-chip
debugging options early in your design process to ensure that your system board,
Quartus® Prime project, and design are able to support the appropriate
options. Planning can reduce time spent debugging, and eliminates design changes later to
accommodate your preferred debugging methodologies. Adding debug pins might not be enough,
because of internal signal accessibility and I/O pin accessibility on the device. First,
select your preferred debugging tools.
Take advantage of on-chip debugging features to analyze internal
signals and perform advanced debugging techniques.
Quartus® Prime portfolio of verification
tools includes the following in-system debugging features:
Signal Probe incremental
routing—Quickly routes internal signals to I/O pins without affecting the routing of the
original design. Starting with a fully routed design, you can select and route signals for
debugging to either previously reserved or currently unused I/O pins.
Signal Tap Embedded Logic
Analyzer—Probes the state of internal and I/O signals without the use of external equipment
or extra I/O pins, while the design is running at full speed in an FPGA device. Defining
custom trigger-condition logic provides greater accuracy and improves the ability to isolate
problems. It does not require external probes or changes to the design files to capture the
state of the internal nodes or I/O pins in the design; all captured signal data is stored in
the device memory until you are ready to read and analyze the data. The Signal Tap Embedded Logic Analyzer works best for synchronous
interfaces. For debugging asynchronous interfaces, consider using Signal Probe or an external logic analyzer to view the signals more accurately.
Signal Tap may affect routing of the original
Logic Analyzer Interface—Enables you to connect and transmit internal FPGA
signals to an external logic analyzer for analysis, allowing you to take advantage of
advanced features in your external logic analyzer or mixed signal oscilloscope. You can use
this feature to connect a large set of internal device signals to a small number of output
pins for debugging purposes and it can multiplex signals with design I/O pins if
In-System Memory Content Editor—Provides read and write access to
in-system FPGA memories and constants through the JTAG interface, so you can test changes to
memory content and constant values in the FPGA while the device is functioning in the
In-System Sources and Probes—Sets up custom register chains to drive or
sample the instrumented nodes in your logic design, providing an easy way to input simple
virtual stimuli and capture the current value of instrumented nodes.
Intel® FPGA IP core—Enables you to build your own system-level
debugging infrastructure, including both processor-based debugging solutions and debugging
tools in the software for system-level debugging. You can instantiate the SLD_VIRTUAL_JTAG
Intel® FPGA IP core directly in your HDL code to provide one or more
transparent communication channels to access parts of your FPGA design using the JTAG
interface of the device.
EMIF Debug toolkit—Tcl-based graphical user interface communicating via a
JTAG connection to enable external memory interface on the circuit board to retrieve
calibration status and debug information. The Driver Margining feature of the tool kit
allows you to measure margins on your memory interface using a driver with arbitrary traffic
patterns. Tcl-based graphical user interface that provides access to memory calibration data
gathered by the
Nios® II sequencer, via a JTAG connection.
The Toolkit allows you to mask ranks for calibration, and to request recalibration of the
interface. The Driver Margining feature of the toolkit allows you to measure margins on the
memory interface using a driver with arbitrary traffic patterns. The EMIF Toolkit can
communicate with several different memory interfaces on the same device, but only one at a
Transceiver Toolkit—Uses System Console technology to help FPGA and board
designers validate transceiver link signal integrity real time in a system and improve board
bring-up time. Test for bit-error rate (BER) while simultaneously running multiple links at
your target data rate to validate your board design with Transceiver Toolkit. Tune
transceiver analog settings for optimal link performance while using different test metrics
to quantify results. Simultaneously test multiple devices across one or more boards using
link tests in the Transceiver Toolkit GUI.
Table 24. Planning Guidelines for Debugging Tools Checklist
Select on-chip debugging schemes early to plan memory and logic
requirements, I/O pin connections, and board connections.
If you want to use Signal Probe incremental routing, the Signal Tap Embedded
Logic Analyzer, Logic Analyzer Interface, In-System Memory Content Editor, In-System
Sources and Probes, or Virtual JTAG IP core, plan your
system and board with JTAG connections that are available for debugging.
Plan for the small amount of additional logic resources used to
implement the JTAG hub logic for JTAG debugging features.
For debugging with the Signal Tap Embedded Logic Analyzer, reserve device memory resources to
capture data during system operation.
Reserve I/O pins for debugging with Signal Probe or the Logic Analyzer Interface so you do not have to change
the design or board to accommodate debugging signals later.
Ensure the board supports a debugging mode where debugging
signals do not affect system operation.
Incorporate a pin header or mictor connector as required for an
external logic analyzer or mixed signal oscilloscope.
To use debug tools incrementally and reduce compilation time,
ensure incremental compilation is on so you do not have to recompile the design to
modify the debug tool.
To use the Virtual JTAG IP core for
custom debugging applications, instantiate it in the HDL code as part of the design
To use the In-System Sources and Probes feature, instantiate the
IP core in the HDL code.
To use the In-System Memory Content Editor for RAM or ROM blocks,
turn on the Allow In-System Memory Content
Editor to capture and update content independently of the system clock
option for the memory block in the IP catalog.
If you intend to use any of the on-chip debugging tools, plan for the tool(s) when developing
the system board,
Quartus® Prime project, and design.
Pin Connection Considerations for Board Design
When designing the interfaces to the
Stratix® 10 device,
various factors can affect the PCB design.
Design board for power-up: All
Stratix® 10 GPIO pins are tri-stated until the device is configured and
configuration pins drive out. The transceiver pins are at high impedance before the
device periphery could get programmed. Once the periphery is programmed, the
termination and Vcm are set immediately after transceiver
calibration is complete.
Design voltage power supply ramps to be monotonic.
Set POR time to ensure power supplies are stable.
Design power sequencing and voltage regulators for best device
reliability. Connect the GND between boards before connecting the power
The minimum current requirement for the power-on-reset (POR) supplies must be available
during device power-up.
Stratix® 10 device has Power-On Reset Circuitry,
which keeps the device in a reset state until the power supply outputs are within the
recommended operating range. The device must reach the recommended operating range within the
maximum power supply ramp time. If the ramp time is not met, the device I/O pins and
programming registers remain tri-stated and device configuration fails. For the
Stratix® 10 device to exit POR, you must power the
VCCBAT power supply even if you do not use the volatile key.
Stratix® 10 devices, a pin-selectable option (MSEL)
allows you to select between a typical POR time setting of 4 ms or 100 ms. In both cases, you
can extend the POR time by using an external component to assert the nSTATUS
pin low. Extend POR time if the board cannot meet the maximum power ramp time specifications
to ensure the device configures properly and enters user mode.
Stratix® 10 devices have power-up
sequencing and power-down sequencing requirements. You should consider the power-up timing and
power-down timing for each rail in order to meet the power sequencing requirements.
Intel uses GND as a reference for I/O buffer
designs. Connecting the GND between boards before connecting the power supplies prevents the
GND on your board from being pulled up inadvertently by a path to power through other
components on your board. A pulled-up GND could otherwise cause an out-of-specification I/O
voltage or current condition with the Intel
Table 26. Power Pin Connections and Power Supplies Checklist
Connect all power pins correctly as specified in the
Stratix® 10 Device Family Pin
Connect VCCIO pins and VREF
pins to support each bank’s I/O standards.
Explore unique requirements for FPGA power pins or other power
pins on your board, and determine which devices on your board can share a power
Follow the suggested power supply sharing and isolation guidance,
and the specific guidelines for each pin in the
Stratix® 10 Device Family Pin Connection
Refer to AN 692: Power Sequencing Considerations for
Arria® 10 and
Stratix® 10 Devices to understand the power sequencing design
Stratix® 10 devices require various voltage supplies
depending on your design requirements.
Stratix® 10 devices support a wide range
of industry I/O standards. The device output pins do not meet the I/O standard specifications
if the VCCIO level is out of the recommended operating range for
the I/O standard.
Voltage reference (VREF) pins serve as voltage references for certain I/O
standards. The VREF pin is used mainly for a voltage bias and does not source
or sink much current. The voltage can be created with a regulator or a resistor divider
The VREFP_ADC pin is not a power supply pin. It provides the reference
voltage for the ADC for the voltage sensor. For better voltage sensor performance, connect the
VREFP_ADC pin to an external reference 1.25 V source. Connecting the
VREFP_ADC pin to GND actives an on-chip reference source.
Use the PDN tool to plan your power distribution netlist and
Board decoupling is important for improving overall power supply integrity while ensuring the
rated device performance.
Stratix® 10 devices include on-die
decoupling capacitors to provide high-frequency decoupling. These low-inductance capacitors
suppress power noise for excellent power integrity performance, and reduce the number of
external PCB decoupling capacitors, saving board space, reducing cost, and greatly simplifying
Intel has created an easy-to-use
power distribution network (PDN) design tool that optimizes the board-level PDN graphically.
The purpose of the board-level PDN is to distribute power and return currents from the voltage
regulating module (VRM) to the FPGA power supplies. By using the PDN tool, you can quickly
arrive at an optimized PDN decoupling solution for your specific design.
For each power supply, PDN designers must choose a network of bulk and decoupling capacitors.
While SPICE simulation could be used to simulate the circuit, the PDN design tool provides a
fast, accurate, and interactive way to determine the right number of decoupling capacitors for
optimal cost and performance trade-offs.
PLL Board Design Guidelines
Table 28. PLL Board Design Guidelines Checklist
Connect all PLL power pins to reduce noise even if the design
does not use all the PLLs.
Power supply nets should be provided by an isolated power plane,
a power plane cut out, or thick trace of at least 20 mils.
Plan your board design when you design a power system for PLL usage and to minimize jitter,
because PLLs contain analog components embedded in a digital device.
Check that all configuration pin connections and
pull-up/pull-down resistors are set correctly for your configuration schemes.
Depending on your configuration scheme, different pull-up/pull-down resistor
or signal integrity requirements might apply. Some configuration pins also have specific
requirements if unused. It is very important to connect the configuration pins correctly. The
following guidelines address the common issues.
Table 31. Configuration Pin Voltage Level Checklist
Ensure VCCIO_SDM and VCCIO of the
configuration pins match the voltage level of the external devices used for
Configuration pins from the
device connect to external devices, for example the EPCQ-L configuration device,
Avalon®-ST host, or SD/MMC flash memories. The voltage level of
the configuration pins need to match the voltage level of the devices connected to them. The
JTAG and SDM I/Os used as configuration pins are powered by the VCCIO_SDM supply. For
Avalon®-ST ×32 and ×16
configuration schemes, the AVST_CLK, AVST_VALID, and AVST_DATA pins are powered by the
VCCIO of the I/O bank in which the pins reside in. When using the
Avalon®-ST ×32 or ×16 configuration scheme, VCCIO of the I/O bank which the AVST_CLK, AVST_VALID, and AVST_DATA pins are located in, must match the VCCIO_SDM
Clock Trace Signal Integrity
Table 32. Clock Trace Signal Integrity Checklist
Design configuration clock traces to be noise-free.
Board trace for clocks used in configuration, for example TCK, AS_CLK, AVSTx8_CLK, AVST_CLK, SDMMC_CFG_CCLK, and OSC_CLK_1 clock input, should
produce clean signals with no overshoot, undershoot, or ringing. When designing the board, lay
out the configuration clock traces with the same techniques used to lay out a clock line. Any
overshoot, undershoot, ringing, or other noise on the clock signal can cause configuration
failure. Make sure to have clock routing as stripline. Keep the clock routing away from any
high-speed signals to isolate the clock signals from other signals.
Table 33. JTAG Pins Checklist
Connect JTAG pins to a stable voltage level if not in
Because JTAG configuration takes precedence over all other configuration
methods, the JTAG pins should not be left floating or toggling during configuration if you do
not use the JTAG interface. If you are using the JTAG interface, adhere to the following
JTAG Pin Connections
Table 34. JTAG Pin Connections Checklist
Connect JTAG pins correctly to the download cable header. Ensure
the pin order is not reversed.
To disable the JTAG state machine during power-up, pull the
TCK pin low through a resistor to ensure that an
unexpected rising edge does not occur on the TCK
Pull the TMS and TDI pins high through a resistor.
A device operating in JTAG mode uses four required pins—TDI, TDO, TMS, and
TCK. The TCK pin has an
internal weak pull-down resistor, while the TDI and TMS pins have weak internal pull-up resistors.
If you have more than one device in the chain, connect the TDO pin of a
device to the TDI pin of the next device in the chain.
Noise on the JTAG pins during configuration, user mode, or power-up can cause the device to
go into an undefined state or mode.
Download Cable Operating Voltage
Table 35. Download Cable Operating Voltage Checklist
Ensure the download cable and JTAG pin voltages are compatible
because the download cable interfaces with the JTAG pins of your device.
The operating voltage supplied to the Intel download
cable by the target board through the 10-pin header determines the operating voltage level of
the download cable.
JTAG pins in the
Stratix® 10 device are
powered up by VCCIO_SDM. In a JTAG chain containing devices with
different VCCIO levels, ensure that the VIL max, VIH min, and the maximum VI specifications of the device JTAG input pins are not violated. Level shifter might
be required between devices to meet the voltage specifications of the devices input pin.
JTAG Signal Buffering
Table 36. JTAG Signal Buffering Checklist
Buffer JTAG signals per the recommendations, especially for
connectors or if the cable drives more than three devices.
If your device is in a configuration chain, ensure all devices in
the chain are connected properly.
You might have to add buffers to a JTAG chain, depending on the JTAG signal integrity,
especially the TCK signal, because it is the JTAG clock and the fastest
switching JTAG signal. Intel recommends buffering the
signals at the connector because cables and board connectors tend to make bad transmission
lines and introduce noise to the signals. After this initial buffer at the connector, add
buffers as the chain gets longer or whenever the signals cross a board connector.
If a cable drives three or more devices, buffer the JTAG signal at the cable
connector to prevent signal deterioration. This also depends on the board layout, loads,
connectors, jumpers, and switches on the board. Anything added to the board that affects the
inductance or capacitance of the JTAG signals increases the likelihood that a buffer should be
added to the chain.
Each buffer should drive no more than eight loads for the TCK and
TMS signals, which drive in parallel. If jumpers or switches are added to
the path, decrease the number of loads.
MSEL Configuration Mode Pins
Table 37. MSEL Configuration Mode Pins Checklist
Connect the SDM pins with MSEL function to select the
configuration scheme; do not leave them floating. Do not hardwire the pins to
VCCIO_SDM or GND if they have other configuration functions based on the
configuration scheme selected.
Select the configuration scheme by pulling the SDM pins with MSEL function high or low with
external resistors. JTAG configuration is always available, regardless of the MSEL settings.
The SDM pins with MSEL function are powered by the VCCIO_SDM power supply,
and they have internal weak pull-up resistors.
During POR and reconfiguration, the SDM pins with MSEL function must be at LVTTL
VIL and VIH levels to be considered as logic low and logic high,
respectively. The SDM pins used for MSEL function also have other configuration functions,
depending on the configuration schemes used. Do not hardwire the SDM pins with MSEL function
to VCCIO_SDM or GND without pull-up or pull-down resistors, if they are needed for
the configuration scheme used.
Other Configuration Pins
Table 38. Other Configuration Pins Checklist
Use the SDM pins which have multiple configuration functions if
power management function is required.
When a –V device is used, you must enable the SmartVID connection between the
device and the VCC voltage regulator to allow the FPGA to directly control its core
voltage requirements. Refer to the
Stratix® 10 Device Family Pin Connection Guidelines and
Stratix® 10 Power Management User Guide for the pin connections
Most of the SDM pins have multiple configuration functions, depending on the configuration
schemes used. Some SDM pins also have power management functions. If power management function
is required, choose the SDM pins which do not need to be used for configuration to implement
the power management function.
Connect the SDM pins on your board to the external configuration host or configuration device
based on the configuration scheme to be used. If more than one configuration scheme are used,
ensure there is no contention between configuration host or configuration devices connected to
the SDM pins.
Table 39. Board-Related
Quartus® Prime Settings
Set the settings for the FPGA I/O pins correctly and plan for the
functionality during board design.
Quartus® Prime software provides options for the FPGA I/O
pins that you should consider during board design. Ensure that these options are set correctly
Quartus® Prime project is created, and plan for the
functionality during board design.
Table 40. Unused Pins Checklist
Specify the reserved state for unused I/O pins.
Carefully check the pin connections in the
Quartus® Prime software-generated .pin
file. Do not connect RESERVED pins.
You can specify the state of unused pins in the
Quartus® Prime software to allow flexibility in the board design by choosing one of the
five allowable states for Reserve all unused pins on
the Unused Pins category in the Device and
Pin Options dialog box:
As inputs tri-stated
As output driving ground
As outputs driving an unspecified signal
As input tri-stated with bus-hold circuitry
As input tri-stated with weak pull-up
The common setting is to set unused pins As inputs tri-stated with weak
pull-up. To improve signal integrity, set the unused pins to As
output driving ground. Doing this reduces inductance by creating a shorter
return path and reduces noise on the neighboring I/Os. This approach should not be used if
this results in many via paths causing congestion for signals under the device.
To reduce power dissipation, set clock pins and other unused I/O pins As inputs
tri-stated, and tie them to ground.
Signal Integrity Considerations
Signal integrity considerations include detailed board design guidelines, as
well as a few guidelines related to VREF pins, SSN, and I/O
High-Speed Board Design
Table 41. High-Speed Board Design Checklist
Refer to the Board Design Resource Center.
If your design has high-speed signals, especially with
Stratix® 10 GX/SX device high-speed transceivers, the board design has a major
impact on the signal integrity in the system.
Break out large bus signals on board layers close to the device
to reduce cross talk.
Route traces orthogonally if two signal layers are next to each
other, if possible. Use a separation of two to three times the trace width.
SSN is a concern when too many pins (in close proximity) change voltage levels at the same
time. Noise generated by SSN can reduce the noise margin and cause incorrect switching.
Although SSN is dominant on the device package, plan the board layout according to the board
layout recommendations in the PCB guidelines can help with noise reduction.
Check I/O termination and impedance matching for chosen I/O
standards, especially for voltage-referenced standards.
Voltage-referenced I/O standards require both an VREF and a termination voltage
(VTT). The reference voltage of the receiving device tracks the termination
voltage of the transmitting device. Each voltage-referenced I/O standard requires a unique
Although single-ended, non-voltage-referenced I/O standards do not require termination,
impedance matching is necessary to reduce reflections and improve signal integrity.
Stratix® 10 on-chip series and parallel termination
provides the convenience of no external components. Alternatively, you can use external
pull-up resistors to terminate the voltage-referenced I/O standards such as SSTL and HSTL.
Differential I/O standards typically require a termination resistor between the two signals
at the receiver. The termination resistor must match the differential load impedance of the
Stratix® 10 devices provide an optional
on-chip differential resistor when using LVDS.
Board-Level Simulation and Advanced I/O Timing Analysis
Table 45. Board-Level Simulation and Advanced I/O Timing Analysis
Perform board-level simulation using IBIS models (when
Configure board trace models for
Quartus® Prime advanced I/O timing analysis.
To ensure that the I/O signaling meets receiver threshold levels on your board setup, perform
full board routing simulation with third-party board-level simulation tools using an IBIS
When this feature is available in the
Quartus® Prime software,
select IBIS under Board-level signal integrity
analysis on the Board-Level page in EDA Tool
Settings of the Settings dialog box.
When you include an FPGA device with high-speed interfaces in a board design, knowing the
signal integrity and board routing propagation delay is vital for proper system operation. You
should analyze board level timing as part of the I/O and board planning, especially for
You can configure board trace models of selected I/O standards and generate
“board-aware” signal integrity reports with the
software. When Enable Advanced I/O Timing is turned on
(Timing Analyzer page in the Settings dialog box), the Timing Analyzer
uses simulation results for the I/O buffer, package, and the board trace model to generate
more accurate I/O delays and extra reports to give insight into signal behavior at the system
level. You can use these advanced timing reports as a guide to make changes to the I/O
assignments and board design to improve timing and signal integrity.
Planning and allocating I/O and clock resources is an important task with the high pin counts
and advanced clock management features in
devices. Various considerations are important to effectively plan the available I/O resources
to maximize utilization and prevent issues related to signal integrity. Good clock management
systems are also crucial to the performance of an FPGA design.
The I/O and clock connections of your FPGA affect the rest of your system and board design,
so it is important to plan these connections early in your design cycle.
Making FPGA Pin Assignments
Table 46. Making FPGA Pin Assignments Checklist
Quartus® Prime Pin Planner
to make pin assignments.
Quartus® Prime Fitter messages
and reports for sign-off of pin assignments.
Verify that the
Quartus® Prime pin
assignments match those in the schematic and board layout tools.
Plan interfaces and device periphery using the Interface Planner. After design synthesis, use the Interface Planner to rapidly define a legal device floorplan. Planning
using the Interface Planner involves initialization of the Interface Planner, reconciliation of project assignments, placement of
periphery elements and clocks, and export of plan constraints to your
Quartus® Prime project.
Quartus® Prime Pin Planner GUI, you can identify I/O
banks, VREF groups, and differential pin pairings to help you through the I/O
planning process. Right-click in the Pin Planner spreadsheet interface and click the
Pin Finder to search for specific pins. If migration devices are
selected, the Pin Migration view highlights pins that change function in the migration device
when compared to the currently selected device.
You have the option of importing a Microsoft Excel spreadsheet into the
Quartus® Prime software to start the I/O planning process if you
normally use a spreadsheet in your design flow. You can also export a spreadsheet compatible
(.csv) file containing your I/O assignments when all pins are
When you compile your design in the
Quartus® Prime software, I/O
Assignment Analysis in the Fitter validates that the assignments meet all the device
requirements and generates messages if there are any problems.
Quartus® Prime designers can then pass the pin location
information to PCB designers. Pin assignments between the
Quartus® Prime software and your schematic and board layout tools must match to ensure
the design works correctly on the board where it is placed, especially if changes to the
pin-out must be made. The Pin Planner is integrated with certain PCB design EDA tools and can
read pin location changes from these tools to check the suggested changes. When you compile
your design, the
Quartus® Prime software generates the
.pin file. You can use this file to verify that each pin is correctly
connected in the board schematics.
Table 47. Early Pin Planning and I/O Assignment Analysis Checklist
Use the Create Top-Level Design File
command with I/O Assignment Analysis to check the I/O assignments before the design is
In many design environments, FPGA designers want to plan top-level FPGA I/O pins early so
that board designers can start developing the PCB design and layout. The FPGA device’s I/O
capabilities and board layout guidelines influence pin locations and other types of
assignments. In cases where the board design team specifies an FPGA pin-out, it is crucial
that you verify pin locations in the FPGA place-and-route software as soon as possible to
avoid board design changes.
Starting FPGA pin planning early improves the confidence in early board layouts, reduces the
chance of error, and improves the design’s overall time to market. You can create a
preliminary pin-out for an Intel FPGA using the
Quartus® Prime Pin Planner before the source code is
Early in the design process, the system architect typically has information about the
standard I/O interfaces (such as memory and bus interfaces), IP cores to be used in the
design, and any other I/O-related assignments defined by system requirements.
The Pin Planner Create/Import IP Core feature interfaces with the IP catalog, and enables you
to create or import custom IP cores that use I/O interfaces. Enter PLL and LVDS blocks,
including options such as dynamic phase alignment (DPA), because options affect the pin
placement rules. When you have entered as much I/O-related information as possible, generate a
top-level design netlist file using the Create Top-Level Design File
command in the Pin Planner. You can use the I/O analysis results to change pin assignments or
IP parameters and repeat the checking process until the I/O interface meets your design
requirements and passes the pin checks in the
When planning is complete, the preliminary pin location information can be passed to PCB
designers. When the design is complete, use the reports and messages generated by the
Quartus® Prime Fitter for the final sign-off of the pin assignments.
Stratix® 10 I/O pins are designed for
ease of use and rapid system integration, while simultaneously providing high bandwidth.
Independent modular I/O banks with a common bank structure for vertical migration lend
efficiency and flexibility to the high speed I/O.
The following guidelines provide information pertaining to I/O features and
Plan the I/O signaling type based on the system
Allow the software to assign locations for the negative pin in
differential pin pairs.
Stratix® 10 devices support a wide range
of industry I/O standards, including single-ended, voltage-referenced single-ended, and
differential I/O standards. Follow these general guidelines when you select a signaling
Single-ended I/O signaling provides a simple rail-to-rail interface. Its speed is limited by
the large voltage swing and noise. Single-ended I/Os do not require termination, unless
reflection in the system causes undesirable effects.
Voltage-referenced signaling reduces the effects of simultaneous switching outputs (SSO) from
pins changing voltage levels at the same time (for example, external memory interface data and
address buses). Voltage-referenced signaling also provides an improved logic transition rate
with a reduced voltage swing, and minimizes noise caused by reflection with a termination
requirement. However, additional termination components are required for the reference voltage
Differential signaling eliminates the interface performance barrier of single-ended and
voltage-referenced signaling, with superior speed using an additional inverted closely-coupled
data pair. Differential signaling also avoids the requirement for a clean reference voltage.
This is possible because of a lower swing voltage and noise immunity with a common mode noise
rejection capability. Considerations for this implementation include the requirements for a
dedicated PLL to generate a sampling clock, and matched trace lengths to eliminate the phase
difference between an inverted and non-inverted pair.
Stratix® 10 I/O pins are organized in pairs to support
differential standards. Each I/O pin pair can support differential input or output operations,
with the exception of certain clock pins that support differential input operations only. In
your design source code, define just one pin to represent a differential pair, and make a pin
assignment for this positive end of the pair. When you specify a differential I/O standard,
Quartus® Prime software automatically places the
corresponding negative pin.
Selectable Standards and Flexible I/O Banks
Table 49. Selectable Standards and Flexible I/O Banks Checklist
Select a suitable signaling type and I/O standard for each I/O
pin. The I/O banks are located in I/O columns. Each I/O bank contains its own PLL,
DPA, and SERDES circuitries.
Ensure that the appropriate I/O standard support is supported in
the targeted I/O bank.
Place I/O pins that share voltage levels in the same I/O
Verify that all output signals in each I/O bank are intended to
drive out at the bank’s VCCIO voltage level.
Verify that all voltage-referenced signals in each I/O bank are
intended to use the bank’s VREF voltage level.
Check the I/O bank support for LVDS and transceiver
Stratix® 10 I/O pins are arranged in
groups called modular I/O banks. Be sure to use the correct dedicated pin inputs for signals
such as clocks and global control signals.
The board must supply each bank with one VCCIO voltage level for every
VCCIO pin in a bank. Each I/O bank is powered by the VCCIO
pins of that particular bank, and is independent of the VCCIO pins of other
I/O banks. A single I/O bank supports output signals that are driving at the same voltage as
the VCCIO. An I/O bank can simultaneously support any number of input signals with
different I/O standards.
To accommodate voltage-referenced I/O standards, each I/O bank supports multiple
VREF pins feeding a common VREF bus. Set the
VREF pins to the correct voltage for the I/O standards in the bank. Each
I/O bank can only have a single VCCIO voltage level and a single VREF
voltage level at a given time. If the VREF pins are not used as voltage
references, they cannot be used as generic I/O pins and should be tied to VCCIO of
that same bank or GND.
An I/O bank including single-ended or differential standards can support voltage-referenced
standards as long as all voltage-referenced standards use the same VREF setting.
Voltage-referenced bi-directional and output signals must drive out at the I/O bank’s
VCCIO voltage level.
Different I/O banks include different support for LVDS signaling, and the
Stratix® 10 transceiver banks include additional support. There
are two types of I/O banks, LVDS and 3 V.
The LVDS I/O bank supports differential and single-ended I/O standards up to 1.8 V. The LVDS
I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel
input/output termination between the two pins. You can use each LVDS channel as transmitter or
The 3 V I/O bank supports only single-ended I/O standards up to 3 V. Each adjacent I/O pair
also supports Differential SSTL and Differential HSTL I/O standards. The single-ended output
of the 3 V I/O has the same set of features as the single-ended output of the DDR I/O IP,
except the programmable pre-emphasis feature.
Use the External Memory InterfacesIntel
Stratix 10 FPGA IP core for each memory interface, and follow
connection guidelines/restrictions in the appropriate documentation.
For a given bank, most memory pins are tied to a dedicated
location. Refer to the
Stratix® 10 Device Family Pin Connection Guidelines for pin
Stratix® 10 devices provide an efficient architecture to
quickly and easily fit wide external memory interfaces with their small modular I/O banks. The
Stratix® 10 FPGA can support DDR external memory on any
I/O banks on all sides of the device that do not support transceivers.
The self-calibrating External Memory Interfaces IP
core is optimized to take advantage of the
Stratix® 10 I/O
structure. The External Memory Interfaces IP core allows you to set
external memory interface features and helps set up the physical interface (PHY) best suited
for your system. When you use the Intel memory
Intel® FPGA IP functions, the External Memory Interfaces IP core is instantiated automatically. If you
design multiple memory interfaces into the device using Intel FPGA IP core, generate a unique interface for each instance to ensure good
results instead of designing it once and instantiating it multiple times.
The data strobe DQS and data DQ pin locations are fixed in
Stratix® 10 devices. Before you design your device pin-out, refer to the memory
interface guidelines for details and important restrictions related to the connections for
these and other memory-related signals.
You can implement a protocol that is not supported by External Memory Interfaces IP core by using the PHY Lite for Parallel InterfacesIntel
Stratix 10 FPGA IP core.
Address and command pins within the address/command bank must follow a fixed pin-out scheme,
as defined in the <variation_name>_readme.txt file
generated with your IP core. The pin-out scheme varies according to the topology of the memory
interface. The pin-out scheme is a hardware requirement that you must follow. Some schemes
require three lanes to implement address and command pins, while others require four
Table 51. Dual-Purpose and Special Pin Connections Checklist
Make dual-purpose pin settings and check for any restrictions
when using these pins as regular I/O.
Stratix® 10 devices allow I/O flexibility with
dual-purpose configuration pins. You can use dual-purpose configuration pins as general I/Os
after device configuration is complete. Select the desired setting for each of the
dual-purpose pins on the Dual-Purpose Pins category of the
Device and Pin Options dialog box. Depending on the configuration
scheme, these pins can be reserved as regular I/O pins, as inputs that are tri-stated, as
outputs that drive ground, or as outputs that drive an unspecified signal.
You can also use dedicated clock inputs, which drive the programmable clock routing networks,
as general-purpose input pins if they are not used as clock pins. When you use the clock
inputs as general inputs, I/O registers use ALM-based registers because the clock input pins
do not include dedicated I/O registers.
The device-wide reset and clear pins are available as design I/Os if they are not
Intel Stratix 10 I/O Features
Stratix® 10 I/O Features
Check available device I/O features that can help I/O interfaces:
current strength, slew rate, I/O delays, open-drain, bus hold, programmable pull-up
clamping diodes, programmable pre-emphasis, and
Consider on-chip termination (OCT) features to save board
Verify that the required termination scheme is supported for all
Choose the appropriate mode of DPA, non-DPA, or soft-CDR for
high-speed LVDS interfaces.
Stratix® 10 bi-directional I/O element (IOE) features
support rapid system integration while simultaneously providing the high bandwidth required to
maximize internal logic capabilities and system-level performance. Advanced features for
device interfaces assist in high-speed data transfer into and out of the device and reduce the
complexity and cost of the PCB.
Intel recommends performing an IBIS or SPICE
simulations to optimize your design settings.
Use the correct dedicated clock pins and routing signals for
clock and global control signals.
Use the device PLLs for clock management.
Analyze input and output routing connections for each PLL and
clock pin. Ensure PLL inputs come from the dedicated clock pins or from another
The first stage in planning your clocking scheme is to determine your system clock
requirements. Understand your device’s available clock resources and correspondingly plan the
design clocking scheme. Consider your requirements for timing performance, and how much logic
is driven by a particular clock.
Stratix® 10 devices provide dedicated low-skew and high
fan-out routing networks.
The dedicated clock pins drive the clock network directly, ensuring lower skew than other I/O
pins. Use the dedicated routing network to have a predictable delay with less skew for high
fan-out signals. You can also use the clock pins and clock network to drive control signals
like asynchronous reset.
Connect clock inputs to specific PLLs to drive specific low-skew routing networks. Analyze
the global resource availability for each PLL and the PLL availability for each clock input
Stratix® 10 devices contain dedicated resources for
distributing signals throughout the fabric with balanced delay. These resources are typically
used for clock signals. You can also use these resources for other signals with low-skew
Stratix® 10 devices, these resources are
implemented as a programmable clock routing, which allows for the implementation of low-skew
clock networks of variable size.
If your system requires more clock or control signals than are available in the target
device, consider cases where the dedicated clock resource could be spared, particularly low
fan-out and low-frequency signals where clock delay and clock skew do not have a significant
impact on the design performance. Use the Global Signal assignment in
Quartus® Prime Assignment Editor to select the type of global
routing, or set the assignment to Off to specify that the signal should
not use any global routing resources.
Enable PLL features and check settings in the parameter
Based on your system requirements, define the required clock frequencies for
your FPGA design, and the input frequencies available to the FPGA. Use these specifications to
determine your PLL scheme. Use the
Quartus® Prime parameter
editor to enter your settings in IOPLL
Intel® FPGA IP core, and check the results to verify whether particular
features and input/output frequencies can be implemented in a particular PLL.
Stratix® 10 devices contain fractional
PLLs in addition to I/O PLLs. You can configure fractional PLLs as integers or as enhanced
You can use I/O PLLs and fractional PLLs to reduce the number of oscillators
required on the board, as well as to reduce the clock pins used in the FPGA by synthesizing
multiple clock frequencies from a single reference clock source. In addition, you can use
fractional PLLs for transmit clocking for transceivers.
Stratix® 10 device PLLs are feature rich, and support
advanced capabilities such as clock feedback modes, switchover, and dynamic phase
Check that the PLL offers the required number of clock outputs
and use dedicated clock output pins.
You can connect clock outputs to dedicated clock output pins or dedicated clock networks.
There is no dedicated clock out pin for fractional PLL. I/O PLL can connect to a clock network
or a dedicated clock pin.
Clock Control Features
Table 57. Clock Control Features Checklist
Use the clock control block for clock selection and
Stratix® 10 devices uses these clock control features:
clock gating and clock divider. The clock from the I/O PLL output can be gated dynamically.
These clock signals along with other clock sources go to the periphery distributed clock
multiplexer (DCM). In the periphery DCM, the clock signal can either pass straight through, be
gated by the root clock gate, or be divided by the clock divider.
In complex FPGA design development, design practices, coding styles, and IP
cores use have an enormous impact on your device’s timing performance, logic utilization,
compilation time, and system reliability. In addition, while planning and creating the design,
plan for a hierarchical or team-based design to improve design productivity.
Table 59. Design Recommendations Checklist
Use synchronous design practices. Pay attention to clock
In a synchronous design, a clock signal triggers all events. When all of the registers’
timing requirements are met, a synchronous design behaves in a predictable and reliable manner
for all process, voltage, and temperature (PVT) conditions. You can easily target synchronous
designs to different device families or speed grades.
Problems with asynchronous design techniques include reliance on propagation delays in a
device, incomplete timing analysis, and possible glitches. Pay particular attention to your
clock signals, because they have a large effect on your design’s timing accuracy, performance,
and reliability. Problems with clock signals can cause functional and timing problems in your
design. Use dedicated clock pins and clock routing for best results. For clock inversion,
multiplication, and division, use the device PLLs. For clock multiplexing and gating, use the
dedicated clock control block or PLL clock switchover feature instead of combinational logic.
If you must use internally generated clock signals, register the output of any combinational
logic used as a clock signal to reduce glitches. For example, if you divide a clock using
combinational logic, clock the final stage with the clock signal that was used to clock the
Intel provides parameterizable IP cores that are
optimized for Intel device architectures. You can
save design time by using IP cores instead of coding your own logic. Additionally, the
Intel-provided IP cores can offer more efficient
logic synthesis and device implementation. You can scale the IP core’s size and set various
options with parameters. IP cores include the library of parameterized modules (LPM) and
Intel device-specific IP cores. You can also take
advantage of Intel and third-party IP cores and
reference designs to save design time. The
Quartus® Prime IP
catalog provides a user interface to customize IP cores. You should build or change IP core
parameters using the parameter editor to ensure you set all ports and parameters
Consider the reconfiguration feature for your board
Stratix® 10 devices allow you to easily modify your
transceivers and FPGA-core while other portions of your design are still running by using
dynamic reconfiguration and partial reconfiguration, respectively.
Stratix® 10 devices allow you to
dynamically reconfigure different portions of the transceivers for different protocols, data
rates, and PMA settings without powering down any part of the device or interrupting adjacent
transceiver channels. This feature will be available in a future release of the
Quartus® Prime software.
If you are interested in using partial reconfiguration, contact your local
Intel representatives for support.
Follow recommended coding styles, especially for inferring device
dedicated logic such as memory and DSP blocks.
HDL coding styles can have a significant effect on the quality of results for programmable
logic designs. Use Intel’s recommended coding styles
to achieve optimal synthesis results. When designing memory and digital system processing
(DSP) functions, understand the device architecture so you can take advantage of the dedicated
logic block sizes and configurations.
Design Implementation, Analysis, Optimization, and Verification
After you create your design source code and apply constraints including the
device selection and timing requirements, your synthesis tool processes the code and maps it
to elements of the device architecture. The
Quartus® Prime Fitter
then performs placement and routing to implement the design elements in specific device
resources. If required, you can use the
Quartus® Prime software
to optimize the design’s resource utilization and achieve timing closure, preserve the
performance of unchanged design blocks, and reduce compilation time for future iterations. You
can also verify the design functionality with simulation. This section provides guidelines for
these stages of the compilation flow.
Selecting a Synthesis Tool
Table 63. Selecting a Synthesis Tool Checklist
Specify your synthesis tool and use the correct supported
Quartus® Prime software includes advanced and easy-to-use
integrated synthesis that fully supports Verilog HDL and VHDL, as well as the Intel hardware description language (AHDL) and schematic
design entry. You can also use industry-leading third-party EDA synthesis tools to synthesize
your Verilog HDL or VHDL design, and then compile the resulting output netlist file in the
Quartus® Prime software. Specify a third-party synthesis tool
in the New Project Wizard or the EDA Tools Settings page of the
Settings dialog box to use the correct Library Mapping File
(.lmf) for your synthesis netlist.
Intel recommends using the most recent version of
third-party synthesis tools, because tool vendors are continuously adding new features, fixing
tool issues, and enhancing performance for Intel
Different synthesis tools can give different results. If you want to select the
best-performing tool for your application, you can experiment by synthesizing typical designs
for your application and coding style and comparing the results. Be sure to perform placement
and routing in the
Quartus® Prime software to get accurate timing
analysis and logic utilization results.
Your synthesis tool might offer the capability to create a
Quartus® Prime project and pass constraints such as the EDA tool setting, device
selection, and timing requirements that you specified in your synthesis project. You can use
this capability to save time when setting up your
project for placement and routing.
Review resource utilization reports after compilation.
After compilation in the
Quartus® Prime software, review the
device resource utilization information to determine whether the future addition of extra
logic or other design changes introduce fitting difficulties. If your compilation results in a
no-fit error, resource utilization information is important so you can analyze the fitting
problems in your design.
To determine resource usage, refer to the Flow Summary section of the
Compilation Report for a percentage representing the total logic utilization, which includes
an estimation of resources that cannot be used due to existing connections or logic use.
Stratix® 10 devices, low logic utilization does not
have the lowest ALM utilization possible. In addition, a design that is reported as close to
100% full might still have space for extra logic. The Fitter uses ALUTs in different ALMs,
even when the logic can be placed within one ALM, so that it can achieve the best timing and
routability results. Logic might be spread throughout the device when achieving these results.
As the device fills up, the Fitter automatically searches for logic that can be placed
together in one ALM.
More detailed resource information is available by viewing the reports under
Fitter > Place section of the Compilation Report. The Fitter Resource Usage Summary report breaks down the logic utilization information and
indicates the number of fully and partially used ALMs, and provides other resource information
including the number of bits in each type of memory block. There are also reports that
describe some of the optimizations that occurred during compilation. For example, if you use
Quartus® Prime integrated synthesis, the reports under
Analysis & Synthesis > Partition <partition_name> > Optimization Results provide information, including registers that were removed during synthesis.
Use this report to estimate device resource utilization for a partial design to ensure that
registers were not removed due to missing connections with other parts of the design.
Intel Quartus Prime Messages
Quartus® Prime Messages Checklist
Quartus® Prime messages,
especially warning or error messages.
Each stage of the compilation flow generates messages, including informational notes,
warnings, and critical warnings. Review these messages to check for any design problems.
Ensure that you understand the significance of any warning messages, and make changes to the
design or settings if required. In the
Quartus® Prime user
interface, you can use the Message window tabs to look at only certain
types of messages, and you can suppress messages if you have determined that they do not
require any action from you.
Ensure timing constraints are complete and accurate, including
all clock signals and I/O delays.
Review the Timing Analyzer reports after
compilation to ensure there are no timing violations.
Ensure that the input I/O times are not violated when data is
provided to the
Stratix® 10 device.
In an FPGA design flow, accurate timing constraints allow timing-driven synthesis software
and place-and-route software to obtain optimal results. Timing constraints are critical to
ensure designs meet their timing requirements, which represent actual design requirements that
must be met for the device to operate correctly. The
Quartus® Prime software optimizes and analyzes your design using different timing models for each device
speed grade, so you must perform timing analysis for the correct speed grade. The final
programmed device might not operate as expected if the timing paths are not fully constrained,
analyzed, and verified to meet requirements.
Quartus® Prime software includes the
Quartus® PrimeTiming Analyzer, a powerful ASIC-style timing analysis tool that validates
the timing performance of all logic in your design. It supports the industry standard
Design Constraints (SDC) format timing constraints, and has an
easy-to-use GUI with interactive timing reports. It is ideal for constraining high-speed
source-synchronous interfaces and clock multiplexing design structures.
A comprehensive static timing analysis includes analysis of register to register, I/O, and
asynchronous reset paths. It is important to specify the frequencies and relationships for all
clocks in your design. Use input and output delay constraints to specify external device or
board timing parameters. Specify accurate timing requirements for external interfacing
components to reflect the exact system intent.
The Timing Analyzer performs static timing analysis on
the entire system, using data required times, data arrival times, and clock arrival times to
verify circuit performance and detect possible timing violations. It determines the timing
relationships that must be met for the design to correctly function.
You can use the report_datasheet command to generate a datasheet report that
summarizes the I/O timing characteristics of the entire design.
Recommended Timing Optimization and Analysis Assignments
Table 67. Recommended Timing Optimization and Analysis Assignments
Turn on Optimize multi-corner timing on
the Fitter Settings page in the Settings
Use create_clock and
create_generated_clock to specify the frequencies and relationships
for all clocks in your design.
Use set_input_delay and
set_output_delay to specify the external device or board timing
Use derive_clock_uncertainty to automatically
apply inter-clock, intra-clock, and I/O interface uncertainties.
Use check_timing to generate a report on any
problem with the design or applied constraints, including missing constraints.
Use set_false_path or set_clock_groups for
These assignments and settings are important for large designs such as those
Stratix® 10 devices.
When you turn on the Optimize multi-corner
timing option, the design is optimized to meet its timing requirements at all
timing process corners and operating conditions. Therefore, turning on this option helps
create a design implementation that is more robust across PVT variations.
In your Timing Analyzer.sdc constraints file, apply the recommended constraints
to your design.
Run Fitter (Plan) if you want timing estimates before running a
Quartus® Prime optimization
features to achieve timing closure or improve the resource utilization.
Use the Timing Optimization Advisors to suggest optimization
This section highlights some of the features offered in the
Quartus® Prime software to help optimize area (or resource utilization) and timing
performance. If the timing analysis reports that your design requirements were not met, you
must make changes to your design or settings and recompile the design to achieve timing
closure. If your compilation results in no-fit messages, you must make changes to get
successful placement and routing.
You can run Fitter (Plan) to estimate your design’s timing results before the
software performs full placement and routing. Click Processing > Start > Start Fitter (Plan) to generate initial compilation results after you have run analysis and
Physical synthesis optimizations make placement-specific changes to the netlist that improve
results for a specific Intel device. You can optimize
for performance by selecting High Performance Effort or
Superior Performance Optimization Mode in the Compiler
Settings. These optimization modes turn on the Advanced Physical
Synthesis option under the Advanced Fitter Settings. If you
turn on these options, ensure that they do improve the results for your design. If you do not
require these options to meet your design timing requirements, turn off the options to reduce
the compilation time.
The Design Space Explorer II (DSE II) is a utility that automates the process to find optimal
project settings for resource, performance, or power optimization goals. DSE II attempts
multiple seeds to identify one that meets your requirements. The Exploration Panel > Exploration mode allows you a predefine exploration space to target design performance, area of
improvements, or power reduction with multiple compilations.
The Optimization Advisors provide guidance in making settings that optimize your design. On
the Tools menu, click Advisor > Timing Optimization Advisor. Evaluate the options and choose settings that suit your requirements.
Preserving Performance and Reducing Compilation Time
Table 69. Preserving Performance and Reducing Compilation Time Checklist
Use incremental compilation to preserve performance for unchanged
blocks in your design and to reduce compilation times.
Ensure parallel compilation is enabled if you have multiple
processors available for compilation.
Use the Compilation Time Advisor to suggest settings that reduce
Use the incremental compilation feature to preserve logic in unchanged parts of your design,
preserve timing performance, and reach timing closure more efficiently. You can speed up
design iteration time by an average of 60% when making changes to the design with the
incremental compilation feature.
Quartus® Prime software can run some algorithms in parallel
to take advantage of multiple processors and reduce compilation time when more than one
processor is available to compile the design. Set the Parallel
compilation option on the Compilation Process Settings
page of the Settings dialog box, or change the default setting in the
Options dialog box in the Processing page from
the Tools menu.
The Compilation Time Advisor provides guidance in making settings that reduce your design
compilation time. On the Tools menu, point to Advisors and click
Compilation Time Advisor. Using some of these techniques to reduce
compilation time can reduce the overall quality of results.
Designing with Intel Hyperflex
Table 70. Designing with
optimize your design and achieve enhanced performance.
core architecture adds registers
to both the interconnect routing and the inputs of all major functional blocks in the FPGA.
These added registers, called Hyper-Registers, are different from conventional registers.
Conventional registers are present only in the adaptive logic modules (ALMs). Hyper-Registers
can help to achieve significant core performance improvement.
To achieve this enhanced performance, you must optimize your designs using the following
Specify your simulation tool, and use the correct supported
version and simulation models.
Quartus® Prime software supports both RTL
and gate level functional simulations. Perform functional simulation at the beginning of your
design flow to check the design functionality or logical behavior of each design block. You do
not have to fully compile your design; you can generate a functional simulation netlist that
does not contain timing information.
Intel provides the
ModelSim* - Intel® FPGA Starter Edition and offers the higher performance
ModelSim* - Intel® FPGA Edition, which enable you to take advantage of
advanced testbench capabilities and other features. In addition, the
Quartus® Prime EDA Netlist Writer can generate timing netlist files to support other
third-party simulation tools such as
NC-Sim, and Aldec Active-HDL. Specify your simulation tool in the EDA Tools Settings page of the Settings
dialog box to generate the appropriate output simulation netlist.
If you use a third-party simulation tool, use the software version that is
supported with your
Quartus® Prime software version. The
Quartus® Prime Software Release Notes list the version of each
simulation tool that is officially supported with that particular version of the
Quartus® Prime software. Use the model libraries provided with your
Quartus® Prime software version, because libraries can change
between versions, which might cause a mismatch with your simulation netlist. To create a
testbench, on the Processing menu, point to Start and
click Start Test Bench Template Writer.
After compilation, analyze power consumption and heat dissipation
in the Power Analyzer.
Provide accurate signal activities, preferably with a gate-level
simulation .vcd, to get accurate power analysis
Specify the correct operating conditions for power
Before design completion, estimate power consumption using the EPE
spreadsheet. After compiling your design, analyze the power consumption and heat dissipation
Quartus® Prime Power Analyzer to ensure the design has
not violated power supply and thermal budgets.
You must compile a design (to provide information about design resources,
placement and routing, and I/O standards) and provide signal activity data (toggle rates and
static probabilities) to use the Power Analyzer. You can derive signal activity data from
simulation results or a user-defined default toggle rate and vectorless estimation. The signal
activities used for analysis must be representative of the actual operating behavior. For the
most accurate power estimation, use gate-level simulation results with a .vcd output file from a third-party simulation tool. The
simulation activity should include typical input vectors over a realistic time period and not
the corner cases often used during functional verification. Use the recommended simulator
settings (such as glitch filtering) to ensure good results.
You must also specify operating conditions, including the core voltage, device power
characteristics, ambient and junction temperature, cooling solution, and the board thermal
model. Select the appropriate settings on the Operating Settings and
Conditions page in the Settings dialog box.
To calculate the dynamic, static, and I/O thermal power consumption, on the
Processing menu, click Power Analyzer Tool. The tool
also provides a summary of the signal activities used for analysis and a confidence metric
that reflects the overall quality of the data sources for signal activities.
The report is a power estimate based on the data provided, and is not a power specification.
Always refer to the datasheet for the power specification of your device.
Stratix® 10 devices utilize advanced
process and circuit techniques, along with major circuit and architecture innovations, to
minimize power and deliver high performance.
To reduce dynamic power consumption in
devices, you can use various design and software techniques to optimize your design.
Power optimization in the
Quartus® Prime software depends on
accurate power analysis results. Use the guidelines in the previous section to ensure the
software optimizes the power utilization correctly for the design’s operating behavior and
Device and Design Power Optimization Techniques
Table 73. Device and Design Power Optimization Techniques Checklist
Use recommended design techniques and
Quartus® Prime options to optimize your design for power consumption, if
Use the Power Optimization Advisor to suggest optimization
If your design includes many critical timing paths that require the
high-performance mode, you might be able to reduce power consumption by using a faster speed
grade device if available.
Clock Power Management
Table 75. Clock Power Management Checklist
Optimize the clock power management.
Clocks represent a significant portion of dynamic power consumption, because
of their high switching activity and long paths. The
Quartus® Prime software automatically optimizes clock routing power by enabling only the portions of a
clock network that are required to feed downstream registers. You can also use clock control
features to dynamically enable or disable the clock network. When a clock network is powered
down, all the logic fed by that clock network does not toggle, thereby reducing the overall
power consumption of the device.
To reduce LAB-wide clock power consumption without disabling the entire clock tree, use the
LAB-wide clock enable signal to gate the LAB-wide clock. The
Quartus® Prime software automatically promotes register-level clock enable signals to
the LAB level.
The dynamic power consumed in the I/O buffer is proportional to the total load capacitance;
therefore, lower capacitance reduces power consumption.
Non-terminated I/O standards such as LVTTL and LVCMOS have a rail to-rail output swing equal
to the VCCIO supply voltage. Because dynamic power is proportional to the square of
the voltage, use lower voltage I/O standards to reduce dynamic power. These I/O standards
consume little static power.
Because dynamic power is also proportional to the output transition frequency, use
resistively-terminated I/O standards such as SSTL for high-frequency applications. The output
load voltage swings by an amount smaller than the VCCIO around a bias point;
therefore, dynamic power is lower than for non-terminated I/O under similar conditions.
Resistively-terminated I/O standards dissipate significant static power because current is
constantly driven into the termination network. Use the lowest drive strength that meets your
speed and waveform requirements to minimize static power when using resistively terminated I/O
The power used by external devices is not included in the EPE calculations,
so be sure to include it separately in your system power calculations.
Intel Quartus Prime Power Optimization Techniques
Quartus® Prime Power Optimization
Review recommended design techniques and
Quartus® Prime options to optimize power consumption.
Quartus® Prime software offers
power-optimized synthesis and fitting to reduce core dynamic power.
Optimizing your design for area also saves power because fewer logic blocks
are used; therefore, there is typically less switching activity. Improving your design source
code to optimize for performance can also reduce power usage. You can use the DSE and Power
Optimization Advisor to provide additional suggestions to reduce power.
Use the Power Optimization Advisor to suggest optimization
Quartus® Prime software includes the Power
Optimization Advisor, which provides specific power optimization advice and recommendations
based on the current design project settings and assignments. On the Tools menu, point to
Advisors and click Power
Optimization Advisor. After making any of the recommended changes, recompile
your design and run the Power Analyzer to check the change in your power results.
Document Revision History for Intel Stratix 10 Device Design Guidelines
Added a checklist item on
Reset Release IP in the Planning for Device Configuration
Updated the guidelines on physical synthesis optimizations in the Area and
Timing Optimization section.
Added a checklist item on configuration guidelines and additional clock
requirements for designs using PCIe, transceiver channels, HPS, High Bandwidth
Memory (HBM2) IP core, or SmartVID in the Planning for
Device Configuration Checklist table.
Added a checklist item on SmartVID connection and the VCC
voltage regulator in the Other Configuration Pins
Updated checklist item in the Device
Variant Checklist table.
Added links to transceiver documents in the following
Vertical Device Migration
Transceiver Board Design Guidelines
Removed NAND configuration scheme.
Renamed the following IP cores as per Intel rebranding:
Renamed Intel FPGA S10 Temperature Sensor IP core to Temperature Sensor
Intel Stratix 10 FPGA IP core.
Renamed Virtual JTAG IP core to Virtual JTAG Intel FPGA IP core.
Renamed SLD_VIRTUAL_JTAG IP core to SLD_VIRTUAL_JTAG Intel FPGA IP
Renamed Stratix 10 External Memory Interfaces IP core to External Memory
Interfaces Intel Stratix 10 FPGA IP core.
Renamed Stratix 10 Intel FPGA PHYLite for Parallel Interfaces IP core to
PHYLite for Parallel Interfaces Intel Stratix 10 FPGA IP core.
Renamed Intel FPGA IOPLL IP core to IOPLL Intel FPGA IP core.
Renamed Stratix 10 Clock Control IP core to Clock Control Intel Stratix 10
FPGA IP core.
Removed the LPM_CONSTANT IP core. Not supported in the
Stratix® 10 devices.
Updated checklist item in the Design
Specifications Checklist table.
Updated checklist item in the IP
Selection Checklist table.
Updated checklist item in the PLLs and
Clock Routing Checklist table.
Updated the Logic, Memory, and
Multiplier Density section.
Added checklist item in the Vertical Device Migration Checklist
Added external TSD information in the Temperature Sensing
for Thermal Management section.
Added thermal information in the following sections:
Early Power Estimation
Thermal Management and Design
Temperature Sensing for Thermal
Changed the section title from Data Compression to
Configuration Bitstream Compression.
Updated the Optional Configuration
Added description for the Signal Tap Embedded
Logic Analyzer in the On-Chip Debugging Tools section.
Added checklist item to the Power Pin
Connections and Power Supplies Checklist table.
Updated checklist item in the Board-Related
Quartus® Prime Settings
Updated the links in the Memory Interfaces
Updated the Dual-Purpose and Special Pin
Updated the Design Entry section.
Removed information on Design Assistant in the Design Recommendations section.
Updated the Reconfiguration
Removed information on formal verification in the Design Implementation,
Analysis, Optimization, and Verification section.
Updated report locations in the Device Resource Utilization Reports
Updated the Timing Constraints and
Updated the Recommended Timing
Optimization and Analysis Assignments Checklist table.
Removed checklist item on derive_pll_clocks.
Added checklist item on set_false_path and set_clock_groups.
Updated the Area and Timing
Updated description on Hyper-Registers in the Designing with
Removed information on NativeLink in the Simulation section.
Removed information on programmable power tiles in the following section:
Device Speed Grade
Quartus® Prime Power Optimization
Removed the following sections:
Device-Wide Output Enable Pin
Register Power-Up Levels and Control Signals
Updated the following terms:
Changed Qsys to Platform Designer
Changed OpenCore Plus to
Intel® FPGA IP Evaluation Mode
Changed TimeQuest Timing Analyzer to Timing Analyzer
Changed BluePrint Platform Designer to Interface Planner
Updated IP name from Altera PHYLite for Parallel Interfaces to
PHY Lite for Parallel Interfaces.
Removed Start I/O Assignment Analysis command in Early Pin Planning and I/O
Assignment Analysis section.
Removed incremental compilation feature. Removed the following topics: