Intel^® Stratix^® 10 devices contain dedicated resources for distributing signals throughout the fabric with balanced delay. These resources are typically used for clock signals and other signals with low-skew requirements. In Intel^® Stratix^® 10 devices, these resources are implemented as a programmable clock routing network, which allows for the implementation of low-skew clock trees of various size.

Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Intel^® Stratix^® 10 device family contains the following PLLs for core applications:

• fPLLs—can function as fractional PLLs or integer PLLs
• I/O PLLs—can only function as integer PLLs

The fPLLs are located adjacent to the transceiver blocks in the transceiver banks. Each transceiver bank contains two fPLLs. You can configure each fPLL independently in either conventional integer mode, or fractional mode. In fractional mode, the fPLL can operate with third-order delta-sigma modulation. You can configure each fPLL to generate either a transmitter (TX) clock for a transceiver or to provide a single clock to the core.

The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains one I/O PLL. The I/O PLLs can operate in conventional integer mode. Each I/O PLL has nine C counter outputs.

Intel^® Stratix^® 10 devices have up to 48 fPLLs and 42 I/O PLLs in the largest densities devices.

This section describes the sources that can drive the programmable clock routing.

The sources of dedicated clock input pins are as follows:

• fPLL—REFCLK_GXB[L,R][1,4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T][p,n] from transceiver column
• I/O PLL—CLK_[2,3][A..N]_[0,1][p,n] from I/O column

You can use the dedicated clock input pins for high fan-out control signals, such as asynchronous clears, presets, and clock enables, for protocol signals through the programmable clock routing.

The dedicated clock input pins for an I/O PLL can be either differential clocks or single-ended clocks. The dedicated clock input pins for fPLL only support differential clocks and do not support single-ended clocks.

Driving a PLL over programmable clock routing can cause higher jitter at the PLL input, and the PLL is not able to fully compensate for the programmable clock routing. Intel recommends using the dedicated clock input pins for optimal performance to drive the PLLs.

You can route up to eight core signals to each clock switch multiplexer, except the clock switch multiplexers at the right and left edge of the device, and the clock switch multiplexers next to the I/O banks.

Each DPA clock output can drive the programmable clock routing.

PMA and PCS TX and RX clock outputs can drive the programmable clock routing.

The fPLL and I/O PLL clock outputs can drive the programmable clock routing.

The following figure shows the high level description of the Intel^® Stratix^® 10 clock control features—clock gating and clock divider. The clock from the I/O PLL output can be gated dynamically. These clock signals along with other clock sources go to the periphery distributed clock multiplexer (DCM). In the periphery DCM, the clock signal can either pass straight through, be gated by the root clock gate, or be divided by the clock divider.

The Intel^® Quartus^® Prime software routes the clock signal on the programmable clock routing to reach each clock sector. The clock signal can be gated in each sector by the SCLK gates. The clock enters the SCLK network followed by the row clock network, and eventually reaches the registers in the core. The LAB registers have a built-in functional clock enable feature, as shown in the following figure.

There is one root clock gate per I/O bank and transceiver bank. This gate is a part of the periphery DCM and is located close to the clock buffer.

The Intel^® Stratix^® 10 root clock gate is intended for limited clock gating scenarios where high insertion delay can be tolerated. When you use a root clock gate, set multicycle of several clock cycles between the generation of the clock gating signal in the core and the gated clock in the periphery to meet the timing requirement. For high frequency clocks that require single-cycle gating, use sector clock gates.

There are 32 SCLKs in every sector of the device. Each SCLK has a clock gate and bypassable clock gate path. The SCLK gates are controlled by clock enable inputs from the core logic. The Intel^® Quartus^® Prime software can route up to eight unique clock enable signals to the 32 SCLKs in a sector.

Intel recommends using the clock gate with a negative latch to provide glitch free gating on the output clock signal (outclk). The clock gate captures the enable signal (clkena) on the next rising edge of the input clock signal (inclk). The following timing diagram shows the relationship of the outclk with respect to inclk and clkena.

The clock signal going into the SCLK network in a sector can only reach the core logic in that sector. When you instantiate a SCLK gate in your design, the Intel^® Quartus^® Prime software automatically duplicates the SCLK gate to create a clock gate in every sector to which the clock signal is routed.

The SCLK gate is suitable for cycle-specific clock gating for high-frequency clocks. The timing of the enable path to the SCLK gate is analyzed by the Intel^® Quartus^® Prime software.

You can dynamically gate each output counter of the Intel^® Stratix^® 10 I/O PLL. This provides a useful alternative to the root clock gate because the root clock gate can gate only 1 of the 9 output counters.

However, the I/O PLL clock gate is not cycle-specific. When you use the I/O PLL clock gate, expect a delay of several clock cycles between the assertion or deassertion of the clock gate and the corresponding change to the clock signal. The number of delay cycles is non-deterministic because the enable signal must be synchronized into the clock domain of the output clock, ensuring a glitch-free gate.

The Intel^® Stratix^® 10 LAB register has built-in clock gating functionality. The register clock enable mechanism is a hardened data feedback, as shown in the Clock Gating and Clock Divider in Intel^® Stratix^® 10 Clock Network diagram. The LAB clock gate offers no associated power savings because this is a purely functional clock enable.

The analysis and synthesis phases of the Intel^® Quartus^® Prime software infer a LAB clock gate from a behavioral description of clock gating in the register transfer level (RTL). If a physical clock gate is desired, you must instantiate it explicitly.

There is one clock divider per I/O bank and transceiver bank. The clock divider is a part of the periphery DCM block and is located close to the root clock gate. The outputs of the clock divider cannot be gated by the root clock gate in the same periphery DCM block. However, this limitation does not apply to the SCLK gate. The clock divider output in the periphery DCM block can drive a SCLK gate after going through the programmable clock routing.

The clock divider has three outputs as follows:

• First output—Passes through the input clock.
• Second output—Divides the input clock by two.
• Third output—Divides the input clock by four.

These three clock outputs are edge-aligned at the output of the clock divider.

Intel^® Stratix^® 10 devices do not have hard clock multiplexer blocks for dynamic clock switchover. Thus, the dynamic clock switchover logic is implemented using the soft logic in the core. Optionally, you can make the dynamic clock switchover glitch free using additional external soft logic.

fPLLs are optimized for use as transceiver transmit PLLs and for synthesizing reference clock frequencies. You can use the fPLLs to:

• Transmit clocking for transceivers
• Reduce the number of required oscillators on the board

I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use the I/O PLLs to:

• Reduce the number of required oscillators on the board
• Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
• Simplify the design of external memory interfaces and high-speed LVDS interfaces
• Ease timing closure because the I/O PLLs are tightly coupled with the I/Os
• Compensate for clock network delay
• Zero delay buffering

You can use the reset signal to control PLL operation and resynchronization, and use the locked signal to observe the status of the PLL.

The reset signal port of the IP core for I/O PLL is reset.

The reset signal is the reset or resynchronization input for each I/O PLL. The device input pins or internal logic can drive these input signals.

When the reset signal is driven high, the I/O PLL counters reset, clearing the I/O PLL output and placing the I/O PLL out-of-lock. The VCO is then set back to its nominal setting. When the reset signal is driven low again, the I/O PLL resynchronizes to its input clock source as it re-locks.

You must assert the reset signal every time the I/O PLL loses lock to guarantee the correct phase relationship between the I/O PLL input and output clocks. You can set up the I/O PLL to automatically reset (self-reset) after a loss-of-lock condition using the Intel^® Quartus^® Prime parameter editor.

You must include the reset signal if either of the following conditions is true:

• I/O PLL reconfiguration or clock switchover is enabled in the design.
• Phase relationships between the I/O PLL input and output clocks must be maintained after a loss-of-lock condition.

The locked signal port of the IP core for each PLL is as follows:

• fPLL—pll_locked
• I/O PLL—locked

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.

When PLL loses lock, the output of the PLL starts drifting out of the desired frequency. The downstream logic must be held inactive once PLL has lost lock.

Clock feedback modes compensate for clock network delays to align the rising edge of the output clock with the rising edge of the PLL's reference clock. Select the appropriate type of compensation for the timing critical clock path in your design.

PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.

The default clock feedback mode is direct compensation mode.

fPLLs support only the direct compensation mode.

I/O PLLs support the following clock feedback modes:

• Direct compensation
• LVDS compensation
• Source synchronous compensation
• Normal compensation
• Zero delay buffer (ZDB) compensation
• External feedback (EFB) compensation

Normal and source synchronous compensation modes compensate for the insertion delay of a routed core clock. For Intel^® Stratix^® 10 devices, you can achieve core clock compensation by the following methods:

• You can route a dedicated feedback clock from the M counter in the I/O PLL to emulate the insertion delay of the compensated C counter output clock network.
• You can select Use Nondedicated Feedback Path from the IOPLL Intel^® FPGA IP core which routes the compensated C counter output clock back to the I/O PLL.

Intel recommends the non-dedicated feedback mechanism because it utilizes the clock resources most efficiently. The default is dedicated feedback when you choose normal or source synchronous compensation mode in the IOPLL IP core.

In direct mode, the PLL does not compensate for any clock network delays. This mode provides better jitter performance compared to other compensation modes because the clock feedback into the phase frequency detector (PFD) passes through less circuitry. Both the PLL internal- and external-clock outputs are phase-shifted with respect to the PLL clock input.

The purpose of LVDS compensation mode is to maintain the same data and clock timing relationship seen at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock network, including the difference in delay between the following two paths:

• Data pin-to-SERDES capture register
• Clock input pin-to-SERDES capture register

The output counter must provide the 180° phase shift.

If the data and clock signals arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Only one output clock can be compensated in source synchronous compensation mode.

Intel recommends source synchronous mode for source synchronous data transfers.

The source synchronous mode compensates for the delay of the clock network used and any difference in the delay between the following two paths:

• Data pin to the IOE register input
• Clock input pin to the PLL PFD input

The Intel^® Stratix^® 10 PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode.

An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. The Intel^® Quartus^® Prime Timing Analyzer reports any phase difference between the two. In normal compensation mode, the delay introduced by the clock network is fully compensated. Only one output clock can be compensated in normal compensation mode.

In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device.

In this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock input or output pins.

To ensure phase alignment between the clk pin and the external clock output (CLKOUT) pin in ZDB mode, instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path connecting the fbout and fbin ports of the PLL. The bidirectional I/O pin must always be assigned a single-ended I/O standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the output delay from the clock output port of the PLL to the external clock output pin.

In external feedback (EFB) mode, the output of the M counter (fbout) feeds back to the PLL fbin input (using a trace on the board) and becomes part of the feedback loop.

One of the dual-purpose external clock outputs becomes the fbin input pin in this mode. The external feedback input pin, fbin is phase-aligned with the clock input pin. Aligning these clocks allows you to remove clock delay and skew between devices.

In EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock outputs.

An Intel^® Stratix^® 10 PLL output frequency is related to its input reference clock source by the following scale factors:

• M/(N × C) for I/O PLL
• M/(N × C × 2) for fPLL core applications

The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match f_in × (M/N). When using non-dedicated feedback path in normal or source synchronous compensation mode, the control loop drives the VCO to match f_in × ((M × C_i )/N), where C_i is the compensated outclk C counter value. The Intel^® Quartus^® Prime software automatically chooses the appropriate scale factors according to the input frequency, multiplication, and division values entered into the Intel^® FPGA IP cores for I/O PLL and fPLL.

The programmable phase shift feature allows only the I/O PLLs to generate output clocks with a fixed phase offset.

The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift increment is 1/8 of the VCO period. For example, if an I/O PLL operates with a VCO frequency of 1000 MHz, phase shift steps of 125 ps are possible.

The Intel^® Quartus^® Prime software automatically adjusts the VCO frequency according to the user-specified phase shift values entered into the IOPLL IP core parameter editor.

The programmable duty cycle feature allows I/O PLLs to generate clock outputs with a variable duty cycle. This feature is only supported by the I/O PLL post-scale counters, C. fPLLs do not support the programmable duty cycle feature and only have fixed 50% duty cycle.

The I/O PLL C counter value determines the precision of the duty cycle. The precision is 50% divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty-cycle options from 5% to 90%. If the I/O PLL is in external feedback mode, set the duty cycle for the counter driving the fbin pin to 50%.

The Intel^® Quartus^® Prime software automatically adjusts the VCO frequency according to the required duty cycle that you enter in the IOPLL IP core parameter editor.

Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks.

Intel^® Stratix^® 10 devices support PLL-to-PLL cascading. You can cascade a maximum of two PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL.

If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting, and the destination (downstream) PLL must have a high-bandwidth setting for I/O PLL and medium-bandwidth setting for fPLL. During cascading, the output of the source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the cascaded PLLs may amplify phase noise at certain frequencies.

Intel^® Stratix^® 10 devices support the following PLL-to-PLL cascading modes:

• I/O-PLL-to-I/O-PLL cascading via dedicated cascade path—Upstream I/O PLL and downstream I/O PLL must be in the same I/O column.
• I/O-PLL-to-I/O-PLL cascading via core clock fabric—No restriction on locations of upstream and downstream I/O PLL.

The permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes.

The following figures show the connectivity required between the upstream and downstream I/O PLL for both the PLL cascading modes.

The clock switchover feature allows the I/O PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application where a system turns to the redundant clock if the previous clock stops running. The design can perform clock switchover automatically when the clock is no longer toggling or based on a user control signal, extswitch.

Intel^® Stratix^® 10 I/O PLLs support the following clock switchover modes:

• Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.
• Manual clock switchover—Clock switchover is controlled using the extswitch signal. When the extswitch signal goes from logic high to logic low, and stays low for at least three clock cycles for the inclk being switched to, the reference clock to the I/O PLL is switched from inclk0 to inclk1, or vice-versa.
• Automatic switchover with manual override—This mode combines automatic switchover and manual clock switchover. When the extswitch signal goes low, it overrides the automatic clock switchover function. As long as the extswitch signal is low, further switchover action is blocked.

Intel^® Stratix^® 10 I/O PLLs support a fully configurable clock switchover capability.

When the current reference clock is not present, the clock sense block automatically switches to the backup clock for I/O PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1 port of the I/O PLL in your design.

The clock switchover circuit sends out three status signals—clkbad0, clkbad1, and activeclock—from the I/O PLL to implement a custom switchover circuit in the logic array.

In automatic switchover mode, the clkbad0 and clkbad1 signals indicate the status of the two clock inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%.

The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selected as the reference clock to the I/O PLL. When the frequency difference between the two clock inputs is more than 20%, the activeclock signal is the only valid status signal.

Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the I/O PLL stops toggling. You can switch back and forth between inclk0 and inclk1 any number of times when one of the two clocks fails and the other clock is available.

For example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal (clksw) that controls the multiplexer select input. In this case, inclk1 becomes the reference clock for the I/O PLL.

When using automatic clock switchover mode, the following requirements must be satisfied:

• Both clock inputs must be running when the FPGA is configured.
• The period of the two clock inputs can differ by no more than 20%.
• The input clocks must meet the input jitter specifications and I/O standard specifications.

Glitches in the input clock may be seen as a greater than 20% difference in frequency between the input clocks.

If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated and the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but their period difference is within 20%, the clock sense block detects when a clock stops toggling. However, the I/O PLL may lose lock after the switchover is completed and needs time to relock.

In automatic switchover with manual override mode, you can use the extswitch signal for user- or system-controlled switch conditions. You can use this mode for same-frequency switchover, or to switch between inputs of different frequencies.

For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using the extswitch signal. The automatic clock-sense circuitry cannot monitor clock input (inclk0 and inclk1) frequencies with a frequency difference of more than 100% (2×).

This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between the frequencies of operation.

You must choose the backup clock frequency and set the M, N, C, L, and K counters so that the VCO operates within the recommended operating frequency range. The Intel^® Quartus^® Prime software notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement.

In automatic override with manual switchover mode, the activeclock signal inverts after the extswitch signal transitions from logic high to logic low. Since both clocks are still functional during the manual switch, neither clkbad signal goes high. Because the switchover circuit is negative-edge sensitive, the rising edge of the extswitch signal does not cause the circuit to switch back from inclk1 to inclk0. When the extswitch signal goes low again, the process repeats.

The extswitch signal and automatic switch work only if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available.

In manual clock switchover mode, the extswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the I/O PLL. By default, inclk0 is selected.

A clock switchover event is initiated when the extswitch signal transitions from logic high to logic low, and is held low for at least three inclk cycles for the inclk clock being switched to.

You must bring the extswitch signal back high again to perform another switchover event. If you do not require another switchover event, you can leave the extswitch signal in a logic low state after the initial switch.

If inclk0 and inclk1 are different frequencies and are always running, the extswitch signal minimum low time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.

You can delay the clock switchover action by specifying the switchover delay in the Intel^® FPGA IP cores for the I/O PLL. When you specify the switchover delay, the extswitch signal must be held low for at least three inclk cycles for the inclk being switched to plus the number of the delay cycles that has been specified to initiate a clock switchover.

Intel^® Stratix^® 10 devices support PLL reconfiguration and dynamic phase shift with the following features:

• PLL reconfiguration—I/O PLL and fPLL are able to reconfigure the M, N, and C counters. Only the fPLL supports reconfiguration of the fractional settings.
• Dynamic phase shift—Only the I/O PLL can perform positive or negative phase shift. Able to shift multiple phase steps each time, where one phase step is equal to 1/8 of the VCO period.

I/O PLLs include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. Intel^® Stratix^® 10 uses the I/O manager to perform calibration routines.

There are two main types of calibration.

• Power-up calibration—Initiates automatically at device power-up and runs during device configuration.
• User calibration—If you perform dynamic reconfiguration or change the reference clock frequency of the I/O PLL, you must perform user recalibration. You must enable the required calibration sequence.

To successfully complete the calibration process, OSC_CLK_1 clocks and all reference clocks driving the I/O PLLs must be stable and free running at the start of FPGA configuration. If clock switchover is enabled, both reference clocks must be present for calibration. During user mode, when the I/O PLL does not detect a reference clock during configuration, calibration attempts continue periodically. After calibration has completed, the I/O PLL is locked automatically.

After device power-up, the I/O manager automatically initiates the calibration process. The process continues during device programming.

You must enable the permit_cal signal from the IOPLL IP core to delay the power-up calibration in I/O PLL if the reference clock is not stable before device configuration. Set permit_cal = 0 upon power up until the reference clock is stable and operating at the correct frequency. Then, set permit_cal = 1 to initiate the power-up calibration. You must ensure that the permit_cal signal remains high once asserted.

The I/O PLL must be recalibrated for any of the following conditions after device power up:

• Dynamic I/O PLL reconfiguration that changes the M or N counter settings is performed.
• Change of the reference clock frequency to the I/O PLL.

Recalibration is not necessary when using clock switchover to a secondary reference clock with a different frequency than the primary reference clock. The I/O PLL stores the calibration settings for both reference clocks after power-up calibration.

To perform the recalibration of the I/O PLL, you must enable the IOPLL Reconfig Intel^® FPGA IP core to enable the recalibration mode.

To implement the fPLL IP core, you must adhere to the following constraints:

• You must use create_clock constraints on fPLL reference clocks on the project's top-level SDC file.
• Any SDC design constraints referring to transceiver clocks must be listed after the transceiver Native PHY SDC file constraints.
• fPLL output clocks have no phase relationship to the reference clock when utilizing the fPLL output clocks for core usage. The fPLL output clocks of the clock divider are still in phase with each other, however.

To implement the IOPLL IP core, you must adhere to the following constraints:

• Any SDC design constraints referring to the I/O PLL clocks must be listed after the SDC constraints for the IOPLL IP core.

To reset the PLL, refer to the following guidelines:

• When changing the M counter, N counter, or loop filter settings, the I/O PLL may lose and regain lock. To maintain the appropriate phase relationship between the reference clock and output clocks, assert the areset signal to reset the I/O PLL after reconfiguration is complete. Intel recommends always resetting the I/O PLL after any reconfiguration operation to the M counter, N counter, or loop filter settings.
• When changing the C counter settings, you may lose the expected phase relationship between the C counters. Assert the areset signal after reconfiguration is complete to restore the expected phase relationship. Reset is not required if the phase relationships are not important to your application.
• Resetting the I/O PLL does not modify the counter or loop filter settings. However, resetting the I/O PLL undoes any dynamic phase shift operations that were performed. After the I/O PLL is reset, the phase shift on the C counters is restored to the originally programmed settings.

The I/O PLL configuration must obey the following constraints:

• The phase frequency detector (PFD) and VCO each have a legal frequency range of operation.
• The loop filter settings must be appropriate for the M counter value and user-selected bandwidth mode.

If any of these configuration constraints are violated, the I/O PLL may fail to lock or may exhibit poor jitter performance.

For timing closure, refer to the following guidelines:

• Reconfiguring a PLL's counter and loop filter settings changes both the output frequency and the clock uncertainty of that I/O PLL. Dynamic phase shift only affects the output clock phase.
• The Timing Analyzer in the Intel^® Quartus^® Prime software performs timing analysis for the initial PLL settings only. You must verify that your design closes timing after dynamic reconfiguration or dynamic phase shift.
• Intel recommends compiling the I/O PLL designs with each intended configuration setting to determine the variation in the clock with the I/O PLL settings.

To reconfigure the I/O PLL, refer to the following guidelines:

• If the reference clock frequency changes, you must recalibrate the I/O PLL using the IOPLL Intel^® FPGA IP core.
• The I/O PLL reconfiguration interface must have a free running mgmt_clk signal. The I/O PLL dynamic phase shift interface must have a free running scanclk signal. These interfaces eliminate the need to precisely control the start and stop of mgmt_clk and scanclk signals.
• The I/O PLL can be reconfigured with .mif streaming mode and advanced mode using the IOPLL Reconfig Intel^® FPGA IP core. Intel recommends using the .mif streaming mode.
• Use caution when reconfiguring an I/O PLL with a non-zero phase shift setting. Modifying the M counter or N counter settings does not change the relative phase shift (in percent), but alters the absolute phase shift (in picoseconds). Modifying the C counter settings does not change the absolute phase shift, but modifies the relative phase shift.

To achieve the Intel^® Stratix^® 10 I/O PLL clock output jitter performance as specified in the Intel^® Stratix^® 10 Device Datasheet, adhere to the maximum allowable number of unterminated simultaneously switching output (SSO) pins, such as LVTTL and LVCMOS, within the I/O bank (where the PLL output clock resides).

If you use more than the maximum allowable unterminated SSO pins, additional jitter beyond the PLL clock output jitter specification is induced to the PLL clock output.

When you use a combination of different current strength, calculate the maximum allowable number of SSO pins according to the strongest current strength used. The jitter increment value per SSO pin should then be calculated using the strongest current strength setting from the remaining SSO pins (after deducting the maximum allowable number of SSO pins from the total SSO pins). For example, if the design has 19 pins with current strength 16 mA, 5 pins with current strength 12 mA, and 2 pins with current strength 10 mA, the maximum allowable number of SSO pins for this design is 17, and the jitter increment per SSO pin is 8 ps/pin. Total additional jitter induced is equivalent to [(19 + 5 + 2) – 17] × 8 = 72 ps.

Both sector clock gate and root clock gate have similar skews. To achieve higher performance when transferring between gated and non-gated clocks and vice-versa, refer to the following guidelines:

• Minimize the size of clock region because smaller clock delays have lower skew.
• Ensure that both gated and non-gated clocks have similar sizes.
• Minimize logic on paths between gated and non-gated clocks to achieve better timing margin to compensate for the higher skews.

If you are looking for the fPLL IP core, refer to the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.

The Clock Control IP core provides clock control features such as enabling entry to the clock network, clock multiplexing, clock gating, and clock division for the Intel^® Stratix^® 10 devices.

The IOPLL IP core allows you to configure the settings of the Intel^® Stratix^® 10 I/O PLL.

The IOPLL IP core supports the following features:

• Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
• Generates up to nine clock output signals for the Intel^® Stratix^® 10 device.
• Switches between two reference input clocks.
• Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL cascading mode.
• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
• Supports PLL dynamic phase shift.

You can generate the .mif files in the IOPLL IP core parameter editor.

You can use the IOPLL IP core to perform phase shifting directly through the dynamic phase shift ports.

You must install the Intel^® Quartus^® Prime software version 17.1 or later. The software must be installed on a Windows* or Linux* computer that meets the Intel^® Quartus^® Prime software minimum requirements.

You can use Intel^® Stratix^® 10 devices to implement phase-locked loop (PLL) reconfiguration and dynamic phase shift for I/O PLLs.

The Intel^® Stratix^® 10 I/O PLL supports dynamic reconfiguration when the device is in user mode. With the dynamic reconfiguration feature, you can reconfigure the I/O PLL settings in real time. You can change the divide settings of the PLL counters and the PLL bandwidth settings (loop filter setting and charge pump setting) through an Avalon^® Memory-Mapped ( Avalon^® -MM) interface in the IOPLL Reconfig IP core, without the need to reconfigure the entire FPGA. The Intel^® Stratix^® 10 I/O PLL uses divide counters (N, M, and C counters) and a voltage-controlled oscillator (VCO) to synthesize the desired phase and frequency output.

You can use the IOPLL Reconfig IP core as follows:

• Memory Initialization File (.mif) streaming reconfiguration
  • Allows the I/O PLL reconfiguration using predefined settings saved in an on-chip ROM. You can store many unique PLL configurations in a single ROM.
  • The .mif file is generated automatically by the IOPLL IP core. Using the generated .mif file during .mif streaming reconfiguration ensures the legality of the new configuration.
  • Intel recommends using this reconfiguration method.
• Advanced mode reconfiguration
  • This method of reconfiguration is for advanced users. You must ensure the reconfigured PLL settings are within the legal range.
  • Enable the Advanced Reconfiguration option from the IOPLL Reconfig IP core to reconfigure the individual I/O PLL registers.
  • This method is error prone and may lead to the I/O PLL being reconfigured into an illegal configuration if the reconfiguration is done incorrectly.
• Recalibration of the I/O PLL using .mif
  • Perform recalibration of the I/O PLL without any reconfiguration.
  • Trigger recalibration if the reference clock frequency changes.
• I/O PLL clock gating
  • Gate and un-gate I/O PLL output clock 0 to output clock 7 of the I/O PLL.

You can perform dynamic phase shift using the IOPLL Reconfig IP core.

You can enable the PLL reconfiguration circuitry for the I/O PLL through the Avalon^® -MM interface in the IOPLL Reconfig IP core.

The IOPLL Reconfig IP core has four functional reconfiguration modes. The reconfiguration operation mode is based on the setting in the mgmt_address[9:8] bit.

After performing dynamic reconfiguration on the I/O PLL that changes the M counter, N counter, bandwidth setting, or charge pump current, the I/O PLL must be recalibrated. For .mif streaming reconfiguration, the recalibration is done automatically. For advanced mode reconfiguration, you must manually trigger the recalibration of the I/O PLL. Recalibration is not needed for clock gating and dynamic phase shift reconfiguration.

You must install the Intel^® Quartus^® Prime software version 17.1 or later. The software must be installed on a Windows* or Linux* computer that meets the Intel^® Quartus^® Prime software minimum requirements.

The IOPLL IP core parameter editor appears in the PLL category of the IP Catalog.

Assign a value of “0” for all the unused bits in the address bus and the data bus during reconfiguration operations.