Cyclone V Device Datasheet

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CV-51002 | 2019.11.27

Cyclone V Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Cyclone^® V devices.

Cyclone^® V devices are offered in commercial and industrial grades. Commercial devices are offered in –C6 (fastest), –C7, and –C8 speed grades. Industrial grade devices are offered in the –I7 speed grade. Automotive devices are offered in the –A7 speed grade.

Cyclone^® V SoC devices are also offered in a low-power variant, as indicated by the L power option in the device part number. These devices have 30% static power reduction for devices with 25K LE and 40K LE, and 20% static power reduction for devices with 85K LE and 110K LE. Note that the L power option devices are only available in –I7 speed grade, and have the equivalent operating conditions and timing specifications as the standard –I7 speed grade devices.

Table 1. Low Power Variants
Density	Ordering Part Number (OPN)	Static Power Reduction
25K LE	5CSEBA2U19I7LN	30%
	5CSEBA2U23I7LN
	5CSXFC2C6U23I7LN
40K LE	5CSEBA4U19I7LN
	5CSEBA4U23I7LN
	5CSXFC4C6U23I7LN
85K LE	5CSEBA5U19I7LN	20%
	5CSEBA5U23I7LN
	5CSXC5C6U23I7LN
110K LE	5CSEBA6U19I7LN
	5CSEBA6U23I7LN
	5CSXFC6C6U23I7LN

To estimate total power consumption for a low-power device, listed in Table 1:

Multiply the Total Static Power reported by the Early Power Estimator (EPE) by the appropriate scale factor:
- For 25K LE and 40K LE devices, use 0.7
- For 85K LE and 110K LE devices, use 0.8
Add the result from Step 1 to the Total Dynamic Power reported by the EPE.

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Cyclone^® V devices.

Operating Conditions

Cyclone^® V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Cyclone^® V devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions for Cyclone^® V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms.

The functional operation of the device is not implied for these conditions.

CAUTION:

Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 2. Absolute Maximum Ratings for Cyclone^® V Devices
Symbol	Description	Minimum	Maximum	Unit
V_CC	Core voltage and periphery circuitry power supply	–0.5	1.43	V
V_CCPGM	Configuration pins power supply	–0.5	3.90	V
V_{CC_AUX}	Auxiliary supply	–0.5	3.25	V
V_CCBAT	Battery back-up power supply for design security volatile key register	–0.5	3.90	V
V_CCPD	I/O pre-driver power supply	–0.5	3.90	V
V_CCIO	I/O power supply	–0.5	3.90	V
V_{CCA_FPLL}	Phase-locked loop (PLL) analog power supply	–0.5	3.25	V
V_{CCH_GXB}	Transceiver high voltage power	–0.5	3.25	V
V_{CCE_GXB}	Transceiver power	–0.5	1.50	V
V_{CCL_GXB}	Transceiver clock network power	–0.5	1.50	V
V_I	DC input voltage	–0.5	3.80	V
V_{CC_HPS}	HPS core voltage and periphery circuitry power supply	–0.5	1.43	V
V_{CCPD_HPS}	HPS I/O pre-driver power supply	–0.5	3.90	V
V_{CCIO_HPS}	HPS I/O power supply	–0.5	3.90	V
V_{CCRSTCLK_HPS}	HPS reset and clock input pins power supply	–0.5	3.90	V
V_{CCPLL_HPS}	HPS PLL analog power supply	–0.5	3.25	V
V_{CC_AUX_SHARED} ¹	HPS auxiliary power supply	–0.5	3.25	V
I_OUT	DC output current per pin	–25	40	mA
T_J	Operating junction temperature	–55	125	°C
T_STG	Storage temperature (no bias)	–65	150	°C

¹ V_{CC_AUX_SHARED} must be powered by the same source as V_{CC_AUX} for Cyclone^® V SX C5, C6, D5, and D6 devices, and Cyclone^® V SE A5 and A6 devices.

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.

The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years.

Table 3. Maximum Allowed Overshoot During Transitions for Cyclone^® V DevicesThis table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
Symbol	Description	Condition (V)	Overshoot Duration as % of High Time	Unit
Vi (AC)	AC input voltage	3.8	100	%
		3.85	68	%
		3.9	45	%
		3.95	28	%
		4	15	%
		4.05	13	%
		4.1	11	%
		4.15	9	%
		4.2	8	%
		4.25	7	%
		4.3	5.4	%
		4.35	3.2	%
		4.4	1.9	%
		4.45	1.1	%
		4.5	0.6	%
		4.55	0.4	%
		4.6	0.2	%

For an overshoot of 3.8 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal.

Figure 1. Cyclone^® V Devices Overshoot Duration

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for Cyclone^® V devices.

Recommended Operating Conditions

Table 4. Recommended Operating Conditions for Cyclone^® V DevicesThis table lists the steady-state voltage values expected from Cyclone^® V devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol	Description	Condition	Minimum ²	Typical	Maximum²	Unit
V_CC	Core voltage, periphery circuitry power supply, transceiver physical coding sublayer (PCS) power supply, and transceiver PCI Express* ( PCIe* ) hard IP digital power supply	Devices without internal scrubbing feature	1.07	1.1	1.13	V
V_CC		Devices with internal scrubbing feature (with SC suffix) ³	1.12	1.15	1.18	V
V_{CC_AUX}	Auxiliary supply	—	2.375	2.5	2.625	V
V_CCPD ⁴	I/O pre-driver power supply	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3.0	3.15	V
		2.5 V	2.375	2.5	2.625	V
V_CCIO	I/O buffers power supply	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3.0	3.15	V
		2.5 V	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
		1.5 V	1.425	1.5	1.575	V
		1.35 V	1.283	1.35	1.418	V
		1.25 V	1.19	1.25	1.31	V
		1.2 V	1.14	1.2	1.26	V
V_CCPGM	Configuration pins power supply	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3.0	3.15	V
		2.5 V	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
V_{CCA_FPLL} ⁵	PLL analog voltage regulator power supply	—	2.375	2.5	2.625	V
V_CCBAT ⁶	Battery back-up power supply (For design security volatile key register)	—	1.2	—	3.0	V
V_I	DC input voltage	—	–0.5	—	3.6	V
V_O	Output voltage	—	0	—	V_CCIO	V
T_J	Operating junction temperature	Commercial	0	—	85	°C
		Industrial	–40	—	100	°C
		Automotive	–40	—	125	°C
t_RAMP ⁷	Power supply ramp time	Standard POR	200µs	—	100ms	—
t_RAMP ⁷	Power supply ramp time	Fast POR	200µs	—	4ms	—

² The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

³ The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel sales representatives.

⁴ V_CCPD must be 2.5 V when V_CCIO is 2.5, 1.8, 1.5, 1.35, 1.25, or 1.2 V. V_CCPD must be 3.0 V when V_CCIO is 3.0 V. V_CCPD must be 3.3 V when V_CCIO is 3.3 V.

⁵ PLL digital voltage is regulated from V_{CCA_FPLL}.

⁶ If you do not use the design security feature in Cyclone^® V devices, connect V_CCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Cyclone^® V power-on reset (POR) circuitry monitors V_CCBAT. Cyclone^® V devices do not exit POR if V_CCBAT is not powered up.

⁷ This is also applicable to HPS power supply. For HPS power supply, refer to t_RAMP specifications for standard POR when HPS_PORSEL = 0 and t_RAMP specifications for fast POR when HPS_PORSEL = 1.

Transceiver Power Supply Operating Conditions

Table 5. Transceiver Power Supply Operating Conditions for Cyclone^® V GX, GT, SX, and ST Devices
Symbol	Description	Minimum ⁸	Typical	Maximum⁸	Unit
V_{CCH_GXBL}	Transceiver high voltage power (left side)	2.375	2.5	2.625	V
V_{CCE_GXBL} ⁹ ¹⁰	Transmitter and receiver power (left side)	1.07/1.17	1.1/1.2	1.13/1.23	V
V_{CCL_GXBL} ⁹ ¹⁰	Clock network power (left side)	1.07/1.17	1.1/1.2	1.13/1.23	V

⁸ The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

⁹ Intel recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for Cyclone^® V GT and ST FPGA systems which require full compliance to the PCIe* Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone^® V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone^® V Devices chapter.

¹⁰ Intel recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps ( Cyclone^® V GT and ST devices) and 6.144Gbps ( Cyclone^® V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone^® V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone^® V Devices chapter.

HPS Power Supply Operating Conditions

Table 6. HPS Power Supply Operating Conditions for Cyclone^® V SX and ST DevicesThis table lists the steady-state voltage and current values expected from Cyclone^® V system-on-a-chip (SoC) devices with Arm* -based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions for Cyclone^® V Devices table for the steady-state voltage values expected from the FPGA portion of the Cyclone^® V SoC devices.
Symbol	Description	Condition	Minimum ¹¹	Typical	Maximum¹¹	Unit
V_{CC_HPS}	HPS core voltage and periphery circuitry power supply	—	1.07	1.1	1.13	V
V_{CCPD_HPS} ¹²	HPS I/O pre-driver power supply	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3.0	3.15	V
		2.5 V	2.375	2.5	2.625	V
V_{CCIO_HPS}	HPS I/O buffers power supply	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3.0	3.15	V
		2.5 V	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
		1.5 V	1.425	1.5	1.575	V
		1.35 V ¹³	1.283	1.35	1.418	V
		1.2 V	1.14	1.2	1.26	V
V_{CCRSTCLK_HPS}	HPS reset and clock input pins power supply	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3.0	3.15	V
		2.5 V	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
V_{CCPLL_HPS}	HPS PLL analog voltage regulator power supply	—	2.375	2.5	2.625	V
V_{CC_AUX_SHARED} ¹⁴	HPS auxiliary power supply	—	2.375	2.5	2.625	V

¹¹ The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

¹² V_{CCPD_HPS} must be 2.5 V when V_{CCIO_HPS} is 2.5, 1.8, 1.5, or 1.2 V. V_{CCPD_HPS} must be 3.0 V when V_{CCIO_HPS} is 3.0 V. V_{CCPD_HPS} must be 3.3 V when V_{CCIO_HPS} is 3.3 V.

¹³ V_{CCIO_HPS} 1.35 V is supported for HPS row I/O bank only.

¹⁴ V_{CC_AUX_SHARED} must be powered by the same source as V_{CC_AUX} for Cyclone^® V SX C5, C6, D5, and D6 devices, and Cyclone^® V SE A5 and A6 devices.

DC Characteristics

Supply Current and Power Consumption

Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer feature.

Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the resources you use.

The Intel^® Quartus^® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates.

I/O Pin Leakage Current

Table 7. I/O Pin Leakage Current for Cyclone^® V Devices
Symbol	Description	Condition	Min	Typ	Max	Unit
I_I	Input pin	V_I = 0 V to V_CCIOMAX	–30	—	30	µA
I_OZ	Tri-stated I/O pin	V_O = 0 V to V_CCIOMAX	–30	—	30	µA

Bus Hold Specifications

Table 8. Bus Hold Parameters for Cyclone^® V DevicesThe bus-hold trip points are based on calculated input voltages from the JEDEC* standard.
Parameter	Symbol	Condition	V_CCIO (V)												Unit
			1.2		1.5		1.8		2.5		3.0		3.3
			Min	Max	Min	Max	Min	Max	Min	Max	Min	Max	Min	Max
Bus-hold, low, sustaining current	I_SUSL	V_IN > V_IL (max)	8	—	12	—	30	—	50	—	70	—	70	—	µA
Bus-hold, high, sustaining current	I_SUSH	V_IN < V_IH (min)	–8	—	–12	—	–30	—	–50	—	–70	—	–70	—	µA
Bus-hold, low, overdrive current	I_ODL	0 V < V_IN < V_CCIO	—	125	—	175	—	200	—	300	—	500	—	500	µA
Bus-hold, high, overdrive current	I_ODH	0 V <V_IN <V_CCIO	—	–125	—	–175	—	–200	—	–300	—	–500	—	–500	µA
Bus-hold trip point	V_TRIP	—	0.3	0.9	0.375	1.125	0.68	1.07	0.7	1.7	0.8	2	0.8	2	V

OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.

Table 9. OCT Calibration Accuracy Specifications for Cyclone^® V DevicesCalibration accuracy for the calibrated on-chip series termination (R_S OCT) and on-chip parallel termination (R_T OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Symbol	Description	Condition (V)	Calibration Accuracy			Unit
Symbol	Description	Condition (V)	–C6	–I7, –C7	–C8, –A7	Unit
25-Ω R_S	Internal series termination with calibration (25-Ω setting)	V_CCIO = 3.0, 2.5, 1.8, 1.5, 1.2	±15	±15	±15	%
50-Ω R_S	Internal series termination with calibration (50-Ω setting)	V_CCIO = 3.0, 2.5, 1.8, 1.5, 1.2	±15	±15	±15	%
34-Ω and 40-Ω R_S	Internal series termination with calibration (34-Ω and 40-Ω setting)	V_CCIO = 1.5, 1.35, 1.25, 1.2	±15	±15	±15	%
48-Ω, 60-Ω, and 80-Ω R_S	Internal series termination with calibration (48-Ω, 60-Ω, and 80-Ω setting)	V_CCIO = 1.2	±15	±15	±15	%
50-Ω R_T	Internal parallel termination with calibration (50-Ω setting)	V_CCIO = 2.5, 1.8, 1.5, 1.2	–10 to +40	–10 to +40	–10 to +40	%
20-Ω, 30-Ω, 40-Ω,60-Ω, and 120-Ω R_T	Internal parallel termination with calibration (20-Ω, 30-Ω, 40-Ω, 60-Ω, and 120-Ω setting)	V_CCIO = 1.5, 1.35, 1.25	–10 to +40	–10 to +40	–10 to +40	%
60-Ω and 120-Ω R_T	Internal parallel termination with calibration (60-Ω and 120-Ω setting)	V_CCIO = 1.2	–10 to +40	–10 to +40	–10 to +40	%
25-Ω R_{S_left_shift}	Internal left shift series termination with calibration (25-Ω R_{S_left_shift} setting)	V_CCIO = 3.0, 2.5, 1.8, 1.5, 1.2	±15	±15	±15	%

OCT Without Calibration Resistance Tolerance Specifications

Table 10. OCT Without Calibration Resistance Tolerance Specifications for Cyclone^® V DevicesThis table lists the Cyclone^® V OCT without calibration resistance tolerance to PVT changes.
Symbol	Description	Condition (V)	Resistance Tolerance			Unit
Symbol	Description	Condition (V)	–C6	–I7, –C7	–C8, –A7	Unit
25-Ω R_S	Internal series termination without calibration (25-Ω setting)	V_CCIO = 3.0, 2.5	±30	±40	±40	%
25-Ω R_S	Internal series termination without calibration (25-Ω setting)	V_CCIO = 1.8, 1.5	±30	±40	±40	%
25-Ω R_S	Internal series termination without calibration (25-Ω setting)	V_CCIO = 1.2	±35	±50	±50	%
50-Ω R_S	Internal series termination without calibration (50-Ω setting)	V_CCIO = 3.0, 2.5	±30	±40	±40	%
50-Ω R_S	Internal series termination without calibration (50-Ω setting)	V_CCIO = 1.8, 1.5	±30	±40	±40	%
50-Ω R_S	Internal series termination without calibration (50-Ω setting)	V_CCIO = 1.2	±35	±50	±50	%
100-Ω R_D	Internal differential termination (100-Ω setting)	V_CCIO = 2.5	±25	±40	±40	%

Figure 2. Equation for OCT Variation Without Recalibration

The definitions for the equation are as follows:

The R_OCT value calculated shows the range of OCT resistance with the variation of temperature and V_CCIO.
R_SCAL is the OCT resistance value at power-up.
ΔT is the variation of temperature with respect to the temperature at power up.
ΔV is the variation of voltage with respect to the V_CCIO at power up.
dR/dT is the percentage change of R_SCAL with temperature.
dR/dV is the percentage change of R_SCAL with voltage.

OCT Variation after Power-Up Calibration

Table 11. OCT Variation after Power-Up Calibration for Cyclone^® V DevicesThis table lists OCT variation with temperature and voltage after power-up calibration. The OCT variation is valid for a V_CCIO range of ±5% and a temperature range of 0°C to 85°C.
Symbol	Description	V_CCIO (V)	Value	Unit
dR/dV	OCT variation with voltage without recalibration	3.0	0.100	%/mV
		2.5	0.100
		1.8	0.100
		1.5	0.100
		1.35	0.150
		1.25	0.150
		1.2	0.150
dR/dT	OCT variation with temperature without recalibration	3.0	0.189	%/°C
		2.5	0.208
		1.8	0.266
		1.5	0.273
		1.35	0.200
		1.25	0.200
		1.2	0.317

Pin Capacitance

Table 12. Pin Capacitance for Cyclone^® V Devices
Symbol	Description	Maximum	Unit
C_IOTB	Input capacitance on top and bottom I/O pins	6	pF
C_IOLR	Input capacitance on left and right I/O pins	6	pF
C_OUTFB	Input capacitance on dual-purpose clock output and feedback pins	6	pF

Hot Socketing

Table 13. Hot Socketing Specifications for Cyclone^® V Devices
Symbol	Description	Maximum	Unit
I_{IOPIN (DC)}	DC current per I/O pin	300	μA
I_{IOPIN (AC)}	AC current per I/O pin	8¹⁵	mA
I_{XCVR-TX (DC)}	DC current per transceiver transmitter (TX) pin	100	mA
I_{XCVR-RX (DC)}	DC current per transceiver receiver (RX) pin	50	mA

¹⁵ The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I_IOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate.

Internal Weak Pull-Up Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.

Table 14. Internal Weak Pull-Up Resistor Values for Cyclone^® V Devices
Symbol	Description	Condition (V)¹⁶	Value¹⁷	Unit
R_PU	Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option.	V_CCIO = 3.3 ±5%	25	kΩ
		V_CCIO = 3.0 ±5%	25	kΩ
		V_CCIO = 2.5 ±5%	25	kΩ
		V_CCIO = 1.8 ±5%	25	kΩ
		V_CCIO = 1.5 ±5%	25	kΩ
		V_CCIO = 1.35 ±5%	25	kΩ
		V_CCIO = 1.25 ±5%	25	kΩ
		V_CCIO = 1.2 ±5%	25	kΩ

¹⁶ Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO.

¹⁷ Valid with ±10% tolerances to cover changes over PVT.

I/O Standard Specifications

Tables in this section list the input voltage (V_IH and V_IL), output voltage (V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O standards supported by Cyclone^® V devices.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Single-Ended I/O Standards

Table 15. Single-Ended I/O Standards for Cyclone^® V Devices
I/O Standard	V_CCIO (V)			V_IL (V)		V_IH (V)		V_OL (V)	V_OH (V)	I_OL ¹⁸ (mA)	I_OH ¹⁸ (mA)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Max	Min	I_OL ¹⁸ (mA)	I_OH ¹⁸ (mA)
3.3-V LVTTL	3.135	3.3	3.465	–0.3	0.8	1.7	3.6	0.45	2.4	4	–4
3.3-V LVCMOS	3.135	3.3	3.465	–0.3	0.8	1.7	3.6	0.2	V_CCIO – 0.2	2	–2
3.0-V LVTTL	2.85	3	3.15	–0.3	0.8	1.7	3.6	0.4	2.4	2	–2
3.0-V LVCMOS	2.85	3	3.15	–0.3	0.8	1.7	3.6	0.2	V_CCIO – 0.2	0.1	–0.1
3.0-V PCI*	2.85	3	3.15	—	0.3 × V_CCIO	0.5 × V_CCIO	V_CCIO + 0.3	0.1 × V_CCIO	0.9 × V_CCIO	1.5	–0.5
3.0-V PCI* -X	2.85	3	3.15	—	0.35 × V_CCIO	0.5 × V_CCIO	V_CCIO + 0.3	0.1 × V_CCIO	0.9 × V_CCIO	1.5	–0.5
2.5 V	2.375	2.5	2.625	–0.3	0.7	1.7	3.6	0.4	2	1	–1
1.8 V	1.71	1.8	1.89	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.45	V_CCIO – 0.45	2	–2
1.5 V	1.425	1.5	1.575	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2
1.2 V	1.14	1.2	1.26	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2

¹⁸ To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Cyclone^® V Devices
I/O Standard	V_CCIO (V)			V_REF (V)			V_TT (V)
I/O Standard	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max
SSTL-2 Class I, II	2.375	2.5	2.625	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	V_REF – 0.04	V_REF	V_REF + 0.04
SSTL-18 Class I, II	1.71	1.8	1.89	0.833	0.9	0.969	V_REF – 0.04	V_REF	V_REF + 0.04
SSTL-15 Class I, II	1.425	1.5	1.575	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-135 Class I, II	1.283	1.35	1.418	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-125 Class I, II	1.19	1.25	1.26	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
HSTL-18 Class I, II	1.71	1.8	1.89	0.85	0.9	0.95	—	V_CCIO/2	—
HSTL-15 Class I, II	1.425	1.5	1.575	0.68	0.75	0.9	—	V_CCIO/2	—
HSTL-12 Class I, II	1.14	1.2	1.26	0.47 × V_CCIO	0.5 × V_CCIO	0.53 × V_CCIO	—	V_CCIO/2	—
HSUL-12	1.14	1.2	1.3	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	—	—	—

Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

Table 17. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone^® V Devices
I/O Standard	V_IL(DC) (V)		V_IH(DC) (V)		V_IL(AC) (V)	V_IH(AC) (V)	V_OL (V)	V_OH (V)	I_OL ¹⁹ (mA)	I_OH ¹⁹ (mA)
I/O Standard	Min	Max	Min	Max	Max	Min	Max	Min	I_OL ¹⁹ (mA)	I_OH ¹⁹ (mA)
SSTL-2 Class I	–0.3	V_REF – 0.15	V_REF + 0.15	V_CCIO + 0.3	V_REF – 0.31	V_REF + 0.31	V_TT – 0.608	V_TT + 0.608	8.1	–8.1
SSTL-2 Class II	–0.3	V_REF – 0.15	V_REF + 0.15	V_CCIO + 0.3	V_REF – 0.31	V_REF + 0.31	V_TT – 0.81	V_TT + 0.81	16.2	–16.2
SSTL-18 Class I	–0.3	V_REF – 0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	V_TT – 0.603	V_TT + 0.603	6.7	–6.7
SSTL-18 Class II	–0.3	V_REF – 0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	0.28	V_CCIO – 0.28	13.4	–13.4
SSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	8	–8
SSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	16	–16
SSTL-135	—	V_REF – 0.09	V_REF + 0.09	—	V_REF – 0.16	V_REF + 0.16	0.2 × V_CCIO	0.8 × V_CCIO	—	—
SSTL-125	—	V_REF – 0.85	V_REF + 0.85	—	V_REF – 0.15	V_REF + 0.15	0.2 × V_CCIO	0.8 × V_CCIO	—	—
HSTL-18 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-18 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	16	–16
HSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	16	–16
HSTL-12 Class I	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF + 0.15	0.25 × V_CCIO	0.75 × V_CCIO	8	–8
HSTL-12 Class II	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO+ 0.15	V_REF – 0.15	V_REF + 0.15	0.25 × V_CCIO	0.75 × V_CCIO	16	–16
HSUL-12	—	V_REF – 0.13	V_REF + 0.13	—	V_REF – 0.22	V_REF + 0.22	0.1 × V_CCIO	0.9 × V_CCIO	—	—

¹⁹ To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Differential SSTL I/O Standards

Table 18. Differential SSTL I/O Standards for Cyclone^® V Devices
I/O Standard	V_CCIO (V)			V_SWING(DC) (V)		V_X(AC) (V)			V_SWING(AC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Typ	Max	Min	Max
SSTL-2 Class I, II	2.375	2.5	2.625	0.3	V_CCIO + 0.6	V_CCIO/2 – 0.2	—	V_CCIO/2 + 0.2	0.62	V_CCIO + 0.6
SSTL-18 Class I, II	1.71	1.8	1.89	0.25	V_CCIO + 0.6	V_CCIO/2 – 0.175	—	V_CCIO/2 + 0.175	0.5	V_CCIO + 0.6
SSTL-15 Class I, II	1.425	1.5	1.575	0.2	²⁰	V_CCIO/2 – 0.15	—	V_CCIO/2 + 0.15	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)
SSTL-135	1.283	1.35	1.45	0.18	²⁰	V_CCIO/2 – 0.15	V_CCIO/2	V_CCIO/2 + 0.15	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)
SSTL-125	1.19	1.25	1.31	0.18	²⁰	V_CCIO/2 – 0.15	V_CCIO/2	V_CCIO/2 + 0.15	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)

²⁰ The maximum value for V_SWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC) and V_IL(DC)).

Differential HSTL and HSUL I/O Standards

Table 19. Differential HSTL and HSUL I/O Standards for Cyclone^® V Devices
I/O Standard	V_CCIO (V)			V_DIF(DC) (V)		V_X(AC) (V)			V_CM(DC) (V)			V_DIF(AC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Typ	Max	Min	Typ	Max	Min	Max
HSTL-18 Class I, II	1.71	1.8	1.89	0.2	—	0.78	—	1.12	0.78	—	1.12	0.4	—
HSTL-15 Class I, II	1.425	1.5	1.575	0.2	—	0.68	—	0.9	0.68	—	0.9	0.4	—
HSTL-12 Class I, II	1.14	1.2	1.26	0.16	V_CCIO + 0.3	—	0.5 × V_CCIO	—	0.4 × V_CCIO	0.5 × V_CCIO	0.6 × V_CCIO	0.3	V_CCIO + 0.48
HSUL-12	1.14	1.2	1.3	0.26	0.26	0.5 × V_CCIO – 0.12	0.5 × V_CCIO	0.5 × V_CCIO + 0.12	0.4 × V_CCIO	0.5 × V_CCIO	0.6 × V_CCIO	0.44	0.44

Differential I/O Standard Specifications

Table 20. **Differential I/O Standard Specifications for Cyclone^® V Devices** Differential inputs are powered by V_CCPD which requires 2.5 V.
I/O Standard	V_CCIO (V)			V_ID (mV)²¹			V_ICM(DC) (V)			V_OD (V) ²²			V_OCM (V)²² ²³
I/O Standard	Min	Typ	Max	Min	Condition	Max	Min	Condition	Max	Min	Typ	Max	Min	Typ	Max
PCML	Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to Transceiver Specifications for Cyclone^® V GX, GT, SX, and ST Devices table.
2.5 V LVDS²⁴	2.375	2.5	2.625	100	V_CM = 1.25 V	—	0.05	D_MAX ≤ 700 Mbps	1.80	0.247	—	0.6	1.125	1.25	1.375
2.5 V LVDS²⁴	2.375	2.5	2.625	100	V_CM = 1.25 V	—	1.05	D_MAX > 700 Mbps	1.55	0.247	—	0.6	1.125	1.25	1.375
BLVDS²⁵ ²⁶	2.375	2.5	2.625	100	—	—	—	—	—	—	—	—	—	—	—
RSDS (HIO)²⁷	2.375	2.5	2.625	100	V_CM = 1.25 V	—	0.25	—	1.45	0.1	0.2	0.6	0.5	1.2	1.4
Mini-LVDS (HIO)²⁸	2.375	2.5	2.625	200	—	600	0.300	—	1.425	0.25	—	0.6	1	1.2	1.4
LVPECL²⁹	—	—	—	300	—	—	0.60	D_MAX ≤ 700 Mbps	1.80	—	—	—	—	—	—
LVPECL²⁹	—	—	—	300	—	—	1.00	D_MAX > 700 Mbps	1.60	—	—	—	—	—	—
SLVS	2.375	2.5	2.625	100	V_CM = 1.25 V	—	0.05	—	1.80	—	—	—	—	—	—
Sub-LVDS	2.375	2.5	2.625	100	V_CM = 1.25 V	—	0.05	—	1.80	—	—	—	—	—	—
HiSpi	2.375	2.5	2.625	100	V_CM = 1.25 V	—	0.05	—	1.80	—	—	—	—	—	—

²¹ The minimum V_ID value is applicable over the entire common mode range, V_CM.

²² R_L range: 90 ≤ R_L ≤ 110 Ω.

²³ This applies to default pre-emphasis setting only.

²⁴ For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rate above 700 Mbps and 0.00 V to 1.85 V for data rate below 700 Mbps.

²⁵ There are no fixed V_ICM, V_OD, and V_OCM specifications for BLVDS. They depend on the system topology.

²⁶ For more information about BLVDS interface support in Intel devices, refer to AN522: Implementing Bus LVDS Interface in Supported Intel Device Families.

²⁷ For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.

²⁸ For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.

²⁹ For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to 1.95 V for data rate below 700 Mbps.

Switching Characteristics

This section provides performance characteristics of Cyclone^® V core and periphery blocks.

Transceiver Performance Specifications

Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Table 21. Reference Clock Specifications for Cyclone^® V GX, GT, SX, and ST Devices
Symbol/Description	Condition	Transceiver Speed Grade 5 ³⁰			Transceiver Speed Grade 6			Transceiver Speed Grade 7			Unit
Symbol/Description	Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
Supported I/O standards	1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL³¹, HCSL, and LVDS
Input frequency from `REFCLK` input pins³²	—	27	—	550	27	—	550	27	—	550	MHz
Rise time	Measure at ±60 mV of differential signal ³³	—	—	400	—	—	400	—	—	400	ps
Fall time	Measure at ±60 mV of differential signal³³	—	—	400	—	—	400	—	—	400	ps
Duty cycle	—	45	—	55	45	—	55	45	—	55	%
Peak-to-peak differential input voltage	—	200	—	2000	200	—	2000	200	—	2000	mV
Spread-spectrum modulating clock frequency	PCIe*	30	—	33	30	—	33	30	—	33	kHz
Spread-spectrum downspread	PCIe*	—	0 to –0.5%	—	—	0 to –0.5%	—	—	0 to –0.5%	—	—
On-chip termination resistors	—	—	100	—	—	100	—	—	100	—	Ω
V_ICM (AC coupled)	—	V_{CCE_GXBL} supply ³⁴ ³⁵			V_{CCE_GXBL} supply			V_{CCE_GXBL} supply			V
V_ICM (DC coupled)	HCSL I/O standard for the PCIe* reference clock	250	—	550	250	—	550	250	—	550	mV
Transmitter `REFCLK` phase noise³⁶	10 Hz	—	—	–50	—	—	–50	—	—	–50	dBc/Hz
	100 Hz	—	—	–80	—	—	–80	—	—	–80	dBc/Hz
	1 KHz	—	—	–110	—	—	–110	—	—	–110	dBc/Hz
	10 KHz	—	—	–120	—	—	–120	—	—	–120	dBc/Hz
	100 KHz	—	—	–120	—	—	–120	—	—	–120	dBc/Hz
	≥1 MHz	—	—	–130	—	—	–130	—	—	–130	dBc/Hz
R_REF	—	—	2000 ±1%	—	—	2000 ±1%	—	—	2000 ±1%	—	Ω

Table 22. Transceiver Clocks Specifications for Cyclone^® V GX, GT, SX, and ST Devices
Symbol/Description	Condition	Transceiver Speed Grade 5³⁰			Transceiver Speed Grade 6			Transceiver Speed Grade 7			Unit
Symbol/Description	Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
`fixedclk` clock frequency	PCIe* Receiver Detect	—	125	—	—	125	—	—	125	—	MHz
Transceiver Reconfiguration Controller IP (`mgmt_clk_clk`) clock frequency	—	75	—	100/125 ³⁷	75	—	100/125³⁷	75	—	100/125³⁷	MHz

Table 23. Receiver Specifications for Cyclone^® V GX, GT, SX, and ST Devices
Symbol/Description	Condition	Transceiver Speed Grade 5³⁰			Transceiver Speed Grade 6			Transceiver Speed Grade 7			Unit
Symbol/Description	Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
Supported I/O standards	1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate³⁸	—	614	—	5000/6144³⁵	614	—	3125	614	—	2500	Mbps
Absolute V_MAX for a receiver pin³⁹	—	—	—	1.2	—	—	1.2	—	—	1.2	V
Absolute V_MIN for a receiver pin	—	–0.4	—	—	–0.4	—	—	–0.4	—	—	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) before device configuration	—	—	—	1.6	—	—	1.6	—	—	1.6	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) after device configuration	—	—	—	2.2	—	—	2.2	—	—	2.2	V
Minimum differential eye opening at the receiver serial input pins⁴⁰	—	110	—	—	110	—	—	110	—	—	mV
Differential on-chip termination resistors	85-Ω setting	—	85	—	—	85	—	—	85	—	Ω
	100-Ω setting	—	100	—	—	100	—	—	100	—	Ω
	120-Ω setting	—	120	—	—	120	—	—	120	—	Ω
	150-Ω setting	—	150	—	—	150	—	—	150	—	Ω
V_ICM (AC coupled)	2.5 V PCML, LVPECL, and LVDS	V_{CCE_GXBL} supply³⁴ ³⁵			V_{CCE_GXBL} supply			V_{CCE_GXBL} supply			V
V_ICM (AC coupled)	1.5 V PCML	0.65/0.75/0.8 ⁴¹									V
t_LTR ⁴²	—	—	—	10	—	—	10	—	—	10	µs
t_LTD ⁴³	—	—	—	4	—	—	4	—	—	4	µs
t_{LTD_manual} ⁴⁴	—	—	—	4	—	—	4	—	—	4	µs
t_{LTR_LTD_manual} ⁴⁵	—	15	—	—	15	—	—	15	—	—	µs
Programmable ppm detector⁴⁶	—	±62.5, 100, 125, 200, 250, 300, 500, and 1000									ppm
Run length	—	—	—	200	—	—	200	—	—	200	UI
Programmable equalization AC and DC gain	AC gain setting = 0 to 3 ⁴⁷ DC gain setting = 0 to 1	Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone^® V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone^® V GX, GT, SX, and ST Devices diagrams.									dB

Table 24. Transmitter Specifications for Cyclone^® V GX, GT, SX, and ST Devices
Symbol/Description	Condition	Transceiver Speed Grade 5³⁰			Transceiver Speed Grade 6			Transceiver Speed Grade 7			Unit
Symbol/Description	Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
Supported I/O standards	1.5 V PCML
Data rate	—	614	—	5000/6144³⁵	614	—	3125	614	—	2500	Mbps
V_OCM (AC coupled)	—	—	650	—	—	650	—	—	650	—	mV
Differential on-chip termination resistors	85-Ω setting	—	85	—	—	85	—	—	85	—	Ω
	100-Ω setting	—	100	—	—	100	—	—	100	—	Ω
	120-Ω setting	—	120	—	—	120	—	—	120	—	Ω
	150-Ω setting	—	150	—	—	150	—	—	150	—	Ω
Intra-differential pair skew	TX V_CM = 0.65 V and slew rate of 15 ps	—	—	15	—	—	15	—	—	15	ps
Intra-transceiver block transmitter channel-to-channel skew	×6 PMA bonded mode	—	—	180	—	—	180	—	—	180	ps
Inter-transceiver block transmitter channel-to-channel skew	×`N` PMA bonded mode	—	—	500	—	—	500	—	—	500	ps

Table 25. CMU PLL Specifications for Cyclone^® V GX, GT, SX, and ST Devices
Symbol/Description	Condition	Transceiver Speed Grade 5³⁰			Transceiver Speed Grade 6			Transceiver Speed Grade 7			Unit
Symbol/Description	Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
Supported data range	—	614	—	5000/6144³⁵	614	—	3125	614	—	2500	Mbps
fPLL supported data range	—	614	—	3125	614	—	3125	614	—	2500	Mbps

Table 26. Transceiver-FPGA Fabric Interface Specifications for Cyclone^® V GX, GT, SX, and ST Devices
Symbol/Description	Condition	Transceiver Speed Grade 5³⁰			Transceiver Speed Grade 6			Transceiver Speed Grade 7			Unit
Symbol/Description	Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
Interface speed (single-width mode)	—	25	—	187.5	25	—	187.5	25	—	163.84	MHz
Interface speed (double-width mode)	—	25	—	163.84	25	—	163.84	25	—	156.25	MHz

³⁰ Transceiver Speed Grade 5 covers specifications for Cyclone^® V GT and ST devices.

³¹ Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.

³² The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone^® V Devices chapter.

³³ REFCLK performance requires to meet transmitter REFCLK phase noise specification.

³⁴ Intel recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for Cyclone^® V GT and ST FPGA systems which require full compliance to the PCIe* Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone^® V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone^® V Devices chapter.

³⁵ Intel recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps ( Cyclone^® V GT and ST devices) and 6.144 Gbps ( Cyclone^® V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone^® V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone^® V Devices chapter.

³⁶ The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10^-12.

³⁷ The maximum supported clock frequency is 100 MHz if the PCIe* hard IP block is enabled or 125 MHz if the PCIe* hard IP block is not enabled.

³⁸ To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.

³⁹ The device cannot tolerate prolonged operation at this absolute maximum.

⁴⁰ The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

⁴¹ The AC coupled V_ICM = 650 mV for Cyclone^® V GX and SX in PCIe* mode only. The AC coupled V_ICM = 750mV for Cyclone^® V GT and ST in PCIe* mode only.

⁴² t_LTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset.

⁴³ t_LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.

⁴⁴ t_{LTD_manual} is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.

⁴⁵ t_{LTR_LTD_manual} is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

⁴⁶ The rate matcher supports only up to ±300 parts per million (ppm).

⁴⁷ The Intel^® Quartus^® Prime software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.

CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain

Figure 3. Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone^® V GX, GT, SX, and ST Devices

CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain

Figure 4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone^® V GX, GT, SX, and ST Devices

Typical TX VOD Setting for Cyclone V Transceiver Channels with termination of 100 Ω

Table 27. Typical TX V_OD Setting for Cyclone^® V Transceiver Channels with termination of 100 Ω
Symbol	V_OD Setting ⁴⁸	V_OD Value (mV)	V_OD Setting⁴⁸	V_OD Value (mV)
V_OD differential peak-to-peak typical	6 ⁴⁹	120	34	680
	7⁴⁹	140	35	700
	8⁴⁹	160	36	720
	9	180	37	740
	10	200	38	760
	11	220	39	780
	12	240	40	800
	13	260	41	820
	14	280	42	840
	15	300	43	860
	16	320	44	880
	17	340	45	900
	18	360	46	920
	19	380	47	940
	20	400	48	960
	21	420	49	980
	22	440	50	1000
	23	460	51	1020
	24	480	52	1040
	25	500	53	1060
	26	520	54	1080
	27	540	55	1100
	28	560	56	1120
	29	580	57	1140
	30	600	58	1160
	31	620	59	1180
	32	640	60	1200
	33	660

⁴⁸ Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls.

⁴⁹ Only valid for data rates ≤ 5 Gbps.

Transmitter Pre-Emphasis Levels

The following table lists the simulation data on the transmitter pre-emphasis levels in dB for the first post tap under the following conditions:

Low-frequency data pattern—five 1s and five 0s
Data rate—2.5 Gbps

The levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the pre-emphasis levels may change with data pattern and data rate.

Cyclone^® V devices only support 1st post tap pre-emphasis with the following conditions:

The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = V_OD setting with termination value, R_TERM = 100 Ω and |C| = 1st post tap pre-emphasis setting.
|B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps.
(V_MAX/V_MIN – 1)% < 600%, where V_MAX = |B| + |C| and V_MIN = |B| – |C|.

Exceptions for PCIe* Gen2 design:

V_OD setting = 50 and pre-emphasis setting = 22 are allowed for PCIe* Gen2 design with transmit de-emphasis –6dB setting (pipe_txdeemp = 1’b0) using Intel^® PCIe* Hard IP and PIPE IP cores.
V_OD setting = 50 and pre-emphasis setting = 12 are allowed for PCIe* Gen2 design with transmit de-emphasis –3.5dB setting (pipe_txdeemp = 1’b1) using Intel^® PCIe* Hard IP and PIPE IP cores.

For example, when V_OD = 800 mV, the corresponding V_OD value setting is 40. The following conditions show that the 1st post tap pre-emphasis setting = 2 is valid:

|B| + |C| ≤ 60→ 40 + 2 = 42
|B| – |C| > 5→ 40 – 2 = 38
(V_MAX/V_MIN – 1)% < 600%→ (42/38 – 1)% = 10.52%

To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Cyclone^® V HSSI HSPICE models.

Table 28. **Transmitter Pre-Emphasis Levels for Cyclone^® V Devices**
Intel^® Quartus^® Prime 1st Post Tap Pre-Emphasis Setting	Intel^® Quartus^® Prime V_OD Setting							Unit
Intel^® Quartus^® Prime 1st Post Tap Pre-Emphasis Setting	10 (200 mV)	20 (400 mV)	30 (600 mV)	35 (700 mV)	40 (800 mV)	45 (900 mV)	50 (1000 mV)	Unit
0	0	0	0	0	0	0	0	dB
1	1.97	0.88	0.43	0.32	0.24	0.19	0.13	dB
2	3.58	1.67	0.95	0.76	0.61	0.5	0.41	dB
3	5.35	2.48	1.49	1.2	1	0.83	0.69	dB
4	7.27	3.31	2	1.63	1.36	1.14	0.96	dB
5	—	4.19	2.55	2.1	1.76	1.49	1.26	dB
6	—	5.08	3.11	2.56	2.17	1.83	1.56	dB
7	—	5.99	3.71	3.06	2.58	2.18	1.87	dB
8	—	6.92	4.22	3.47	2.93	2.48	2.11	dB
9	—	7.92	4.86	4	3.38	2.87	2.46	dB
10	—	9.04	5.46	4.51	3.79	3.23	2.77	dB
11	—	10.2	6.09	5.01	4.23	3.61	—	dB
12	—	11.56	6.74	5.51	4.68	3.97	—	dB
13	—	12.9	7.44	6.1	5.12	4.36	—	dB
14	—	14.44	8.12	6.64	5.57	4.76	—	dB
15	—	—	8.87	7.21	6.06	5.14	—	dB
16	—	—	9.56	7.73	6.49	—	—	dB
17	—	—	10.43	8.39	7.02	—	—	dB
18	—	—	11.23	9.03	7.52	—	—	dB
19	—	—	12.18	9.7	8.02	—	—	dB
20	—	—	13.17	10.34	8.59	—	—	dB
21	—	—	14.2	11.1	—	—	—	dB
22	—	—	15.38	11.87	—	—	—	dB
23	—	—	—	12.67	—	—	—	dB
24	—	—	—	13.48	—	—	—	dB
25	—	—	—	14.37	—	—	—	dB
26	—	—	—	—	—	—	—	dB
27	—	—	—	—	—	—	—	dB
28	—	—	—	—	—	—	—	dB
29	—	—	—	—	—	—	—	dB
30	—	—	—	—	—	—	—	dB
31	—	—	—	—	—	—	—	dB

Transceiver Compliance Specification

The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Cyclone^® V GX, GT, SX, and ST devices. For more information about the protocol parameter details and compliance specifications, contact your Intel Sales Representative.

Table 29. Transceiver Compliance Specification for All Supported Protocol for Cyclone^® V GX, GT, SX, and ST Devices
Protocol	Sub-protocol	Data Rate (Mbps)
PCIe*	PCIe* Gen1	2,500
	PCIe* Gen2⁵⁰	5,000
	PCIe* Cable	2,500
XAUI	XAUI 2135	3,125
Serial RapidIO^® (SRIO)	SRIO 1250 SR	1,250
	SRIO 1250 LR	1,250
	SRIO 2500 SR	2,500
	SRIO 2500 LR	2,500
	SRIO 3125 SR	3,125
	SRIO 3125 LR	3,125
	SRIO 5000 SR	5,000
	SRIO 5000 MR	5,000
	SRIO 5000 LR	5,000
Common Public Radio Interface (CPRI)	CPRI E6LV	614.4
	CPRI E6HV	614.4
	CPRI E6LVII	614.4
	CPRI E12LV	1,228.8
	CPRI E12HV	1,228.8
	CPRI E12LVII	1,228.8
	CPRI E24LV	2,457.6
	CPRI E24LVII	2,457.6
	CPRI E30LV	3,072
	CPRI E30LVII	3,072
	CPRI E48LVII ⁵¹	4,915.2
	CPRI E60LVII⁵¹	6,144
Gbps Ethernet (GbE)	GbE 1250	1,250
OBSAI	OBSAI 768	768
	OBSAI 1536	1,536
	OBSAI 3072	3,072
Serial digital interface (SDI)	SDI 270 SD	270
	SDI 1485 HD	1,485
	SDI 2970 3G	2,970
VbyOne	VbyOne 3750	3,750
HiGig+	HIGIG 3750	3,750

⁵⁰ For PCIe* Gen2 sub-protocol, Intel recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for Cyclone^® V GT and ST FPGA systems which ensure full compliance to the PCIe* Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone^® V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone^® V Devices chapter.

⁵¹ For CPRI E48LVII and E60LVII, Intel recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps ( Cyclone^® V GT and ST devices) and 6.144 Gbps ( Cyclone^® V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone^® V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone^® V Devices chapter.

Core Performance Specifications

Clock Tree Specifications

Table 30. Clock Tree Specifications for Cyclone^® V Devices
Parameter	Performance			Unit
Parameter	–C6	–C7, –I7	–C8, –A7	Unit
Global clock and Regional clock	550	550	460	MHz
Peripheral clock	155	155	155	MHz

PLL Specifications

Table 31. PLL Specifications for Cyclone^® V DevicesThis table lists the Cyclone^® V PLL block specifications. Cyclone^® V PLL block does not include HPS PLL.
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	–C6 speed grade	5	—	670 ⁵²	MHz
		–C7, –I7 speed grades	5	—	622⁵²	MHz
		–C8, –A7 speed grades	5	—	500⁵²	MHz
f_INPFD	Integer input clock frequency to the phase frequency detector (PFD)	—	5	—	325	MHz
f_FINPFD	Fractional input clock frequency to the PFD	—	50	—	160	MHz
f_VCO ⁵³	PLL voltage-controlled oscillator (VCO) operating range	–C6, –C7, –I7 speed grades	600	—	1600	MHz
f_VCO ⁵³	PLL voltage-controlled oscillator (VCO) operating range	–C8, –A7 speed grades	600	—	1300	MHz
t_EINDUTY	Input clock or external feedback clock input duty cycle	—	40	—	60	%
f_OUT	Output frequency for internal global or regional clock	–C6, –C7, –I7 speed grades	—	—	550 ⁵⁴	MHz
f_OUT	Output frequency for internal global or regional clock	–C8, –A7 speed grades	—	—	460⁵⁴	MHz
f_{OUT_EXT}	Output frequency for external clock output	–C6, –C7, –I7 speed grades	—	—	667⁵⁴	MHz
f_{OUT_EXT}	Output frequency for external clock output	–C8, –A7 speed grades	—	—	533⁵⁴	MHz
t_OUTDUTY	Duty cycle for external clock output (when set to 50%)	—	45	50	55	%
t_FCOMP	External feedback clock compensation time	—	—	—	10	ns
t_DYCONFIGCLK	Dynamic configuration clock for `mgmt_clk` and `scanclk`	—	—	—	100	MHz
t_LOCK	Time required to lock from end-of-device configuration or deassertion of `areset`	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
f_CLBW	PLL closed-loop bandwidth	Low	—	0.3	—	MHz
		Medium	—	1.5	—	MHz
		High⁵⁵	—	4	—	MHz
t_{PLL_PSERR}	Accuracy of PLL phase shift	—	—	—	±50	ps
t_ARESET	Minimum pulse width on the `areset` signal	—	10	—	—	ns
t_INCCJ ⁵⁶ ⁵⁷	Input clock cycle-to-cycle jitter	F_REF ≥ 100 MHz	—	—	0.15	UI (p-p)
t_INCCJ ⁵⁶ ⁵⁷	Input clock cycle-to-cycle jitter	F_REF < 100 MHz	—	—	±750	ps (p-p)
t_{OUTPJ_DC} ⁵⁸	Period jitter for dedicated clock output in integer PLL	F_OUT ≥ 100 MHz	—	—	300	ps (p-p)
t_{OUTPJ_DC} ⁵⁸	Period jitter for dedicated clock output in integer PLL	F_OUT < 100 MHz	—	—	30	mUI (p-p)
t_{FOUTPJ_DC} ⁵⁸	Period jitter for dedicated clock output in fractional PLL	F_OUT ≥ 100 MHz	—	—	425⁶¹, 300 ⁵⁹	ps (p-p)
t_{FOUTPJ_DC} ⁵⁸	Period jitter for dedicated clock output in fractional PLL	F_OUT < 100 MHz	—	—	42.5⁶¹, 30⁵⁹	mUI (p-p)
t_{OUTCCJ_DC} ⁵⁸	Cycle-to-cycle jitter for dedicated clock output in integer PLL	F_OUT ≥ 100 MHz	—	—	300	ps (p-p)
t_{OUTCCJ_DC} ⁵⁸		F_OUT < 100 MHz	—	—	30	mUI (p-p)
t_{FOUTCCJ_DC} ⁵⁸	Cycle-to-cycle jitter for dedicated clock output in fractional PLL	F_OUT ≥ 100 MHz	—	—	425⁶¹, 300⁵⁹	ps (p-p)
t_{FOUTCCJ_DC} ⁵⁸		F_OUT < 100 MHz	—	—	42.5⁶¹, 30⁵⁹	mUI (p-p)
t_{OUTPJ_IO} ⁵⁸ ⁶⁰	Period jitter for clock output on a regular I/O in integer PLL	F_OUT ≥ 100 MHz	—	—	650	ps (p-p)
t_{OUTPJ_IO} ⁵⁸ ⁶⁰		F_OUT < 100 MHz	—	—	65	mUI (p-p)
t_{FOUTPJ_IO} ⁵⁸ ⁶⁰ ⁶¹	Period jitter for clock output on a regular I/O in fractional PLL	F_OUT ≥ 100 MHz	—	—	650	ps (p-p)
t_{FOUTPJ_IO} ⁵⁸ ⁶⁰ ⁶¹		F_OUT < 100 MHz	—	—	65	mUI (p-p)
t_{OUTCCJ_IO} ⁵⁸ ⁶⁰	Cycle-to-cycle jitter for clock output on regular I/O in integer PLL	F_OUT ≥ 100 MHz	—	—	650	ps (p-p)
t_{OUTCCJ_IO} ⁵⁸ ⁶⁰		F_OUT < 100 MHz	—	—	65	mUI (p-p)
t_{FOUTCCJ_IO} ⁵⁸ ⁶⁰ ⁶¹	Cycle-to-cycle jitter for clock output on regular I/O in fractional PLL	F_OUT ≥ 100 MHz	—	—	650	ps (p-p)
t_{FOUTCCJ_IO} ⁵⁸ ⁶⁰ ⁶¹		F_OUT < 100 MHz	—	—	65	mUI (p-p)
t_{CASC_OUTPJ_DC} ⁵⁸ ⁶²	Period jitter for dedicated clock output in cascaded PLLs	F_OUT ≥ 100 MHz	—	—	300	ps (p-p)
t_{CASC_OUTPJ_DC} ⁵⁸ ⁶²	Period jitter for dedicated clock output in cascaded PLLs	F_OUT < 100 MHz	—	—	30	mUI (p-p)
t_DRIFT	Frequency drift after `PFDENA` is disabled for a duration of 100 µs	—	—	—	±10	%
dK_BIT	Bit number of Delta Sigma Modulator (DSM)	—	8	24	32	Bits
k_VALUE	Numerator of fraction	—	128	8388608	2147483648	—
f_RES	Resolution of VCO frequency	f_INPFD = 100 MHz	390625	5.96	0.023	Hz

⁵² This specification is limited in the Intel^® Quartus^® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.

⁵³ The VCO frequency reported by the Intel^® Quartus^® Prime software takes into consideration the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the f_VCO specification.

⁵⁴ This specification is limited by the lower of the two: I/O f_MAX or F_OUT of the PLL.

⁵⁵ High bandwidth PLL settings are not supported in external feedback mode.

⁵⁶ A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

⁵⁷ F_REF is f_IN/N, specification applies when N = 1.

⁵⁸ Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Memory Output Clock Jitter Specification for Cyclone^® V Devices table.

⁵⁹ This specification only covers fractional PLL for low bandwidth. The f_VCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.

⁶⁰ External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Cyclone^® V Devices table.

⁶¹ This specification only covers fractional PLL for low bandwidth. The f_VCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.

⁶² The cascaded PLL specification is only applicable with the following conditions:

Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
Downstream PLL: Downstream PLL BW > 2 MHz

DSP Block Performance Specifications

Table 32. DSP Block Performance Specifications for Cyclone^® V Devices
Mode		Performance			Unit
Mode		–C6	–C7, –I7	–C8, –A7	Unit
Modes using One DSP Block	Independent 9 × 9 multiplication	340	300	260	MHz
	Independent 18 × 19 multiplication	287	250	200	MHz
	Independent 18 × 18 multiplication	287	250	200	MHz
	Independent 27 × 27 multiplication	250	200	160	MHz
	Independent 18 × 25 multiplication	310	250	200	MHz
	Independent 20 × 24 multiplication	310	250	200	MHz
	Two 18 × 19 multiplier adder mode	310	250	200	MHz
	18 × 18 multiplier added summed with 36-bit input	310	250	200	MHz
Modes using Two DSP Blocks	Complex 18 × 19 multiplication	310	250	200	MHz

Memory Block Performance Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel^® Quartus^® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX.

Table 33. Memory Block Performance Specifications for Cyclone^® V Devices
Memory	Mode	Resources Used		Performance			Unit
Memory	Mode	ALUTs	Memory	–C6	–C7, –I7	–C8, –A7	Unit
MLAB	Single port, all supported widths	0	1	420	350	300	MHz
	Simple dual-port, all supported widths	0	1	420	350	300	MHz
	Simple dual-port with read and write at the same address	0	1	340	290	240	MHz
	ROM, all supported width	0	1	420	350	300	MHz
M10K Block	Single-port, all supported widths	0	1	315	275	240	MHz
	Simple dual-port, all supported widths	0	1	315	275	240	MHz
	Simple dual-port with the read-during-write option set to Old Data, all supported widths	0	1	275	240	180	MHz
	True dual port, all supported widths	0	1	315	275	240	MHz
	ROM, all supported widths	0	1	315	275	240	MHz

Periphery Performance

This section describes the periphery performance, high-speed I/O, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

Table 34. High-Speed I/O Specifications for Cyclone^® V Devices
When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.

For LVDS applications, you must use the PLLs in integer PLL mode. This is achieved by using the LVDS clock network.

The Cyclone^® V devices support the following output standards using true LVDS output buffer types on all I/O banks.

True RSDS output standard with data rates of up to 360 Mbps

True mini-LVDS output standard with data rates of up to 400 Mbps
Symbol		Condition	–C6			–C7, –I7			–C8, –A7			Unit
Symbol		Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_{HSCLK_in} (input clock frequency) True Differential I/O Standards		Clock boost factor W = 1 to 40 ⁶³	5	—	437.5	5	—	420	5	—	320	MHz
f_{HSCLK_in} (input clock frequency) Single-Ended I/O Standards		Clock boost factor W = 1 to 40⁶³	5	—	320	5	—	320	5	—	275	MHz
f_{HSCLK_OUT} (output clock frequency)		—	5	—	420	5	—	370	5	—	320	MHz
Transmitter	True Differential I/O Standards - f_HSDR (data rate)	SERDES factor J =4 to 10 ⁶⁴	⁶⁵	—	840	⁶⁵	—	740	⁶⁵	—	640	Mbps
	True Differential I/O Standards - f_HSDR (data rate)	SERDES factor J = 1 to 2, uses DDR registers	⁶⁵	—	⁶⁶	⁶⁵	—	⁶⁶	⁶⁵	—	⁶⁶	Mbps
	Emulated Differential I/O Standards with Three External Output Resistor Networks- f_HSDR (data rate) ⁶⁷	SERDES factor J = 4 to 10	⁶⁵	—	640	⁶⁵	—	640	⁶⁵	—	550	Mbps
	Emulated Differential I/O Standards with One External Output Resistor Network - f_HSDR (data rate)	SERDES factor J = 4 to 10	⁶⁵	—	170	⁶⁵	—	170	⁶⁵	—	170	Mbps
	t_{x Jitter} -True Differential I/O Standards⁶⁷	Total Jitter for Data Rate, 600 Mbps – 840 Mbps	—	—	350	—	—	380	—	—	500	ps
	t_{x Jitter} -True Differential I/O Standards⁶⁷	Total Jitter for Data Rate < 600Mbps	—	—	0.21	—	—	0.23	—	—	0.30	UI
	t_{x Jitter} -Emulated Differential I/O Standards with Three External Output Resistor Networks	Total Jitter for Data Rate < 640Mbps	—	—	500	—	—	500	—	—	500	ps
	t_{x Jitter} -Emulated Differential I/O Standards with One External Output Resistor Network	Total Jitter for Data Rate < 640Mbps	—	—	0.15	—	—	0.15	—	—	0.15	UI
	t_DUTY	TX output clock duty cycle for both True and Emulated Differential I/O Standards	45	50	55	45	50	55	45	50	55	%
	t_RISE and t_FALL	True Differential I/O Standards	—	—	200	—	—	200	—	—	200	ps
		Emulated Differential I/O Standards with Three External Output Resistor Networks	—	—	250	—	—	250	—	—	300	ps
		Emulated Differential I/O Standards with One External Output Resistor Network	—	—	300	—	—	300	—	—	300	ps
	TCCS	True Differential I/O Standards	—	—	200	—	—	250	—	—	250	ps
		Emulated Differential I/O Standards with Three External Output Resistor Networks	—	—	300	—	—	300	—	—	300	ps
		Emulated Differential I/O Standards with One External Output Resistor Network	—	—	300	—	—	300	—	—	300	ps
Receiver	f_HSDR (data rate)	SERDES factor J =4 to 10⁶⁴	⁶⁵	—	875⁶⁷	⁶⁵	—	840⁶⁷	⁶⁵	—	640⁶⁷	Mbps
Receiver	f_HSDR (data rate)	SERDES factor J = 1 to 2, uses DDR registers	⁶⁵	—	⁶⁶	⁶⁵	—	⁶⁶	⁶⁵	—	⁶⁶	Mbps
Sampling Window		—	—	—	350	—	—	350	—	—	350	ps

⁶³ Clock boost factor (W) is the ratio between the input data rate and the input clock rate.

⁶⁴ The F_max specification is based on the fast clock used for serial data. The interface F_max is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

⁶⁵ The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.

⁶⁶ The maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (f_out), provided you can close the design timing and the signal integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

⁶⁷ You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

DLL Frequency Range Specifications

Table 35. DLL Frequency Range Specifications for Cyclone^® V Devices
Parameter	–C6	–C7, –I7	–C8	Unit
DLL operating frequency range	167 – 400	167 – 400	167 – 333	MHz

DQS Logic Block Specifications

Table 36. DQS Phase Shift Error Specification for DLL-Delayed Clock (t_{DQS_PSERR}) for Cyclone^® V DevicesThis error specification is the absolute maximum and minimum error.
Number of DQS Delay Buffer	–C6	–C7, –I7	–C8	Unit
2	40	80	80	ps

Memory Output Clock Jitter Specifications

Table 37. Memory Output Clock Jitter Specifications for Cyclone^® V Devices
The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.

The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10^–12, equivalent to 14 sigma.

Intel recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.
Parameter	Clock Network	Symbol	–C6		–C7, –I7		–C8		Unit
Parameter	Clock Network	Symbol	Min	Max	Min	Max	Min	Max	Unit
Clock period jitter	PHYCLK	t_JIT(per)	–60	60	–70	70	–70	70	ps
Cycle-to-cycle period jitter	PHYCLK	t_JIT(cc)	—	90	—	100	—	100	ps

OCT Calibration Block Specifications

Table 38. OCT Calibration Block Specifications for Cyclone^® V Devices
Symbol	Description	Min	Typ	Max	Unit
`OCTUSRCLK`	Clock required by OCT calibration blocks	—	—	20	MHz
T_OCTCAL	Number of `OCTUSRCLK` clock cycles required for R_S OCT/R_T OCT calibration	—	1000	—	Cycles
T_OCTSHIFT	Number of `OCTUSRCLK` clock cycles required for `OCT` code to shift out	—	32	—	Cycles
T_{RS_RT}	Time required between the `dyn_term_ctrl` and `oe` signal transitions in a bidirectional I/O buffer to dynamically switch between R_S OCT and R_T OCT	—	2.5	—	ns

Figure 5. Timing Diagram for oe and dyn_term_ctrl Signals

Duty Cycle Distortion (DCD) Specifications

Table 39. Worst-Case DCD on Cyclone^® V I/O PinsThe output DCD cycle only applies to the I/O buffer. It does not cover the system DCD.
Symbol	–C6		–C7, –I7		–C8, –A7		Unit
Symbol	Min	Max	Min	Max	Min	Max	Unit
Output Duty Cycle	45	55	45	55	45	55	%

HPS Specifications

This section provides HPS specifications and timing for Cyclone^® V devices.

For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.

HPS Clock Performance

Table 40. HPS Clock Performance for Cyclone^® V Devices
Symbol/Description	–C6	–C7, –I7	–A7	–C8	Unit
mpu_base_clk (microprocessor unit clock)	925	800	700	600	MHz
main_base_clk (L3/L4 interconnect clock)	400	400	350	300	MHz
h2f_user0_clk	100	100	100	100	MHz
h2f_user1_clk	100	100	100	100	MHz
h2f_user2_clk	200	200	160	160	MHz

HPS PLL Specifications

HPS PLL VCO Frequency Range

Table 41. HPS PLL VCO Frequency Range for Cyclone^® V Devices
Description	Speed Grade	Minimum	Maximum	Unit
VCO range	–C7, –I7, –A7, –C8	320	1,600	MHz
VCO range	–C6	320	1,850	MHz

HPS PLL Input Clock Range

The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs.

HPS PLL Input Jitter

Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the denominator is 1 to 64.

Maximum input jitter = Input clock period × Divide value (N) × 0.02

Table 42. Examples of Maximum Input Jitter
Input Reference Clock Period	Divide Value (N)	Maximum Jitter	Unit
40 ns	1	0.8	ns
40 ns	2	1.6	ns
40 ns	4	3.2	ns

Quad SPI Flash Timing Characteristics

Table 43. Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone^® V Devices
Symbol	Description	Min	Typ	Max	Unit
F_clk	SCLK_OUT clock frequency (External clock)	—	—	108	MHz
T_{qspi_clk}	QSPI_CLK clock period (Internal reference clock)	2.32	—	—	ns
T_dutycycle	SCLK_OUT duty cycle	45	—	55	%
T_dssfrst	Output delay QSPI_SS valid before first clock edge	—	1/2 cycle of SCLK_OUT	—	ns
T_dsslst	Output delay QSPI_SS valid after last clock edge	–1	—	1	ns
T_dio	I/O data output delay	–1	—	1	ns
T_{din_start}	Input data valid start	—	—	(2 + R_delay) × T_{qspi_clk} – 7.52 ⁶⁸	ns
T_{din_end}	Input data valid end	(2 + R_delay) × T_{qspi_clk} – 1.21 ⁶⁸	—	—	ns

Figure 6. Quad SPI Flash Timing DiagramThis timing diagram illustrates clock polarity mode 0 and clock phase mode 0.

⁶⁸ R_delay is set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Intel provides automatic Quad SPI calibration in the preloader. For more information about R_delay, refer to the Quad SPI Flash Controller chapter in the Cyclone^® V Hard Processor System Technical Reference Manual.

SPI Timing Characteristics

Table 44. SPI Master Timing Requirements for Cyclone^® V DevicesThe setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol	Description	Min	Max	Unit
T_clk	CLK clock period	16.67	—	ns
T_su	SPI Master-in slave-out (MISO) setup time	8.35 ⁶⁹	—	ns
T_h	SPI MISO hold time	1	—	ns
T_dutycycle	SPI_CLK duty cycle	45	55	%
T_dssfrst	Output delay SPI_SS valid before first clock edge	8	—	ns
T_dsslst	Output delay SPI_SS valid after last clock edge	8	—	ns
T_dio	Master-out slave-in (MOSI) output delay	–1	1	ns

Figure 7. SPI Master Timing Diagram

Table 45. SPI Slave Timing Requirements for Cyclone^® V DevicesThe setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol	Description	Min	Max	Unit
T_clk	CLK clock period	20	—	ns
T_s	MOSI Setup time	5	—	ns
T_h	MOSI Hold time	5	—	ns
T_suss	Setup time SPI_SS valid before first clock edge	8	—	ns
T_hss	Hold time SPI_SS valid after last clock edge	8	—	ns
T_d	MISO output delay	—	6	ns

Figure 8. SPI Slave Timing Diagram

⁶⁹ This value is based on rx_sample_dly = 1 and spi_m_clk = 120 MHz. spi_m_clk is the internal clock that is used by SPI Master to derive it’s SCLK_OUT. These timings are based on rx_sample_dly of 1. This delay can be adjusted as needed to accommodate slower response times from the slave. Note that a delay of 0 is not allowed. The setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_sample_dly value because each SPI slave device may have different output delay and each application board may have different path delay. For more information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual.

SD/MMC Timing Characteristics

Table 46. Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone^® V Devices
After power up or cold reset, the Boot ROM uses `drvsel` = 3 and `smplsel` = 0 to execute the code. At the same time, the SD/MMC controller enters the Identification Phase followed by the Data Phase. During this time, the value of interface output clock `SDMMC_CLK_OUT` changes from a maximum of 400 kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock `SDMMC_CLK` and the `CSEL` setting. The value of `SDMMC_CLK` is based on the external oscillator frequency and has a maximum value of 50 MHz.

After the Boot ROM code exits and control is passed to the preloader, software can adjust the value of `drvsel` and `smplsel` via the system manager. `drvsel` can be set from 1 to 7 and `smplsel` can be set from 0 to 7. While the preloader is executing, the values for `SDMMC_CLK` and `SDMMC_CLK_OUT` increase to a maximum of 200 MHz and 50 MHz respectively.
Symbol	Description	Min	Max	Unit
T_{sdmmc_clk} (internal reference clock)	SDMMC_CLK clock period (Identification mode)	20	—	ns
	SDMMC_CLK clock period (Default speed mode)	5	—	ns
	SDMMC_CLK clock period (High speed mode)	5	—	ns
T_{sdmmc_clk_out} (interface output clock)	SDMMC_CLK_OUT clock period (Identification mode)	2500	—	ns
	SDMMC_CLK_OUT clock period (Default speed mode)	40	—	ns
	SDMMC_CLK_OUT clock period (High speed mode)	20	—	ns
T_dutycycle	SDMMC_CLK_OUT duty cycle	45	55	%
T_d	SDMMC_CMD/SDMMC_D output delay	(T_{sdmmc_clk} × `drvsel`)/2 – 1.23 ⁷⁰	(T_{sdmmc_clk} × `drvsel`)/2 + 1.69 ⁷⁰	ns
T_su	Input setup time	1.05 – (T_{sdmmc_clk} × `smplsel`)/2 ⁷¹	—	ns
T_h	Input hold time	(T_{sdmmc_clk} × `smplsel`)/2 ⁷¹	—	ns

Figure 9. SD/MMC Timing Diagram

⁷⁰ drvsel is the drive clock phase shift select value.

⁷¹ smplsel is the sample clock phase shift select value.

USB Timing Characteristics

PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board.

Table 47. USB Timing Requirements for Cyclone^® V Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk	USB CLK clock period	—	16.67	—	ns
T_d	CLK to USB_STP/USB_DATA[7:0] output delay	4.4	—	11	ns
T_su	Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]	2	—	—	ns
T_h	Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]	1	—	—	ns

Figure 10. USB Timing Diagram

Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 48. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Cyclone^® V Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk (1000Base-T)	TX_CLK clock period	—	8	—	ns
T_clk (100Base-T)	TX_CLK clock period	—	40	—	ns
T_clk (10Base-T)	TX_CLK clock period	—	400	—	ns
T_dutycycle	TX_CLK duty cycle	45	—	55	%
T_d	TX_CLK to TXD/TX_CTL output data delay	–0.85	—	0.15	ns

Figure 11. RGMII TX Timing Diagram

Table 49. RGMII RX Timing Requirements for Cyclone^® V Devices
Symbol	Description	Min	Typ	Unit
T_clk (1000Base-T)	RX_CLK clock period	—	8	ns
T_clk (100Base-T)	RX_CLK clock period	—	40	ns
T_clk (10Base-T)	RX_CLK clock period	—	400	ns
T_su	RX_D/RX_CTL setup time	1	—	ns
T_h	RX_D/RX_CTL hold time	1	—	ns

Figure 12. RGMII RX Timing Diagram

Table 50. Management Data Input/Output (MDIO) Timing Requirements for Cyclone^® V Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk	MDC clock period	—	400	—	ns
T_d	MDC to MDIO output data delay	10	—	20	ns
T_s	Setup time for MDIO data	10	—	—	ns
T_h	Hold time for MDIO data	0	—	—	ns

Figure 13. MDIO Timing Diagram

I2C Timing Characteristics

Table 51. I²C Timing Requirements for Cyclone^® V Devices
Symbol	Description	Standard Mode		Fast Mode		Unit
Symbol	Description	Min	Max	Min	Max	Unit
T_clk	Serial clock (SCL) clock period	10	—	2.5	—	µs
T_clkhigh	SCL high time	4.7	—	0.6	—	µs
T_clklow	SCL low time	4	—	1.3	—	µs
T_s	Setup time for serial data line (SDA) data to SCL	0.25	—	0.1	—	µs
T_h	Hold time for SCL to SDA data	0	3.45	0	0.9	µs
T_d	SCL to SDA output data delay	—	0.2	—	0.2	µs
T_{su_start}	Setup time for a repeated start condition	4.7	—	0.6	—	µs
T_{hd_start}	Hold time for a repeated start condition	4	—	0.6	—	µs
T_{su_stop}	Setup time for a stop condition	4	—	0.6	—	µs

Figure 14. I²C Timing Diagram

NAND Timing Characteristics

Table 52. NAND ONFI 1.0 Timing Requirements for Cyclone^® V DevicesThe NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. This table lists the requirements for ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by programming the `C4` output of the main HPS PLL and timing registers provided in the NAND controller.
Symbol	Description	Min	Max	Unit
T_wp ⁷²	Write enable pulse width	10	—	ns
T_wh ⁷²	Write enable hold time	7	—	ns
T_rp ⁷²	Read enable pulse width	10	—	ns
T_reh ⁷²	Read enable hold time	7	—	ns
T_clesu ⁷²	Command latch enable to write enable setup time	10	—	ns
T_cleh ⁷²	Command latch enable to write enable hold time	5	—	ns
T_cesu ⁷²	Chip enable to write enable setup time	15	—	ns
T_ceh ⁷²	Chip enable to write enable hold time	5	—	ns
T_alesu ⁷²	Address latch enable to write enable setup time	10	—	ns
T_aleh ⁷²	Address latch enable to write enable hold time	5	—	ns
T_dsu ⁷²	Data to write enable setup time	10	—	ns
T_dh ⁷²	Data to write enable hold time	5	—	ns
T_cea	Chip enable to data access time	—	25	ns
T_rea	Read enable to data access time	—	16	ns
T_rhz	Read enable to data high impedance	—	100	ns
T_rr	Ready to read enable low	20	—	ns

Figure 15. NAND Command Latch Timing Diagram

Figure 16. NAND Address Latch Timing Diagram

Figure 17. NAND Data Write Timing Diagram

Figure 18. NAND Data Read Timing Diagram

⁷² Timing of the NAND interface is controlled through the NAND configuration registers.

Arm Trace Timing Characteristics

Table 53. Arm* Trace Timing Requirements for Cyclone^® V DevicesMost debugging tools have a mechanism to adjust the capture point of trace data.
Description	Min	Max	Unit
CLK clock period	12.5	—	ns
CLK maximum duty cycle	45	55	%
CLK to D0 –D7 output data delay	–1	1	ns

UART Interface

The maximum UART baud rate is 6.25 megasymbols per second.

GPIO Interface

The minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. The pulse width is based on a debounce clock frequency of 1 MHz.

CAN Interface

The maximum controller area network (CAN) data rate is 1 Mbps.

HPS JTAG Timing Specifications

Table 54. HPS JTAG Timing Parameters and Values for Cyclone^® V Devices
Symbol	Description	Min	Max	Unit
t_JCP	TCK clock period	30	—	ns
t_JCH	TCK clock high time	14	—	ns
t_JCL	TCK clock low time	14	—	ns
t_{JPSU (TDI)}	TDI JTAG port setup time	2	—	ns
t_{JPSU (TMS)}	TMS JTAG port setup time	3	—	ns
t_JPH	JTAG port hold time	5	—	ns
t_JPCO	JTAG port clock to output	—	12 ⁷³	ns
t_JPZX	JTAG port high impedance to valid output	—	14⁷³	ns
t_JPXZ	JTAG port valid output to high impedance	—	14⁷³	ns

⁷³ A 1-ns adder is required for each V_{CCIO
_HPS} voltage step down from 3.0 V. For example, t_JPCO= 13 ns if V_{CCIO _HPS} of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V.

Configuration Specifications

This section provides configuration specifications and timing for Cyclone^® V devices.

POR Specifications

Table 55. Fast and Standard POR Delay Specification for Cyclone^® V Devices
POR Delay	Minimum	Maximum	Unit
Fast	4	12⁷⁴	ms
Standard	100	300	ms

⁷⁴ The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe* hard IP to initialize after the POR trip.

FPGA JTAG Configuration Timing

Table 56. FPGA JTAG Timing Parameters and Values for Cyclone^® V Devices
Symbol	Description	Min	Max	Unit
t_JCP	TCK clock period	30, 167⁷⁵	—	ns
t_JCH	TCK clock high time	14	—	ns
t_JCL	TCK clock low time	14	—	ns
t_{JPSU (TDI)}	TDI JTAG port setup time	1	—	ns
t_{JPSU (TMS)}	TMS JTAG port setup time	3	—	ns
t_JPH	JTAG port hold time	5	—	ns
t_JPCO	JTAG port clock to output	—	11 ⁷⁶	ns
t_JPZX	JTAG port high impedance to valid output	—	14⁷⁶	ns
t_JPXZ	JTAG port valid output to high impedance	—	14⁷⁶	ns

⁷⁵ The minimum TCK clock period is 167 ns if V_CCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.

⁷⁶ A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V.

FPP Configuration Timing

DCLK-to-DATA[] Ratio (r) for FPP Configuration

Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.

Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.

Cyclone^® V devices use additional clock cycles to decrypt and decompress the configuration data. If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into the Cyclone^® V device.

Table 57. DCLK-to-DATA[] Ratio for Cyclone^® V DevicesThe specifications in this table are not applicable to Cyclone^® V QS package.
Configuration Scheme	Encryption	Compression	DCLK-to-DATA[] Ratio (r)
FPP (8-bit wide)	Off	Off	1
	On	Off	1
	Off	On	2
	On	On	2
FPP (16-bit wide)	Off	Off	1
	On	Off	2
	Off	On	4
	On	On	4

FPP Configuration Timing when DCLK-to-DATA[] = 1

When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Cyclone^® V Devices table.

Table 58. FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone^® V DevicesThe specifications in this table are not applicable to Cyclone^® V QS package.
Symbol	Parameter	Minimum	Maximum	Unit
t_CF2CD	`nCONFIG` low to `CONF_DONE` low	—	600	ns
t_CF2ST0	`nCONFIG` low to `nSTATUS` low	—	600	ns
t_CFG	`nCONFIG` low pulse width	2	—	µs
t_STATUS	`nSTATUS` low pulse width	268	1506⁷⁷	µs
t_CF2ST1	`nCONFIG` high to `nSTATUS` high	—	1506⁷⁸	µs
t_CF2CK ⁷⁹	`nCONFIG` high to first rising edge on `DCLK`	1506	—	µs
t_ST2CK ⁷⁹	`nSTATUS` high to first rising edge of `DCLK`	2	—	µs
t_DSU	`DATA[]` setup time before rising edge on `DCLK`	5.5	—	ns
t_DH	`DATA[]` hold time after rising edge on `DCLK`	0	—	ns
t_CH	`DCLK` high time	0.45 × 1/f_MAX	—	s
t_CL	`DCLK` low time	0.45 × 1/f_MAX	—	s
t_CLK	`DCLK` period	1/f_MAX	—	s
f_MAX	`DCLK` frequency (FPP ×8/ ×16)	—	125	MHz
t_CD2UM	`CONF_DONE` high to user mode⁸⁰	175	437	µs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	4× maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	t_CD2CU + (T_init × `CLKUSR` period)	—	—
T_init	Number of clock cycles required for device initialization	8,576	—	Cycles

⁷⁷ You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width.

⁷⁸ You can obtain this value if you do not delay configuration by externally holding the nSTATUS low.

⁷⁹ If nSTATUS is monitored, follow the t_ST2CK specification. If nSTATUS is not monitored, follow the t_CF2CK specification.

⁸⁰ The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

FPP Configuration Timing when DCLK-to-DATA[] >1

Table 59. FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone^® V Devices
The specifications in this table are not applicable to Cyclone^® V QS package.

Use these timing parameters when you use the decompression and design security features.
Symbol	Parameter	Minimum	Maximum	Unit
t_CF2CD	`nCONFIG` low to `CONF_DONE` low	—	600	ns
t_CF2ST0	`nCONFIG` low to `nSTATUS` low	—	600	ns
t_CFG	`nCONFIG` low pulse width	2	—	µs
t_STATUS	`nSTATUS` low pulse width	268	1506⁸¹	µs
t_CF2ST1	`nCONFIG` high to `nSTATUS` high	—	1506⁸²	µs
t_CF2CK ⁸³	`nCONFIG` high to first rising edge on `DCLK`	1506	—	µs
t_ST2CK ⁸³	`nSTATUS` high to first rising edge of `DCLK`	2	—	µs
t_DSU	`DATA[]` setup time before rising edge on `DCLK`	5.5	—	ns
t_DH	`DATA[]` hold time after rising edge on `DCLK`	`N` – 1/f_DCLK ⁸⁴	—	s
t_CH	`DCLK` high time	0.45 × 1/f_MAX	—	s
t_CL	`DCLK` low time	0.45 × 1/f_MAX	—	s
t_CLK	`DCLK` period	1/f_MAX	—	s
f_MAX	`DCLK` frequency (FPP ×8/ ×16)	—	125	MHz
t_R	Input rise time	—	40	ns
t_F	Input fall time	—	40	ns
t_CD2UM	`CONF_DONE` high to user mode⁸⁵	175	437	µs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	t_CD2CU + (T_init × `CLKUSR` period)	—	—
T_init	Number of clock cycles required for device initialization	8,576	—	Cycles

⁸¹ This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

⁸² This value can be obtained if you do not delay configuration by externally holding nSTATUS low.

⁸³ If nSTATUS is monitored, follow the t_ST2CK specification. If nSTATUS is not monitored, follow the t_CF2CK specification.

⁸⁴ N is the DCLK-to-DATA[] ratio and f_DCLK is the DCLK frequency of the system.

⁸⁵ The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

Active Serial (AS) Configuration Timing

Table 60. AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone^® V Devices (For Non Cyclone^® V QS Packages)
The minimum and maximum numbers apply to both the internal oscillator and `CLKUSR` when either one is used as the clock source for device configuration.

The t_CF2CD, t_CF2ST0, t_CFG, t_STATUS, and t_CF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Cyclone^® V Devices table. You can obtain the t_CF2ST1 value if you do not delay configuration by externally holding `nSTATUS` low.
Symbol	Parameter	Condition	Minimum	Maximum	Unit
t_CO ⁸⁶	`DCLK` falling edge to the `AS_DATA[3:0]`/`ASDO` output	—	—	2	ns
t_SU ⁸⁷	Data setup time before the falling edge on `DCLK`	—	1.5	—	ns
t_DH ⁸⁷	Data hold time after the falling edge on `DCLK`	–6 speed grade	2.3 ⁸⁸	—	ns
t_DH ⁸⁷	Data hold time after the falling edge on `DCLK`	–7 or –8 speed grades	2.9⁸⁹/2.7⁸⁸	—	ns
t_CD2UM	`CONF_DONE` high to user mode	—	175	437	µs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	—	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	—	t_CD2CU + (T_init × `CLKUSR` period)	—	—
T_init	Number of clock cycles required for device initialization	—	8,576	—	Cycles

Table 61. AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone^® V Devices (For Cyclone^® V QS Package)
The minimum and maximum numbers apply to both the internal oscillator and `CLKUSR` when either one is used as the clock source for device configuration.

The t_CF2CD, t_CF2ST0, t_CFG, t_STATUS, and t_CF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Cyclone^® V Devices table. You can obtain the t_CF2ST1 value if you do not delay configuration by externally holding `nSTATUS` low.
Symbol	Parameter	Condition	Minimum	Maximum	Unit
t_CO	`DCLK` falling edge to the `AS_DATA[3:0]`/`ASDO` output	—	–1.3	0	ns
t_SU	Data setup time before the falling edge on `DCLK`	—	2.9	—	ns
t_DH	Data hold time after the falling edge on `DCLK`	–6 speed grade	0.5⁸⁸	—	ns
t_DH	Data hold time after the falling edge on `DCLK`	–7 or –8 speed grades	1.3⁹⁰/1.1⁸⁸	—	ns
t_CD2UM	`CONF_DONE` high to user mode	—	175	437	µs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	—	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	—	t_CD2CU + (T_init × `CLKUSR` period)	—	—
T_init	Number of clock cycles required for device initialization	—	8,576	—	Cycles

⁸⁶ Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the t_CO for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation.

⁸⁷ To evaluate the data setup (t_SU) and data hold time (t_DH) slack on your board in order to ensure you are meeting the t_SU and t_DH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline.

⁸⁸ Specification for the commercial grade devices.

⁸⁹ Specification for the industrial and automotive grade devices.

⁹⁰ Specification for the industrial grade devices.

DCLK Frequency Specification in the AS Configuration Scheme

Table 62. DCLK Frequency Specification in the AS Configuration Scheme
The specifications in this table are applicable to both Cyclone^® V QS and non QS packages.

This table lists the internal clock frequency specification for the AS configuration scheme. The `DCLK` frequency specification applies when you use the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support `DCLK` frequency of 100 MHz.
Parameter	Minimum	Typical	Maximum	Unit
`DCLK` frequency in AS configuration scheme	5.3	7.9	12.5	MHz
	10.6	15.7	25.0	MHz
	21.3	31.4	50.0	MHz
	42.6	62.9	100.0	MHz

Passive Serial (PS) Configuration Timing

Table 63. PS Timing Parameters for Cyclone^® V DevicesThe specifications in this table are not applicable to Cyclone^® V QS package.
Symbol	Parameter	Minimum	Maximum	Unit
t_CF2CD	`nCONFIG` low to `CONF_DONE` low	—	600	ns
t_CF2ST0	`nCONFIG` low to `nSTATUS` low	—	600	ns
t_CFG	`nCONFIG` low pulse width	2	—	µs
t_STATUS	`nSTATUS` low pulse width	268	1506⁹¹	µs
t_CF2ST1	`nCONFIG` high to `nSTATUS` high	—	1506⁹²	µs
t_CF2CK ⁹³	`nCONFIG` high to first rising edge on `DCLK`	1506	—	µs
t_ST2CK ⁹³	`nSTATUS` high to first rising edge of `DCLK`	2	—	µs
t_DSU	`DATA[]` setup time before rising edge on `DCLK`	5.5	—	ns
t_DH	`DATA[]` hold time after rising edge on `DCLK`	0	—	ns
t_CH	`DCLK` high time	0.45 × 1/f_MAX	—	s
t_CL	`DCLK` low time	0.45 × 1/f_MAX	—	s
t_CLK	`DCLK` period	1/f_MAX	—	s
f_MAX	`DCLK` frequency	—	125	MHz
t_CD2UM	`CONF_DONE` high to user mode⁹⁴	175	437	µs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	t_CD2CU + (T_init × `CLKUSR` period)	—	—
T_init	Number of clock cycles required for device initialization	8,576	—	Cycles

⁹¹ You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

⁹² You can obtain this value if you do not delay configuration by externally holding nSTATUS low.

⁹³ If nSTATUS is monitored, follow the t_ST2CK specification. If nSTATUS is not monitored, follow the t_CF2CK specification.

⁹⁴ The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

Initialization

Table 64. Initialization Clock Source Option and the Maximum Frequency for Cyclone^® V Devices
Initialization Clock Source	Configuration Scheme	Maximum Frequency (MHz)	Minimum Number of Clock Cycles
Internal Oscillator	AS, PS, and FPP	12.5	T_init
`CLKUSR` ⁹⁵	PS and FPP	125
`CLKUSR` ⁹⁵	AS	100
`DCLK`	PS and FPP	125

⁹⁵ To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Intel^® Quartus^® Prime software from the General panel of the Device and Pin Options dialog box.

Configuration Files

Table 65. Uncompressed .rbf Sizes for Cyclone^® V Devices
Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes.

For the different types of configuration file and file sizes, refer to the Intel^® Quartus^® Prime software. However, for a specific version of the Intel^® Quartus^® Prime software, any design targeted for the same device has the same uncompressed configuration file size.

The IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature.
Variant	Member Code	Configuration .rbf Size (bits)	IOCSR .rbf Size (bits)	Recommended EPCQ Serial Configuration Device⁹⁶
Cyclone^® V E ⁹⁷	A2	21,061,280	275,608	EPCQ64
	A4	21,061,280	275,608	EPCQ64
	A5	33,958,560	322,072	EPCQ128
	A7	56,167,552	435,288	EPCQ128
	A9	102,871,776	400,408	EPCQ256
Cyclone^® V GX	C3	14,510,912	320,280	EPCQ32
	C4	33,958,560	322,072	EPCQ128
	C5	33,958,560	322,072	EPCQ128
	C7	56,167,552	435,288	EPCQ128
	C9	102,871,776	400,408	EPCQ256
Cyclone^® V GT	D5	33,958,560	322,072	EPCQ128
	D7	56,167,552	435,288	EPCQ128
	D9	102,871,776	400,408	EPCQ256
Cyclone^® V SE ⁹⁷	A2	33,958,560	322,072	EPCQ128
	A4	33,958,560	322,072	EPCQ128
	A5	56,057,632	324,888	EPCQ128
	A6	56,057,632	324,888	EPCQ128
Cyclone^® V SX	C2	33,958,560	322,072	EPCQ128
	C4	33,958,560	322,072	EPCQ128
	C5	56,057,632	324,888	EPCQ128
	C6	56,057,632	324,888	EPCQ128
Cyclone^® V ST	D5	56,057,632	324,888	EPCQ128
Cyclone^® V ST	D6	56,057,632	324,888	EPCQ128

⁹⁶ The recommended EPCQ serial configuration devices are able to store more than one image.

⁹⁷ No PCIe* hard IP, configuration via protocol (CvP) is not supported in this family.

Minimum Configuration Time Estimation

Table 66. Minimum Configuration Time Estimation for Cyclone^® V DevicesThe estimated values are based on the configuration .rbf sizes in Uncompressed .rbf Sizes for Cyclone^® V Devices table.
Variant	Member Code	Active Serial⁹⁸			Fast Passive Parallel⁹⁹
Variant	Member Code	Width	DCLK (MHz)	Minimum Configuration Time (ms)	Width	DCLK (MHz)	Minimum Configuration Time (ms)
Cyclone^® V E	A2	4	100	53	16	125	11
	A4	4	100	53	16	125	11
	A5	4	100	85	16	125	17
	A7	4	100	140	16	125	28
	A9	4	100	257	16	125	51
Cyclone^® V GX	C3	4	100	36	16	125	7
	C4	4	100	85	16	125	17
	C5	4	100	85	16	125	17
	C7	4	100	140	16	125	28
	C9	4	100	257	16	125	51
Cyclone^® V GT	D5	4	100	85	16	125	17
	D7	4	100	140	16	125	28
	D9	4	100	257	16	125	51
Cyclone^® V SE	A2	4	100	85	16	125	17
	A4	4	100	85	16	125	17
	A5	4	100	140	16	125	28
	A6	4	100	140	16	125	28
Cyclone^® V SX	C2	4	100	85	16	125	17
	C4	4	100	85	16	125	17
	C5	4	100	140	16	125	28
	C6	4	100	140	16	125	28
Cyclone^® V ST	D5	4	100	140	16	125	28
Cyclone^® V ST	D6	4	100	140	16	125	28

⁹⁸ DCLK frequency of 100 MHz using external CLKUSR.

⁹⁹ Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.

Remote System Upgrades

Table 67. Remote System Upgrade Circuitry Timing Specifications for Cyclone^® V Devices
Parameter	Minimum	Unit
t_{RU_nCONFIG} ¹⁰⁰	250	ns
t_{RU_nRSTIMER} ¹⁰¹	250	ns

¹⁰⁰ This is equivalent to strobing the reconfiguration input of the Remote Update Intel FPGA IP core high for the minimum timing specification.

¹⁰¹ This is equivalent to strobing the reset timer input of the Remote Update Intel FPGA IP core high for the minimum timing specification.

User Watchdog Internal Oscillator Frequency Specifications

Table 68. User Watchdog Internal Oscillator Frequency Specifications for Cyclone^® V Devices
Parameter	Minimum	Typical	Maximum	Unit
User watchdog internal oscillator frequency	5.3	7.9	12.5	MHz

I/O Timing

Intel offers two ways to determine I/O timing—the Excel-based I/O timing and the Intel^® Quartus^® Prime Timing Analyzer.

Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis.

The Intel^® Quartus^® Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route.

Programmable IOE Delay

Table 69. I/O element (IOE) Programmable Delay for Cyclone^® V Devices
Parameter¹⁰²	Available Settings	Minimum Offset¹⁰³	Fast Model		Slow Model					Unit
Parameter¹⁰²	Available Settings	Minimum Offset¹⁰³	Industrial	Commercial	–C6	–C7	–C8	–I7	–A7	Unit
D1	32	0	0.508	0.517	0.971	1.187	1.194	1.179	1.160	ns
D3	8	0	1.761	1.793	3.291	4.022	3.961	3.999	3.929	ns
D4	32	0	0.510	0.519	1.180	1.187	1.195	1.180	1.160	ns
D5	32	0	0.508	0.517	0.970	1.186	1.194	1.179	1.179	ns

¹⁰² You can set this value in the Intel^® Quartus^® Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.

¹⁰³ Minimum offset does not include the intrinsic delay.

Programmable Output Buffer Delay

Table 70. Programmable Output Buffer Delay for Cyclone^® V Devices
This table lists the delay chain settings that control the rising and falling edge delays of the output buffer.

You can set the programmable output buffer delay in the Intel^® Quartus^® Prime software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment.
Symbol	Parameter	Typical	Unit
D_OUTBUF	Rising and/or falling edge delay	0 (default)	ps
		50	ps
		100	ps
		150	ps

Glossary

Table 71. Glossary
Term	Definition
Differential I/O standards	Receiver Input Waveforms Transmitter Output Waveforms
f_HSCLK	Left/right PLL input clock frequency.
f_HSDR	High-speed I/O block—Maximum/minimum LVDS data transfer rate (f_HSDR =1/TUI).
J	High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG timing specifications	JTAG Timing Specifications
PLL specifications	Diagram of PLL specifications
R_L	Receiver differential input discrete resistor (external to the Cyclone^® V device).
Sampling window (SW)	Timing diagram—The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown:
Single-ended voltage referenced I/O standard	The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard
t_C	High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew)	The timing difference between the fastest and slowest output edges, including the t_CO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
t_DUTY	High-speed I/O block—Duty cycle on high-speed transmitter output clock.
t_FALL	Signal high-to-low transition time (80–20%)
t_INCCJ	Cycle-to-cycle jitter tolerance on the PLL clock input
t_{OUTPJ_IO}	Period jitter on the GPIO driven by a PLL
t_{OUTPJ_DC}	Period jitter on the dedicated clock output driven by a PLL
t_RISE	Signal low-to-high transition time (20–80%)
Timing Unit Interval (TUI)	The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)
V_CM(DC)	DC common mode input voltage.
V_ICM	Input common mode voltage—The common mode of the differential signal at the receiver.
V_ID	Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver.
V_DIF(AC)	AC differential input voltage—Minimum AC input differential voltage required for switching.
V_DIF(DC)	DC differential input voltage— Minimum DC input differential voltage required for switching.
V_IH	Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high.
V_IH(AC)	High-level AC input voltage
V_IH(DC)	High-level DC input voltage
V_IL	Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low.
V_IL(AC)	Low-level AC input voltage
V_IL(DC)	Low-level DC input voltage
V_OCM	Output common mode voltage—The common mode of the differential signal at the transmitter.
V_OD	Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter.
V_SWING	Differential input voltage
V_X	Input differential cross point voltage
V_OX	Output differential cross point voltage
W	High-speed I/O block—Clock boost factor

Document Revision History for Cyclone V Device Datasheet

Document Version	Changes
2019.11.27	Updated t_CO parameter in the AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone^® V Devices (For Non Cyclone^® V QS Packages) table. Added active serial (AS) configuration timing for Cyclone^® V QS package. Added a note to indicate that the specifications are not applicable to Cyclone^® V QS package in the following tables: DCLK-to-DATA[] Ratio for Cyclone^® V Devices FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone^® V Devices FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone^® V Devices PS Timing Parameters for Cyclone^® V Devices Added a note to indicate that the specifications are applicable to both Cyclone^® V QS and non QS packages in the DCLK Frequency Specification in the AS Configuration Scheme table.
2019.01.25	Changed "VCO post-scale counter `K` value" to "VCO post divider value" in the f_VCO note in the PLL Specifications for Cyclone^® V Devices table. Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone^® V Devices table. Updated t_DH specifications. These specifications are applicable to the commercial, industrial, and automotive grade devices. Added note to t_CO and t_SU.
2018.05.07	Added description about the low-power option ("L" suffix) for Cyclone^® V SE and SX devices. Added the Cyclone^® V Devices Overshoot Duration diagram. Removed the description on SD/MMC interface calibration support in the Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone^® V Devices table. This feature is currently supported in the preloader. Removed the note to Cyclone^® V SE A2 and A4 devices, and Cyclone^® V SX C2 and C4 devices in the Uncompressed .rbf Sizes for Cyclone^® V Devices table. These devices are currently supported in the Intel^® Quartus^® Prime software. Removed PowerPlay text from tool name. Updated the IP name from ALTREMOTE_UPDATE to Remote Update Intel FPGA IP. Rebranded as Intel. Added the Low Power Variants table and the estimating power consumption steps to the " Cyclone^® V Device Datasheet" Overview section. Updated the minimum value for t_DH to 2.5 for -6 speed grade/2.9 for -7 and -8 speed grade.

Date	Version	Changes
December 2016	2016.12.09	Updated V_ICM (AC coupled) specifications for 1.5 V PCML in Receiver Specifications for Cyclone^® V GX, GT, SX, and ST Devices table. Added maximum specification for T_d in Management Data Input/Output (MDIO) Timing Requirements for Cyclone^® V Devices table. Updated T_init specifications in the following tables: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone^® V Devices FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone^® V Devices AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone^® V Devices PS Timing Parameters for Cyclone^® V Devices
June 2016	2016.06.10	Changed pin capacitance to maximum values. Updated SPI Master Timing Requirements for Cyclone^® V Devices table. Added T_su and T_h specifications. Removed T_dinmax specifications. Updated SPI Master Timing Diagram. Updated T_clk spec from maximum to minimum in I²C Timing Requirements for Cyclone^® V Devices table.
December 2015	2015.12.04	Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone^® V Devices table. Updated F_clk, T_dutycycle, and T_dssfrst specifications. Added T_{qspi_clk}, T_{din_start}, and T_{din_end} specifications. Removed T_dinmax specifications. Updated the minimum specification for T_clk to 16.67 ns and removed the maximum specification in SPI Master Timing Requirements for Cyclone^® V Devices table. Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone^® V Devices table. Updated T _clk to T_{sdmmc_clk_out} symbol. Updated T_{sdmmc_clk_out} and T_d specifications. Added T_{sdmmc_clk}, T_su, and T_h specifications. Removed T_dinmax specifications. Updated the following diagrams: Quad SPI Flash Timing Diagram SD/MMC Timing Diagram Updated configuration .rbf sizes for Cyclone^® V devices. Changed instances of Quartus II to Quartus Prime.
June 2015	2015.06.12	Updated the supported data rates for the following output standards using true LVDS output buffer types in the High-Speed I/O Specifications for Cyclone^® V Devices table: True RSDS output standard: data rates of up to 360 Mbps True mini-LVDS output standard: data rates of up to 400 Mbps Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash. Updated T_h location in I²C Timing Diagram. Updated T_wp location in NAND Address Latch Timing Diagram. Updated the maximum value for t_CO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone^® V Devices table. Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Cyclone^® V Devices chapter. FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1 FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1 AS Configuration Timing Waveform PS Configuration Timing Waveform
March 2015	2015.03.31	Added V_CC specifications for devices with internal scrubbing feature (with SC suffix) in Recommended Operating Conditions table. Corrected the unit for t_DH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone^® V Devices table.
January 2015	2015.01.23	Updated the transceiver specification for Cyclone^® V ST from 5 Gbps to 6.144 Gbps. Updated the note in the following tables: Transceiver Power Supply Operating Conditions for Cyclone^® V GX, GT, SX, and ST Devices Transceiver Specifications for Cyclone^® V GX, GT, SX, and ST Devices Transceiver Compliance Specification for All Supported Protocol for Cyclone^® V Devices Updated the description for V_{CC_AUX_SHARED} to “HPS auxiliary power supply”. Added a note to state that V_{CC_AUX_SHARED} must be powered by the same source as VCC_AUX for Cyclone^® V SX C5, C6, D5, and D6 devices, and Cyclone^® V SE A5 and A6 devices. Updated in the following tables: Absolute Maximum Ratings for Cyclone^® V Devices HPS Power Supply Operating Conditions for Cyclone^® V SE, SX, and ST Devices Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of differential signal. Added a note to the conditions: `REFCLK` performance requires to meet transmitter `REFCLK` phase noise specification. Updated f_VCO maximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL specifications table. Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design. Added the following notes in the High-Speed I/O Specifications for Cyclone^® V Devices table: The Cyclone^® V devices support true RSDS output standard with data rates of up to 230 Mbps using true LVDS output buffer types on all I/O banks. The Cyclone^® V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using true LVDS output buffer types on all I/O banks. Updated HPS Clock Performance main_base_clk specifications from 462 MHz to 400 MHz for –C6 speed grade. Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and 1,850 MHz (for –C6 speed grade). Changed the symbol for HPS PLL input jitter divide value from NR to N. Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables: SPI Master Timing Requirements for Cyclone^® V Devices SPI Slave Timing Requirements for Cyclone