Intel Arria 10 Device Datasheet

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A10-DATASHEET | 2018.06.15

Intel Arria 10 Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Intel^® Arria^® 10 devices.

Intel^® Arria^® 10 devices are offered in extended, industrial, and automotive grades. Extended devices are offered in –E1 (fastest), –E2, and –E3 speed grades. Industrial grade devices are offered in the –I1, –I2, and –I3 speed grades. Automotive devices are offered in the –A3 speed grade and transceiver speed grade 4.

Note: The specifications for the automotive devices are preliminary, pending characterization.

The suffix after the speed grade denotes the power options offered in Intel^® Arria^® 10 devices.

L—Low static power
S—Standard power
V—Supported with the SmartVID feature (lowest static power)
H—High performance power

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Intel^® Arria^® 10 devices.

Operating Conditions

Intel^® Arria^® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel^® Arria^® 10 devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions for Intel^® Arria^® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

CAUTION:

Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 1. Absolute Maximum Ratings for Intel^® Arria^® 10 Devices
Symbol	Description	Condition	Minimum	Maximum	Unit
V_CC	Core voltage power supply	—	–0.50	1.21	V
V_CCP	Periphery circuitry and transceiver fabric interface power supply	—	–0.50	1.21	V
V_CCERAM	Embedded memory power supply	—	–0.50	1.36	V
V_CCPT	Power supply for programmable power technology and I/O pre-driver	—	–0.50	2.46	V
V_CCBAT	Battery back-up power supply for design security volatile key register	—	–0.50	2.46	V
V_CCPGM	Configuration pins power supply	¹	–0.50	2.46	V
V_CCIO	I/O buffers power supply	3 V I/O	–0.50	4.10	V
V_CCIO	I/O buffers power supply	LVDS I/O	–0.50	2.46	V
V_{CCA_PLL}	Phase-locked loop (PLL) analog power supply	—	–0.50	2.46	V
V_{CCT_GXB}	Transmitter power supply	—	–0.50	1.34	V
V_{CCR_GXB}	Receiver power supply	—	–0.50	1.34	V
V_{CCH_GXB}	Transceiver output buffer power supply	—	–0.50	2.46	V
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	—	–0.50	1.27	V
V_{CCIO_HPS}	HPS I/O buffers power supply	3 V I/O	–0.50	4.10	V
V_{CCIO_HPS}	HPS I/O buffers power supply	LVDS I/O	–0.50	2.46	V
V_{CCIOREF_HPS}	HPS I/O pre-driver power supply	—	–0.50	2.46	V
V_{CCPLL_HPS}	HPS PLL power supply	—	–0.50	2.46	V
I_OUT	DC output current per pin	—	–25 ² ³ ⁴ ⁵ ⁶	25	mA
T_J	Operating junction temperature	—	–55	125	°C
T_STG	Storage temperature (no bias)	—	–65	150	°C

¹ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

² The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA.

³ Total current per LVDS I/O bank must not exceed 100 mA.

⁴ Voltage level must not exceed 1.89 V.

⁵ Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os.

⁶ Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel^® Cyclone^® 10 GX, Intel^® Arria^® 10, and Intel^® Stratix^® 10 Devices and Power Management in Intel^® Arria^® 10 Devices chapter.

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.

The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.

Table 2. Maximum Allowed Overshoot During Transitions for Intel^® Arria^® 10 Devices. This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O values are applicable to the `VREFP_ADC` and `VREFN_ADC` I/O pins.
Symbol	Description	Condition (V)		Overshoot Duration as % at T_J = 100°C	Unit
Symbol	Description	LVDS I/O ⁷	3 V I/O	Overshoot Duration as % at T_J = 100°C	Unit
Vi (AC)	AC input voltage	2.50	3.80	100	%
		2.55	3.85	42	%
		2.60	3.90	18	%
		2.65	3.95	9	%
		2.70	4.00	4	%
		> 2.70	> 4.00	No overshoot allowed	%

For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal.

Figure 1. Intel^® Arria^® 10 Devices Overshoot Duration

⁷ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for Intel^® Arria^® 10 devices.

Recommended Operating Conditions

Table 3. Recommended Operating Conditions for Intel^® Arria^® 10 Devices. This table lists the steady-state voltage values expected from Intel^® Arria^® 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol	Description	Condition	Minimum ⁸	Typical	Maximum ⁸	Unit
V_CC	Core voltage power supply	Standard and low power ⁹	0.87	0.9	0.93	V
		Standard and low power ⁹	0.92	0.95	0.98	V
		SmartVID ¹⁰	0.82	—	0.93	V
V_CCP	Periphery circuitry and transceiver fabric interface power supply	Standard and low power ⁹	0.87	0.9	0.93	V
		Standard and low power ⁹	0.92	0.95	0.98	V
		SmartVID ¹⁰	0.82	—	0.93	V
V_CCPGM	Configuration pins power supply	1.8 V	1.71	1.8	1.89	V
		1.5 V	1.425	1.5	1.575	V
		1.2 V	1.14	1.2	1.26	V
V_CCERAM	Embedded memory power supply	0.9 V ⁹	0.87	0.9	0.93	V
V_CCERAM	Embedded memory power supply	0.95 V ⁹	0.92	0.95	0.98	V
V_CCBAT ¹¹	Battery back-up power supply  (For design security volatile key register)	—	1.14	—	1.89	V
V_CCPT	Power supply for programmable power technology and I/O pre-driver	1.8 V	1.71	1.8	1.89	V
V_CCIO	I/O buffers power supply	3.0 V (for 3 V I/O only)	2.85	3.0	3.15	V
		2.5 V (for 3 V I/O only)	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
		1.5 V	1.425	1.5	1.575	V
		1.35 V	¹²	1.35	¹²	V
		1.25 V	1.19	1.25	1.31	V
		1.2 V	¹²	1.2	¹²	V
V_{CCA_PLL}	PLL analog voltage regulator power supply	—	1.71	1.8	1.89	V
V_{REFP_ADC}	Precision voltage reference for voltage sensor	—	1.2475	1.25	1.2525	V
V_I ¹³ ¹⁴	DC input voltage	3 V I/O	–0.3	—	3.3	V
V_I ¹³ ¹⁴	DC input voltage	LVDS I/O	–0.3	—	2.19	V
V_O	Output voltage	—	0	—	V_CCIO	V
T_J	Operating junction temperature	Extended	0	—	100	°C
		Industrial	–40	—	100	°C
		Automotive	–40	—	125	°C
t_RAMP ¹⁵ ¹⁶	Power supply ramp time	Standard POR	200 µs	—	100 ms	—
t_RAMP ¹⁵ ¹⁶	Power supply ramp time	Fast POR	200 µs	—	4 ms	—

⁸ This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

⁹ You can operate –1 and –2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate –3 speed grade device only at 0.9 V typical value. Operating at 0.95 V results in higher core performance and higher power consumption. Refer to core performance in this datasheet for different typical values. For more information about the power consumption of different typical values, refer to the Intel^® Quartus^® Prime software, Power Analyzer report, and Early Power Estimator (EPE).

¹⁰ SmartVID is supported in devices with –3V speed grades only.

¹¹ If you do not use the design security feature in Intel^® Arria^® 10 devices, connect V_CCBAT to a 1.5-V to 1.8-V power supply. Intel^® Arria^® 10 power-on reset (POR) circuitry monitors V_CCBAT. Intel^® Arria^® 10 devices do not exit POR if V_CCBAT is not powered up.

¹² For minimum and maximum voltage values, refer to the I/O Standard Specifications section.

¹³ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

¹⁴ This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.

¹⁵ This is also applicable to HPS power supply. For HPS power supply, refer to t_RAMP specifications for standard POR when HPS_PORSEL = 0 and t_RAMP specifications for fast POR when HPS_PORSEL = 1.

¹⁶ t_ramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies.

Transceiver Power Supply Operating Conditions

Table 4. Transceiver Power Supply Operating Conditions for Intel^® Arria^® 10 GX/SX Devices
Symbol	Description	Condition ¹⁷	Minimum ¹⁸	Typical	Maximum ¹⁸	Unit
V_{CCT_GXB [L1,R4] [C, D, E, F, G, H, I, J]} ¹⁹	Transmitter power supply	Chip-to-Chip ≤ 17.4 Gbps Or Backplane ²⁰ ≤ 12.5 Gbps	1.0	1.03	1.06	V
V_{CCT_GXB [L1,R4] [C, D, E, F, G, H, I, J]} ¹⁹	Transmitter power supply	Chip-to-Chip ≤ 11.3 Gbps	0.92	0.95	0.98	V
V_{CCR_GXB[L1,R4] [C, D, E, F, G, H, I, J]} ¹⁹	Receiver power supply	Chip-to-Chip ≤ 17.4 Gbps Or Backplane ²⁰ ≤ 12.5 Gbps	1.0	1.03	1.06	V
V_{CCR_GXB[L1,R4] [C, D, E, F, G, H, I, J]} ¹⁹	Receiver power supply	Chip-to-Chip ≤ 11.3 Gbps	0.92	0.95	0.98	V
V_{CCH_GXB[L,R]}	Transceiver output buffer power supply	—	1.710	1.8	1.890	V

Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize power consumption. Refer to the Intel^® Arria^® 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Intel^® Quartus^® Prime pin report for information about pinning out the package to minimize power consumption for your specific design.

Table 5. Transceiver Power Supply Operating Conditions for Intel^® Arria^® 10 GT Devices
Symbol	Description	Condition ²¹	Minimum ¹⁸	Typical	Maximum ¹⁸	Unit
V_{CCT_GXB[L,R]}	Transmitter power supply	Chip-to-Chip ≤ 25.8 Gbps ²² Or Backplane ²⁰ ≤ 12.5 Gbps	1.10	1.12	1.14	V
		Chip-to-Chip ≤ 15 Gbps Or Backplane ²⁰ ≤ 12.5 Gbps	1.0	1.03	1.06	V
		Chip-to-Chip ≤ 11.3 Gbps	0.92	0.95	0.98	V
V_{CCR_GXB[L,R]}	Receiver power supply	Chip-to-Chip ≤ 25.8 Gbps Or Backplane ²⁰ ≤ 12.5 Gbps	1.10	1.12	1.14	V
		Chip-to-Chip ≤ 15 Gbps Or Backplane ²⁰ ≤ 12.5 Gbps	1.0	1.03	1.06	V
		Chip-to-Chip ≤ 11.3 Gbps	0.92	0.95	0.98	V
V_{CCH_GXB[L,R]}	Transceiver output buffer power supply	—	1.710	1.8	1.890	V

¹⁷ These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel^® Arria^® 10 GX/SX Devices for exact data rate ranges.

¹⁸ This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

¹⁹ To support PCIe^® Gen3, this pin must be 1.03 V (± 30 mV) or higher.

²⁰ Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.

²¹ These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel^® Arria^® 10 GT Devices table for exact data rate ranges.

²² 25.8 Gbps is the maximum data rate for GT channels. 17.4 Gbps is the maximum data rate for GX channels.

HPS Power Supply Operating Conditions

Table 6. HPS Power Supply Operating Conditions for Intel^® Arria^® 10 SX Devices. This table lists the steady-state voltage and current values expected from Intel^® Arria^® 10 system-on-a-chip (SoC) devices with ARM*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Intel^® Arria^® 10 Devices table for the steady-state voltage values expected from the FPGA portion of the Intel^® Arria^® 10 SoC devices.
Symbol	Description	Condition	Minimum ²³	Typical	Maximum ²³	Unit
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	0.9 V ²⁴	0.87	0.9	0.93	V
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	0.95 V ²⁴	0.92	0.95	0.98	V
V_{CCIO_HPS}	HPS I/O buffers power supply	3.0 V	2.85	3.0	3.15	V
		2.5 V	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
V_{CCIOREF_HPS}	HPS I/O pre-driver power supply	—	1.71	1.8	1.89	V
V_{CCPLL_HPS}	HPS PLL analog voltage regulator power supply	—	1.71	1.8	1.89	V

²³ This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

²⁴ V_{CCL_HPS} options are valid under the operating conditions specified in the Maximum HPS Clock Frequencies table.

DC Characteristics

Supply Current and Power Consumption

Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer feature.

Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel^® Quartus^® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

I/O Pin Leakage Current

Table 7. I/O Pin Leakage Current for Intel^® Arria^® 10 Devices. If V_O = V_CCIO to V_CCIOMAX, 300 μA of leakage current per I/O is expected.
Symbol	Description	Condition	Min	Max	Unit
I_I	Input pin	V_I = 0 V to V_CCIOMAX	–80	80	µA
I_OZ	Tri-stated I/O pin	V_O = 0 V to V_CCIOMAX	–80	80	µA

Bus Hold Specifications

The bus-hold trip points are based on calculated input voltages from the JEDEC^® standard.

Table 8. Bus Hold Parameters for Intel^® Arria^® 10 Devices
Parameter	Symbol	Condition	V_CCIO (V)										Unit
			1.2		1.5		1.8		2.5		3.0
			Min	Max	Min	Max	Min	Max	Min	Max	Min	Max
Bus-hold, low, sustaining current	I_SUSL	V_IN > V_IL (max)	8 ²⁵, 26 ²⁶	—	12 ²⁵, 32 ²⁶	—	30 ²⁵, 55 ²⁶	—	60	—	70	—	µA
Bus-hold, high, sustaining current	I_SUSH	V_IN < V_IH (min)	–8 ²⁵, –26 ²⁶	—	–12 ²⁵, –32 ²⁶	—	–30 ²⁵, –55 ²⁶	—	–60	—	–70	—	µA
Bus-hold, low, overdrive current	I_ODL	0 V < V_IN < V_CCIO	—	125	—	175	—	200	—	300	—	500	µA
Bus-hold, high, overdrive current	I_ODH	0 V < V_IN < V_CCIO	—	–125	—	–175	—	–200	—	–300	—	–500	µA
Bus-hold trip point	V_TRIP	—	0.3	0.9	0.38	1.13	0.68	1.07	0.70	1.7	0.8	2	V

²⁵ This value is only applicable for LVDS I/O bank.

²⁶ This value is only applicable for 3 V I/O bank.

OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.

Table 9. OCT Calibration Accuracy Specifications for Intel^® Arria^® 10 Devices. Calibration accuracy for the calibrated on-chip series termination (R_S OCT) and on-chip parallel termination (R_T OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Symbol	Description	Condition (V)	Resistance Tolerance				Unit
Symbol	Description	Condition (V)	–E1, –I1	–E2, –I2	–E3, –I3	–A3 ²⁷	Unit
25-Ω and 50-Ω R_S	Internal series termination with calibration (25-Ω and 50-Ω setting)	V_CCIO = 1.8, 1.5, 1.2	± 15	± 15	± 15	± 20	%
34-Ω and 40-Ω R_S	Internal series termination with calibration (34-Ω and 40-Ω setting)	V_CCIO = 1.5, 1.25, 1.2	± 15	± 15	± 15	± 20	%
34-Ω and 40-Ω R_S		V_CCIO = 1.35	± 20	± 20	± 20	± 20	%
48-Ω, 60-Ω, 80-Ω, and 120-Ω R_S	Internal series termination with calibration (48-Ω, 60-Ω, 80-Ω, and 120-Ω setting)	V_CCIO = 1.2	± 15	± 15	± 15	± 20	%
240-Ω R_S	Internal series termination with calibration (240-Ω setting)	V_CCIO = 1.2	± 20	± 20	± 20	± 20	%
30-Ω R_T	Internal parallel termination with calibration (30-Ω setting)	V_CCIO = 1.5, 1.35, 1.25	–10 to +40	–10 to +40	–10 to +40	–15 to +40	%
34-Ω, 48-Ω, 80-Ω, and 240-Ω R_T	Internal parallel termination with calibration (34-Ω, 48-Ω, 80-Ω, and 240-Ω setting)	V_CCIO = 1.2	± 15	± 15	± 15	± 20	%
40-Ω, 60-Ω, and 120-Ω R_T	Internal parallel termination with calibration (40-Ω, 60-Ω, and 120-Ω setting)	V_CCIO = 1.5, 1.35, 1.25, 1.2	–10 to +40	–10 to +40	–10 to +40	–15 to +40	%
40-Ω, 60-Ω, and 120-Ω R_T		V_CCIO = 1.2 ²⁸	± 15	± 15	± 15	± 20	%
80-Ω R_T	Internal parallel termination with calibration (80-Ω setting)	V_CCIO = 1.2	± 15	± 15	± 15	± 20	%

²⁷ Preliminary, pending characterization.

²⁸ Only applicable to POD12 I/O standard.

OCT Without Calibration Resistance Tolerance Specifications

Table 10. OCT Without Calibration Resistance Tolerance Specifications for Intel^® Arria^® 10 Devices. This table lists the Intel^® Arria^® 10 OCT without calibration resistance tolerance to PVT changes.
Symbol	Description	Condition (V)	Resistance Tolerance			Unit
Symbol	Description	Condition (V)	–E1, –I1	–E2, –I2	–E3, –I3, –A3 ²⁹	Unit
25-Ω and 50-Ω R_S	Internal series termination without calibration (25-Ω and 50-Ω setting)	V_CCIO = 3.0, 2.5	–40 to +30	± 40	± 40	%
25-Ω and 50-Ω R_S		V_CCIO = 1.8, 1.5, 1.2	–50 to +30	± 50	± 50	%
34-Ω and 40-Ω R_S	Internal series termination without calibration (34-Ω and 40-Ω setting)	V_CCIO = 1.5, 1.35, 1.25, 1.2	–50 to +30	± 50	± 50	%
48-Ω and 60-Ω R_S	Internal series termination without calibration (48-Ω and 60-Ω setting)	V_CCIO = 1.2	–50 to +30	± 50	± 50	%
120-Ω R_s	Internal series termination without calibration (120-Ω setting)	V_CCIO = 1.2	–50 to +30	± 50	± 50	%
100-Ω R_D	Internal differential termination (100-Ω setting)	V_CCIO = 1.8	± 25	± 35	± 40	%

²⁹ Preliminary, pending characterization.

Pin Capacitance

Table 11. Pin Capacitance for Intel^® Arria^® 10 Devices
Symbol	Description	Maximum	Unit
C_{IO_COLUMN}	Input capacitance on column I/O pins	2.5	pF
C_OUTFB	Input capacitance on dual-purpose clock output/feedback pins	2.5	pF

Internal Weak Pull-Up and Weak Pull-Down Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the pins as described in the Internal Weak Pull-Down Resistor Values for Intel^® Arria^® 10 Devices table.

Table 12. Internal Weak Pull-Up Resistor Values for Intel^® Arria^® 10 Devices
Symbol	Description	Condition (V) ³⁰	Value ³¹	Unit
R_PU	Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option.	V_CCIO = 3.0 ±5%	25	kΩ
		V_CCIO = 2.5 ±5%	25	kΩ
		V_CCIO = 1.8 ±5%	25	kΩ
		V_CCIO = 1.5 ±5%	25	kΩ
		V_CCIO = 1.35 ±5%	25	kΩ
		V_CCIO = 1.25 ±5%	25	kΩ
		V_CCIO = 1.2 ±5%	25	kΩ

Table 13. Internal Weak Pull-Down Resistor Values for Intel^® Arria^® 10 Devices
Pin Name	Description	Condition (V)	Value ³¹	Unit
`nIO_PULLUP`	Dedicated input pin that determines the internal pull-ups on user I/O pins and dual-purpose I/O pins.	V_CC = 0.9 ±3.33%	25	kΩ
`TCK`	Dedicated JTAG test clock input pin.	V_CCPGM = 1.8 ±5 %	25	kΩ
		V_CCPGM = 1.5 ±5%	25	kΩ
		V_CCPGM = 1.2 ±5%	25	kΩ
`MSEL[0:2]`	Configuration input pins that set the configuration scheme for the FPGA device.	V_CCPGM = 1.8 ±5%	25	kΩ
		V_CCPGM = 1.5 ±5%	25	kΩ
		V_CCPGM = 1.2 ±5%	25	kΩ

³⁰ Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO.

³¹ Valid with ±25% tolerances to cover changes over PVT.

I/O Standard Specifications

Tables in this section list the input voltage (V_IH and V_IL), output voltage (V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O standards supported by Intel^® Arria^® 10 devices.

For minimum voltage values, use the minimum V_CCIO values. For maximum voltage values, use the maximum V_CCIO values.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Single-Ended I/O Standards Specifications

Table 14. Single-Ended I/O Standards Specifications for Intel^® Arria^® 10 Devices
I/O Standard	V_CCIO(V)			V_IL(V)		V_IH(V)		V_OL(V)	V_OH(V)	I_OL ³² (mA)	I_OH ³² (mA)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Max	Min	I_OL ³² (mA)	I_OH ³² (mA)
3.0-V LVTTL	2.85	3	3.15	–0.3	0.8	1.7	3.3	0.4	2.4	2	–2
3.0-V LVCMOS	2.85	3	3.15	–0.3	0.8	1.7	3.3	0.2	V_CCIO – 0.2	0.1	–0.1
2.5 V	2.375	2.5	2.625	–0.3	0.7	1.7	3.3	0.4	2	1	–1
1.8 V	1.71	1.8	1.89	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.45	V_CCIO – 0.45	2	–2
1.5 V	1.425	1.5	1.575	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2
1.2 V	1.14	1.2	1.26	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2

³² To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the 3.0-V LVTTL specification (2 mA), you should set the current strength settings to 2 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel^® Arria^® 10 Devices
I/O Standard	V_CCIO (V)			V_REF (V)			V_TT (V)
I/O Standard	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max
SSTL-18  Class I, II	1.71	1.8	1.89	0.833	0.9	0.969	V_REF – 0.04	V_REF	V_REF + 0.04
SSTL-15  Class I, II	1.425	1.5	1.575	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-135/ SSTL-135  Class I, II	1.283	1.35	1.418	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-125/ SSTL-125  Class I, II	1.19	1.25	1.31	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-12/ SSTL-12  Class I, II	1.14	1.2	1.26	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
HSTL-18  Class I, II	1.71	1.8	1.89	0.85	0.9	0.95	—	V_CCIO/2	—
HSTL-15  Class I, II	1.425	1.5	1.575	0.68	0.75	0.9	—	V_CCIO/2	—
HSTL-12  Class I, II	1.14	1.2	1.26	0.47 × V_CCIO	0.5 × V_CCIO	0.53 × V_CCIO	—	V_CCIO/2	—
HSUL-12	1.14	1.2	1.3	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	—	—	—
POD12	1.16	1.2	1.24	0.69 × V_CCIO	0.7 × V_CCIO	0.71 × V_CCIO	—	V_CCIO	—

Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel^® Arria^® 10 Devices
I/O Standard	V_IL(DC)(V)		V_IH(DC) (V)		V_IL(AC) (V)	V_IH(AC) (V)	V_OL (V)	V_OH (V)	I_OL ³³ (mA)	I_OH ³³ (mA)
I/O Standard	Min	Max	Min	Max	Max	Min	Max	Min	I_OL ³³ (mA)	I_OH ³³ (mA)
SSTL-18 Class I	–0.3	V_REF –0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	V_TT – 0.603	V_TT + 0.603	6.7	–6.7
SSTL-18 Class II	–0.3	V_REF –0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	0.28	V_CCIO –0.28	13.4	–13.4
SSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	8	–8
SSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	16	–16
SSTL-135/ SSTL-135  Class I, II	—	V_REF – 0.09	V_REF + 0.09	—	V_REF – 0.16	V_REF + 0.16	0.2 × V_CCIO	0.8 × V_CCIO	—	—
SSTL-125/ SSTL-125  Class I, II	—	V_REF – 0.09	V_REF + 0.09	—	V_REF – 0.15	V_REF + 0.15	0.2 × V_CCIO	0.8 × V_CCIO	—	—
SSTL-12/ SSTL-12  Class I, II	—	V_REF – 0.10	V_REF + 0.10	—	V_REF – 0.15	V_REF + 0.15	0.2 × V_CCIO	0.8 × V_CCIO	—	—
HSTL-18 Class I	—	V_REF –0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-18 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	16	–16
HSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO –0.4	16	–16
HSTL-12 Class I	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	0.25 × V_CCIO	0.75 × V_CCIO	8	–8
HSTL-12 Class II	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	0.25 × V_CCIO	0.75 × V_CCIO	16	–16
HSUL-12	—	V_REF – 0.13	V_REF + 0.13	—	V_REF – 0.22	V_REF+ 0.22	0.1 × V_CCIO	0.9 × V_CCIO	—	—
POD12	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	(0.7 – 0.15) × V_CCIO	(0.7 + 0.15) × V_CCIO	—	—

³³ To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Differential SSTL I/O Standards Specifications

Table 17. Differential SSTL I/O Standards Specifications for Intel^® Arria^® 10 Devices
I/O Standard	V_CCIO (V)			V_SWING(DC) (V)		V_SWING(AC) (V)		V_IX(AC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Min	Typ	Max
SSTL-18 Class I, II	1.71	1.8	1.89	0.25	V_CCIO+ 0.6	0.5	V_CCIO + 0.6	V_CCIO/2 – 0.175	—	V_CCIO/2 + 0.175
SSTL-15 Class I, II	1.425	1.5	1.575	0.2	³⁴	2(V_IH(AC) – V_REF)	2(V_REF – V_IL(AC))	V_CCIO/2 – 0.15	—	V_CCIO/2 + 0.15
SSTL-135/ SSTL-135  Class I, II	1.283	1.35	1.45	0.18	³⁴	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_CCIO/2 – 0.15	V_CCIO/2	V_CCIO/2 + 0.15
SSTL-125/ SSTL-125  Class I, II	1.19	1.25	1.31	0.18	³⁴	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_CCIO/2 – 0.15	V_CCIO/2	V_CCIO/2 + 0.15
SSTL-12/ SSTL-12  Class I, II	1.14	1.2	1.26	0.16	³⁴	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_REF – 0.15	V_CCIO/2	V_REF + 0.15
POD12	1.16	1.2	1.24	0.16	—	0.3	—	V_REF – 0.08	—	V_REF + 0.08

³⁴ The maximum value for V_SWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC) and V_IL(DC)).

Differential HSTL and HSUL I/O Standards Specifications

Table 18. Differential HSTL and HSUL I/O Standards Specifications for Intel^® Arria^® 10 Devices
I/O Standard	V_CCIO (V)			V_DIF(DC) (V)		V_DIF(AC) (V)		V_IX(AC) (V)			V_CM(DC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Min	Typ	Max	Min	Typ	Max
HSTL-18 Class I, II	1.71	1.8	1.89	0.2	—	0.4	—	0.78	—	1.12	0.78	—	1.12
HSTL-15 Class I, II	1.425	1.5	1.575	0.2	—	0.4	—	0.68	—	0.9	0.68	—	0.9
HSTL-12 Class I, II	1.14	1.2	1.26	0.16	V_CCIO+ 0.3	0.3	V_CCIO + 0.48	—	0.5 × V_CCIO	—	0.4 × V_CCIO	0.5 × V_CCIO	0.6 ×  V_CCIO
HSUL-12	1.14	1.2	1.3	2(V_IH(DC) – V_REF)	2(V_REF – V_IH(DC))	2(V_IH(AC) – V_REF)	2(V_REF – V_IH(AC))	0.5 × V_CCIO – 0.12	0.5 × V_CCIO	0.5 ×  V_CCIO +0.12	0.4 × V_CCIO	0.5 × V_CCIO	0.6 ×  V_CCIO

Differential I/O Standards Specifications

Table 19. Differential I/O Standards Specifications for Intel^® Arria^® 10 Devices. Differential inputs are powered by V_CCPT which requires 1.8 V.
I/O Standard	V_CCIO (V)			V_ID (mV) ³⁵			V_ICM(DC) (V)			V_OD (V) ³⁶			V_OCM (V) ³⁶
I/O Standard	Min	Typ	Max	Min	Condition	Max	Min	Condition	Max	Min	Typ	Max	Min	Typ	Max
LVDS ³⁷	1.71	1.8	1.89	100	V_CM= 1.25 V	—	0	D_MAX≤700 Mbps	1.85	0.247	—	0.6	1.125	1.25	1.375
LVDS ³⁷	1.71	1.8	1.89	100	V_CM= 1.25 V	—	1	D_MAX>700 Mbps	1.6	0.247	—	0.6	1.125	1.25	1.375
RSDS (HIO) ³⁸	1.71	1.8	1.89	100	V_CM= 1.25 V	—	0.3	—	1.4	0.1	0.2	0.6	0.5	1.2	1.4
Mini-LVDS (HIO) ³⁹	1.71	1.8	1.89	200	—	600	0.4	—	1.325	0.25	—	0.6	1	1.2	1.4
LVPECL ⁴⁰	1.71	1.8	1.89	300	—	—	0.6	D_MAX≤700 Mbps	1.7	—	—	—	—	—	—
LVPECL ⁴⁰	1.71	1.8	1.89	300	—	—	1	D_MAX>700 Mbps	1.6	—	—	—	—	—	—

³⁵ The minimum V_ID value is applicable over the entire common mode range, V_CM.

³⁶ R_L range: 90 ≤ R_L ≤ 110 Ω.

³⁷ For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0 V to 1.85 V for data rates below 700 Mbps.

³⁸ For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.

³⁹ For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.1 V to 1.625 V.

⁴⁰ For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps.

Switching Characteristics

This section provides the performance characteristics of Intel^® Arria^® 10 core and periphery blocks for extended grade devices.

Transceiver Performance Specifications

Transceiver Performance for Intel Arria 10 GX/SX Devices

Table 20. Transmitter and Receiver Data Rate Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Transceiver Speed Grade 3	Transceiver Speed Grade 4	Unit
Chip-to-Chip ⁴¹	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 1.03 V	17.4	15	14.2	12.5	Gbps
	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 0.95 V	11.3	11.3	11.3	11.3	Gbps
	Minimum Data Rate	1.0 ⁴²				Gbps
Backplane ⁴¹	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 1.03 V	12.5	12.5	12.5	10.3125	Gbps
Backplane ⁴¹	Minimum Data Rate	1.0 ⁴²				Gbps

Table 21. ATX PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Transceiver Speed Grade 3	Transceiver Speed Grade 4	Unit
Supported Output Frequency	Maximum Frequency	8.7	7.5	7.1	6.25	GHz
Supported Output Frequency	Minimum Frequency	500				MHz

Table 22. Fractional PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Transceiver Speed Grade 3	Transceiver Speed Grade 4	Unit
Supported Output Frequency	Maximum Frequency	6.25	6.25	6.25	6.25	GHz
Supported Output Frequency	Minimum Frequency	500				MHz

Table 23. CMU PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Transceiver Speed Grade 3	Transceiver Speed Grade 4	Unit
Supported Output Frequency	Maximum Frequency	5.15625	5.15625	5.15625	5.15625	GHz
Supported Output Frequency	Minimum Frequency	2450				MHz

⁴¹ Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.

⁴² Intel^® Arria^® 10 transceivers can support data rates down to 125 Mbps with over sampling.

High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GX/SX Devices

Table 24. High-Speed Serial Transceiver-Fabric Interface Performance for Intel^® Arria^® 10 GX/SX Devices. The frequencies listed are the maximum frequencies.
Symbol/Description	Condition (V)	Core Speed Grade with Power Options			Unit
Symbol/Description	Condition (V)	-E1H	-E2 / -I2	-E3 / -I3 / -A3 ⁴³	Unit
20-bit interface - FIFO	V_CC = 0.9/0.95	516	400	400	MHz
20-bit interface - Registered	V_CC = 0.9/0.95	491	400	400	MHz
32-bit interface - FIFO	V_CC = 0.9/0.95	441	404	335	MHz
32-bit interface - Registered	V_CC = 0.9/0.95	441	404	335	MHz
64-bit interface - FIFO	V_CC = 0.9/0.95	272	234	222	MHz
64-bit interface - Registered	V_CC = 0.9/0.95	272	234	222	MHz
PCIe Gen3 HIP-Fabric interface	V_CC = 0.9/0.95	300	250	125	MHz

⁴³ Preliminary, pending characterization.

Transceiver Performance for Intel Arria 10 GT Devices

Table 25. Transmitter and Receiver Data Rate Performance
Symbol/Description	Condition		Transceiver Speed Grade 1	Transceiver Speed Grade 2	Unit
Chip-to-chip ⁴⁴	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 1.12 V	GT Channel ⁴⁵	25.8	25.8	Gbps
	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 1.12 V	GX Channel	17.4	15	Gbps
	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 1.03 V	GX Channel	16	14.2	Gbps
	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 0.95 V	GX Channel	11.3	11.3	Gbps
	Minimum data rate	GT Channel	1.0 ⁴⁶		Gbps
	Minimum data rate	GX Channel	1.0 ⁴⁶		Gbps
Backplane ⁴⁴	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 1.12 V	GX Channel	12.5	12.5	Gbps
	Maximum data rate V_{CCR_GXB} = V_{CCT_GXB} = 1.03 V	GX Channel	12.5	12.5	Gbps
	Minimum data rate	GX Channel	1.0 ⁴⁶		Gbps

Table 26. ATX PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Unit
Supported Output Frequency	Maximum frequency	12.9		GHz
Supported Output Frequency	Minimum frequency	500		MHz

Table 27. Fractional PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Unit
Supported Output Frequency	Maximum frequency	6.25		GHz
Supported Output Frequency	Minimum frequency	500		MHz

Table 28. CMU PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Unit
Supported Output Frequency	Maximum frequency	5.15625		GHz
Supported Output Frequency	Minimum frequency	2450		MHz

⁴⁴ Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.

⁴⁵ GT channels can only achieve 25.8 Gbps when V_{CCT_GXB} = 1.12 V and V_{CCR_GXB} = 1.12 V.

⁴⁶ Intel^® Arria^® 10 transceivers can support data rates down to 125 Mbps with over sampling.

High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GT Devices

Table 29. High-Speed Serial Transceiver-Fabric Interface Performance for Intel^® Arria^® 10 GT Devices. The frequencies listed are the maximum frequencies.
Symbol/Description	Condition (V)	Core Speed Grade with Power Options		Unit
Symbol/Description	Condition (V)	-1	-2	Unit
20-bit interface - FIFO	V_CC = 0.9/0.95	400		MHz
20-bit interface - Registered	V_CC = 0.9/0.95	400		MHz
32-bit interface - FIFO	V_CC = 0.9/0.95	404		MHz
32-bit interface - Registered	V_CC = 0.9/0.95	404		MHz
64-bit interface - FIFO	V_CC = 0.9/0.95	407		MHz
64-bit interface - Registered	V_CC = 0.9/0.95	407		MHz
PCIe Gen3 HIP-Fabric interface	V_CC = 0.9/0.95	250		MHz

Transceiver Specifications for Intel Arria 10 GX, SX, and GT Devices

Table 30. Reference Clock Specifications
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	Dedicated reference clock pin	CML, Differential LVPECL, LVDS, and HCSL
Supported I/O Standards	RX reference clock pin	CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU PLL)		61	—	800	MHz
Input Reference Clock Frequency (ATX PLL)		100	—	800	MHz
Input Reference Clock Frequency (fPLL PLL)		25 ⁴⁷ / 50 ⁴⁸	—	800	MHz
Rise time	20% to 80%	—	—	400	ps
Fall time	80% to 20%	—	—	400	ps
Duty cycle	—	45	—	55	%
Spread-spectrum modulating clock frequency	PCIe	30	—	33	kHz
Spread-spectrum downspread	PCIe	—	0 to –0.5	—	%
On-chip termination resistors	—	—	100	—	Ω
Absolute V_MAX	Dedicated reference clock pin	—	—	1.6	V
Absolute V_MAX	RX reference clock pin	—	—	1.2	V
Absolute V_MIN	—	–0.4	—	—	V
Peak-to-peak differential input voltage	—	200	—	1600	mV
V_ICM (AC coupled)	V_{CCR_GXB} = 0.95 V	—	0.95	—	V
	V_{CCR_GXB} = 1.03 V	—	1.03	—	V
	V_{CCR_GXB} = 1.12 V	—	1.12	—	V
V_ICM (DC coupled)	HCSL I/O standard for PCIe reference clock	250	—	550	mV
Transmitter `REFCLK` Phase Noise (622 MHz) ⁴⁹	100 Hz	—	—	–70	dBc/Hz
	1 kHz	—	—	–90	dBc/Hz
	10 kHz	—	—	–100	dBc/Hz
	100 kHz	—	—	–110	dBc/Hz
	≥ 1 MHz	—	—	–120	dBc/Hz
Transmitter `REFCLK` Phase Jitter (100 MHz)	1.5 MHz to 100 MHz (PCIe)	—	—	4.2	ps (rms)
R_REF	—	—	2.0 k ±1%	—	Ω
T_{SSC-MAX-PERIOD-SLEW}	Max SSC df/dt			0.75

Table 31. Transceiver Clocks Specifications
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
`CLKUSR` pin for transceiver calibration	Transceiver Calibration	100	—	125	MHz
`reconfig_clk`	Reconfiguration interface	100	—	125	MHz

Table 32. Transceiver Clock Network Maximum Data Rate Specifications
Clock Network	Maximum Performance ⁵⁰			Channel Span	Unit
Clock Network	ATX	fPLL	CMU	Channel Span	Unit
x1	17.4	12.5	10.3125	6 channels in a single bank	Gbps
x6	17.4	12.5	N/A	6 channels in a single bank	Gbps
PLL feedback compensation mode	17.4	12.5	N/A	Side-wide	Gbps
xN at 0.95 V V_{CCR_GXB}/V_{CCT_GXB}	10.5	10.5	N/A	Up two banks and down two banks ⁵⁰ ⁵¹	Gbps
xN at 1.03 V V_{CCR_GXB}/V_{CCT_GXB}	15.0	12.5	N/A	Up two banks and down two banks⁵⁰ ⁵¹	Gbps
xN at 1.12 V V_{CCR_GXB}/V_{CCT_GXB}	16.0	12.5	N/A	Up two banks and down two banks⁵⁰ ⁵¹	Gbps

Table 33. Receiver Specifications
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O, CML , Differential LVPECL , and LVDS ⁵²
Absolute V_MAX for a receiver pin ⁵³	—	—	—	1.2	V
Absolute V_MIN for a receiver pin ⁵³	—	-0.4	—	—	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) before device configuration	—	—	—	1.6	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) after device configuration	V_{CCR_GXB} = 1.12 V	—	—	2.0	V
	V_{CCR_GXB} = 1.03 V	—	—	2.0	V
	V_{CCR_GXB} = 0.95 V	—	—	2.4	V
Minimum differential eye opening at receiver serial input pins ⁵⁴	—	50	—	—	mV
Differential on-chip termination resistors	85-Ω setting	—	85 ± 30%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 30%	—	Ω
V_ICM (AC and DC coupled) ⁵⁵	V_CM = 0.65 V	—	600	—	mV
	V_CM = 0.7 V	—	700	—	mV
	V_CM = 0.75 V	—	700	—	mV
t_LTR ⁵⁶	—	—	—	10	µs
t_LTD ⁵⁷	—	4	—	—	µs
t_{LTD_manual} ⁵⁸	—	4	—	—	µs
t_{LTR_LTD_manual} ⁵⁹	—	15	—	—	µs
Run Length	—	—	—	200	UI
CDR PPM tolerance	PCIe-only	-300	—	300	PPM
CDR PPM tolerance	All other protocols	-1000	—	1000	PPM
Programmable DC Gain	Setting = 0-4	0	—	10	dB
Programmable AC Gain at High Gain mode and Data Rate ≤ 6 Gbps with 0.95 V V_CCR	Setting = 0-28	0	—	19	dB
Programmable AC Gain at High Gain mode and Data Rate ≤ 6 Gpbs with 1.03 V V_CCR	Setting = 0-28	0	—	21	dB
Programmable AC Gain at High Gain mode and Data Rate ≤ 17.4 Gpbs with 1.03 V V_CCR	Setting = 0-28	0	—	17	dB
Programmable AC Gain at High Data Rate mode	Setting = 0-15	0	—	8	dB

Table 34. Transmitter Specifications
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O ⁶⁰			—
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_OCM (AC coupled)	V_CCT = 0.95 V	—	450	—	mV
	V_CCT = 1.03 V	—	500	—	mV
	V_CCT = 1.12 V	—	550	—	mV
V_OCM (DC coupled)	V_CCT = 0.95 V	—	450	—	mV
	V_CCT = 1.03 V	—	500	—	mV
	V_CCT = 1.12 V	—	550	—	mV
Rise time ⁶¹	20% to 80%	20	—	130	ps
Fall time ⁶¹	80% to 20%	20	—	130	ps
Intra-differential pair skew ⁶²	TX V_CM = 0.5 V and slew rate setting of SLEW_R5 ⁶³	—	—	15	ps

Table 35. Typical Transmitter V_OD Settings
Symbol	V_OD Setting	V_OD-to-V_CCTRatio
V_OD differential value = V_OD-to-V_CCT ratio x V_CCT	31	1.00
	30	0.97
	29	0.93
	28	0.90
	27	0.87
	26	0.83
	25	0.80
	24	0.77
	23	0.73
	22	0.70
	21	0.67
	20	0.63
	19	0.60
	18	0.57
	17	0.53
	16	0.50
	15	0.47
	14	0.43
	13	0.40
	12	0.37

Table 36. Transmitter Channel-to-channel Skew Specifications
Mode	Channel Span	Maximum Skew	Unit
x6 Clock	Up to 6 channels in one bank	61	ps
xN Clock	Within 2 banks	230	ps
xN Clock	Up 2 banks and down 2 banks	500	ps
PLL Feedback Compensation ⁶⁴, ⁶⁵, ⁶⁶	Side-wide	1600	ps

⁴⁷ This specification is for HDMI mode only.

⁴⁸ This specification is for other non-HDMI modes.

⁴⁹ To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622).

⁵⁰ The maximum data rate depends on speed grade.

⁵¹ For more information, refer to the PLLs and Clock Networks chapter of the Intel^® Arria^® 10 Transceiver PHY User Guide.

⁵² CML, Differential LVPECL, and LVDS are only used on AC coupled links.

⁵³ The device cannot tolerate prolonged operation at this absolute maximum.

⁵⁴ The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

⁵⁵ Intel^® Arria^® 10 devices only support DC coupling when using the Hybrid Memory Cube (HMC) or the Intel QuickPath Interconnect (QPI) specifications.

⁵⁶ t_LTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.

⁵⁷ t_LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.

⁵⁸ t_{LTD_manual} is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.

⁵⁹ t_{LTR_LTD_manual} is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

⁶⁰ High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel^® Arria^® 10 transceivers.

⁶¹ The Intel^® Quartus^® Prime software automatically selects the appropriate slew rate depending on the design configurations.

⁶² In QPI mode, if V_CM < 0.17 V, the input Vid must be greater than 100 mV. If V_CM > 0.17 V, the input Vid must be greater than 70 mV.

⁶³ SLEW_R1 is the slowest and SLEW_R5 is the fastest. SLEW_R6 and SLEW_R7 are not used.

⁶⁴ refclk is set to 125 MHz during the test.

⁶⁵ You can reduce the lane-to-lane skew by increasing the reference clock frequency.

⁶⁶ The middle refclk location provides the lowest lane-to-lane skew.

Core Performance Specifications

Clock Tree Specifications

Table 37. Clock Tree Performance for Intel^® Arria^® 10 Devices
Parameter	Performance (All Speed Grades)	Unit
Global clock, regional clock, and small periphery clock	644	MHz
Large periphery clock	525	MHz

PLL Specifications

Fractional PLL Specifications

Table 38. Fractional PLL Specifications for Intel^® Arria^® 10 Devices
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	—	30	—	800 ⁶⁷	MHz
f_INPFD	Input clock frequency to the phase frequency detector (PFD)	—	30	—	700	MHz
f_{CASC_INPFD}	Input clock frequency to the PFD of destination cascade PLL	—	30	—	60	MHz
f_VCO	PLL voltage-controlled oscillator (VCO) operating range	—	6	—	14.025	GHz
t_EINDUTY	Input clock duty cycle	—	45	—	55	%
f_OUT	Output frequency for internal global or regional clock	—	—	—	644	MHz
f_DYCONFIGCLK	Dynamic configuration clock for `reconfig_clk`	—	—	—	100	MHz
t_LOCK	Time required to lock from end-of-device configuration or deassertion of `pll_powerdown`	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
f_CLBW	PLL closed-loop bandwidth	—	0.3	—	4	MHz
t_{PLL_PSERR}	Accuracy of PLL phase shift	Non-SmartVID	—	—	50	ps
t_{PLL_PSERR}	Accuracy of PLL phase shift	SmartVID	—	—	75	ps
t_ARESET	Minimum pulse width on the `pll_powerdown` signal	—	10	—	—	ns
t_INCCJ ⁶⁸ ⁶⁹	Input clock cycle-to-cycle jitter	F_REF ≥ 100 MHz	—	—	0.13	UI (p-p)
t_INCCJ ⁶⁸ ⁶⁹	Input clock cycle-to-cycle jitter	F_REF < 100 MHz	—	—	650	ps (p-p)
t_OUTPJ ⁷⁰	Period jitter for clock output	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_OUTPJ ⁷⁰	Period jitter for clock output	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_OUTCCJ ⁷⁰	Cycle-to-cycle jitter for clock output	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_OUTCCJ ⁷⁰	Cycle-to-cycle jitter for clock output	F_OUT < 100 MHz	—	—	60	mUI (p-p)
dK_BIT	Bit number of Delta Sigma Modulator (DSM)	—	—	32	—	bit

⁶⁷ This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

⁶⁸ A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

⁶⁹ F_REF is f_IN/N, specification applies when N = 1.

⁷⁰ External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel^® Arria^® 10 Devices table.

I/O PLL Specifications

Table 39. I/O PLL Specifications for Intel^® Arria^® 10 Devices
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	–1 speed grade	10	—	800 ⁷¹	MHz
		–2 speed grade	10	—	700 ⁷¹	MHz
		–3 speed grade	10	—	650 ⁷¹	MHz
f_INPFD	Input clock frequency to the PFD	—	10	—	325	MHz
f_{CASC_INPFD}	Input clock frequency to the PFD of destination cascade PLL	—	10	—	60	MHz
f_VCO	PLL VCO operating range	–1 speed grade	600	—	1600	MHz
		–2 speed grade	600	—	1434	MHz
		–3 speed grade	600	—	1250	MHz
f_CLBW	PLL closed-loop bandwidth	—	0.1	—	8	MHz
t_EINDUTY	Input clock or external feedback clock input duty cycle	—	40	—	60	%
f_OUT	Output frequency for internal global or regional clock (`C` counter)	–1, –2, –3 speed grade	—	—	644	MHz
f_{OUT_EXT}	Output frequency for external clock output	–1 speed grade	—	—	800	MHz
		–2 speed grade	—	—	720	MHz
		–3 speed grade	—	—	650	MHz
t_OUTDUTY	Duty cycle for dedicated external clock output (when set to 50%)	Non-SmartVID	45	50	55	%
t_OUTDUTY		SmartVID	42	50	58	%
t_FCOMP	External feedback clock compensation time	—	—	—	10	ns
f_DYCONFIGCLK	Dynamic configuration clock for `mgmt_clk` and `scanclk`	—	—	—	100	MHz
t_LOCK	Time required to lock from end-of-device configuration or deassertion of `areset`	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
t_{PLL_PSERR}	Accuracy of PLL phase shift	—	—	—	±50	ps
t_ARESET	Minimum pulse width on the `areset` signal	—	10	—	—	ns
t_INCCJ ⁷² ⁷³	Input clock cycle-to-cycle jitter	F_REF ≥ 100 MHz	—	—	0.15	UI (p-p)
t_INCCJ ⁷² ⁷³	Input clock cycle-to-cycle jitter	F_REF < 100 MHz	—	—	750	ps (p-p)
t_{OUTPJ_DC}	Period jitter for dedicated clock output	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{OUTPJ_DC}	Period jitter for dedicated clock output	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)
t_{OUTCCJ_DC}	Cycle-to-cycle jitter for dedicated clock output	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{OUTCCJ_DC}	Cycle-to-cycle jitter for dedicated clock output	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)
t_{OUTPJ_IO} ⁷⁴	Period jitter for clock output on the regular I/O	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_{OUTPJ_IO} ⁷⁴	Period jitter for clock output on the regular I/O	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_{OUTCCJ_IO} ⁷⁴	Cycle-to-cycle jitter for clock output on the regular I/O	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_{OUTCCJ_IO} ⁷⁴	Cycle-to-cycle jitter for clock output on the regular I/O	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_{CASC_OUTPJ_DC}	Period jitter for dedicated clock output in cascaded PLLs	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{CASC_OUTPJ_DC}	Period jitter for dedicated clock output in cascaded PLLs	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)

⁷¹ This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

⁷² A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

⁷³ F_REF is f_IN/N, specification applies when N = 1.

⁷⁴ External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel^® Arria^® 10 Devices table.

DSP Block Specifications

Table 40. DSP Block Performance Specifications for Intel^® Arria^® 10 Devices (V_CC and V_CCP at 0.9 V Typical Value)
Mode	Performance						Unit
Mode	–E1S, –E1H	–I1S, –I1H	–E2L, –E2S	–I2L, –I2S	–E3S, –E3V	–I3S, –I3V, –A3S ⁷⁵	Unit
Fixed-point 18 × 19 multiplication mode	548	528	456	438	364	346	MHz
Fixed-point 27 × 27 multiplication mode	541	522	450	434	358	344	MHz
Fixed-point 18 × 18 multiplier adder mode	548	529	459	440	370	351	MHz
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode	539	517	444	422	349	326	MHz
Fixed-point 18 × 19 systolic mode	548	529	459	440	370	351	MHz
Complex 18 × 19 multiplication mode	548	528	456	438	364	346	MHz
Floating point multiplication mode	548	527	447	427	347	326	MHz
Floating point adder or subtract mode	488	471	388	369	288	266	MHz
Floating point multiplier adder or subtract mode	483	465	386	368	290	270	MHz
Floating point multiplier accumulate mode	510	490	418	393	326	294	MHz
Floating point vector one mode	502	482	404	382	306	282	MHz
Floating point vector two mode	474	455	383	367	293	278	MHz

Table 41. DSP Block Performance Specifications for Intel^® Arria^® 10 Devices (V_CC and V_CCP at 0.95 V Typical Value)
Mode	Performance		Unit
Mode	–I1S, –I1H	–I2L, –I2S	Unit
Fixed-point 18 × 19 multiplication mode	635	517	MHz
Fixed-point 27 × 27 multiplication mode	633	517	MHz
Fixed-point 18 × 18 multiplier adder mode	635	516	MHz
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode	631	509	MHz
Fixed-point 18 × 19 systolic mode	635	516	MHz
Complex 18 × 19 multiplication mode	635	517	MHz
Floating point multiplication mode	635	501	MHz
Floating point adder or subtract mode	564	468	MHz
Floating point multiplier adder or subtract mode	564	475	MHz
Floating point multiplier accumulate mode	581	482	MHz
Floating point vector one mode	574	471	MHz
Floating point vector two mode	550	450	MHz

⁷⁵ Preliminary, pending characterization.

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel^® Quartus^® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX.

Table 42. Memory Block Performance Specifications for Intel^® Arria^® 10 Devices (V_CC and V_CCP at 0.9 V Typical Value)
Memory	Mode	Performance
Memory	Mode	–E1S, –E1H	–I1S, –I1H	–E2L, –E2S, –I2L, –I2S	–E3S, –E3V	–I3S, –I3V, –A3S ⁷⁶	Unit
MLAB	Single port, all supported widths (×16/×32)	700	660	570	490	490	MHz
	Simple dual-port, all supported widths (×16/×32)	700	660	570	490	490	MHz
	Simple dual-port with the read-during-write option set to Old Data, all supported widths	460	450	400	330	330	MHz
	ROM, all supported width (×16/×32)	700	660	570	490	490	MHz
M20K Block	Single-port, all supported widths	730	690	625	530	510	MHz
	Simple dual-port, all supported widths	730	690	625	530	510	MHz
	Simple dual-port with the read-during-write option set to Old Data, all supported widths	550	520	470	410	410	MHz
	Simple dual-port with ECC enabled, 512 × 32	470	450	410	360	360	MHz
	Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32	620	590	520	470	470	MHz
	True dual port, all supported widths	730	690	600	480	480	MHz
	ROM, all supported widths	730	690	625	530	510	MHz

Table 43. Memory Block Performance Specifications for Intel^® Arria^® 10 Devices (V_CC and V_CCP at 0.95 V Typical Value)
Memory	Mode	Performance
Memory	Mode	–I1S, –I1H	–I2L, –I2S	Unit
MLAB	Single port, all supported widths (×16/×32)	706	610	MHz
	Simple dual-port, all supported widths (×16/×32)	706	610	MHz
	Simple dual-port with read and write at the same address	482	428	MHz
	ROM, all supported width (×16/×32)	706	610	MHz
M20K Block	Single-port, all supported widths	735	670	MHz
	Simple dual-port, all supported widths	735	670	MHz
	Simple dual-port with the read-during-write option set to Old Data, all supported widths	555	500	MHz
	Simple dual-port with ECC enabled, 512 × 32	480	440	MHz
	Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32	630	555	MHz
	True dual port, all supported widths	735	640	MHz
	ROM, all supported widths	735	670	MHz

⁷⁶ Preliminary, pending characterization.

Temperature Sensing Diode Specifications

Internal Temperature Sensing Diode Specifications

Table 44. Internal Temperature Sensing Diode Specifications for Intel^® Arria^® 10 Devices
Temperature Range	Accuracy	Offset Calibrated Option	Sampling Rate	Conversion Time	Resolution
–40 to 125°C	±5°C	No	1 MHz	< 5 ms	10 bits

External Temperature Sensing Diode Specifications

Table 45. External Temperature Sensing Diode Specifications for Intel^® Arria^® 10 Devices.

The typical value is at 25°C.

Diode accuracy improves with lower injection current.

Absolute accuracy is dependent on third party external diode ADC and integration specifics.
Description	Min	Typ	Max	Unit
I_bias, diode source current	10	—	100	μA
V_bias, voltage across diode	0.3	—	0.9	V
Series resistance	—	—	< 1	Ω
Diode ideality factor	—	1.03	—	—

Internal Voltage Sensor Specifications

Table 46. Internal Voltage Sensor Specifications for Intel^® Arria^® 10 Devices
Parameter		Minimum	Typical	Maximum	Unit
Resolution		—	—	6	Bit
Sampling rate		—	—	500	Ksps
Differential non-linearity (DNL)		—	—	±1	LSB
Integral non-linearity (INL)		—	—	±1	LSB
Gain error		—	—	±1	%
Offset error		—	—	±1	LSB
Input capacitance		—	20	—	pF
Clock frequency		0.1	—	11	MHz
Unipolar Input Mode	Input signal range for Vsigp	0	—	1.5	V
	Common mode voltage on Vsign	0	—	0.25	V
	Input signal range for Vsigp – Vsign	0	—	1.25	V

Periphery Performance Specifications

This section describes the periphery performance, high-speed I/O, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

Table 47. High-Speed I/O Specifications for Intel^® Arria^® 10 Devices.
When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.

For LVDS applications, you must use the PLLs in integer PLL mode.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

The Intel^® Arria^® 10 devices support the following output standards using true LVDS output buffer types on all I/O banks:

True RSDS output standard with data rates of up to 360 Mbps

True mini-LVDS output standard with data rates of up to 400 Mbps
Symbol		Condition	–E1S ⁷⁷, –E1H, –I1S⁷⁷, –I1H			–E2L, –E2S⁷⁷, –I2L, –I2S⁷⁷			–E3L, –E3S⁷⁷, –E3V, –I3L, –I3S⁷⁷, –I3V, –A3S ⁷⁸			Unit
Symbol		Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_{HSCLK_in}(input clock frequency) True Differential I/O Standards		Clock boost factor  W = 1 to 40 ⁷⁹	10	—	800	10	—	700	10	—	625	MHz
f_{HSCLK_in}(input clock frequency) Single Ended I/O Standards		Clock boost factor  W = 1 to 40 ⁷⁹	10	—	625	10	—	625	10	—	525	MHz
f_{HSCLK_OUT} (output clock frequency)		—	—	—	800 ⁸⁰	—	—	700 ⁸⁰	—	—	625 ⁸⁰	MHz
Transmitter	True Differential I/O Standards - f_HSDR (data rate) ⁸¹	SERDES factor J = 4 to 10 ⁸² ⁸³ ⁸⁴	⁸⁴	—	1600	⁸⁴	—	1434	⁸⁴	—	1250	Mbps
		SERDES factor J = 3 ⁸² ⁸³ ⁸⁴	⁸⁴	—	1200	⁸⁴	—	1076	⁸⁴	—	938	Mbps
		SERDES factor J = 2, uses DDR registers	⁸⁴	—	333 ⁸⁵	⁸⁴	—	275 ⁸⁵	⁸⁴	—	250 ⁸⁵	Mbps
		SERDES factor J = 1, uses DDR registers	⁸⁴	—	333 ⁸⁵	⁸⁴	—	275 ⁸⁵	⁸⁴	—	250 ⁸⁵	Mbps
	t_{x Jitter}- True Differential I/O Standards	Total jitter for data rate, 600 Mbps – 1.6 Gbps	—	—	160	—	—	200	—	—	250	ps
	t_{x Jitter}- True Differential I/O Standards	Total jitter for data rate, < 600 Mbps	—	—	0.1	—	—	0.12	—	—	0.15	UI
	t_DUTY ⁸⁶	TX output clock duty cycle for Differential I/O Standards	45	50	55	45	50	55	45	50	55	%
	t_{RISE &} & t_FALL ⁸³ ⁸⁷	True Differential I/O Standards	—	—	160	—	—	180	—	—	200	ps
	TCCS ⁸⁶ ⁸¹	True Differential I/O Standards	—	—	150	—	—	150	—	—	150	ps
Receiver	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 4 to 10 ⁸² ⁸³ ⁸⁴	150	—	1600	150	—	1434	150	—	1250	Mbps
	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 3 ⁸² ⁸³ ⁸⁴	150	—	1200	150	—	1076	150	—	938	Mbps
	f_HSDR (data rate) (without DPA) ⁸¹	SERDES factor J = 3 to 10	⁸⁴	—	⁸⁸	⁸⁴	—	⁸⁸	⁸⁴	—	⁸⁸	Mbps
		SERDES factor J = 2, uses DDR registers	⁸⁴	—	⁸⁵	⁸⁴	—	⁸⁵	⁸⁴	—	⁸⁵	Mbps
		SERDES factor J = 1, uses DDR registers	⁸⁴	—	⁸⁵	⁸⁴	—	⁸⁵	⁸⁴	—	⁸⁵	Mbps
DPA (FIFO mode)	DPA run length	—	—	—	10000	—	—	10000	—	—	10000	UI
DPA (soft CDR mode)	DPA run length	SGMII/GbE protocol	—	—	5	—	—	5	—	—	5	UI
DPA (soft CDR mode)	DPA run length	All other protocols	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—
Soft CDR mode	Soft-CDR ppm tolerance	—	—	—	300	—	—	300	—	—	300	± ppm
Non DPA mode	Sampling Window	—	—	—	300	—	—	300	—	—	300	ps

⁷⁷ This speed grade is applicable to V_CC = 0.95 V specifications.

⁷⁸ Preliminary, pending characterization.

⁷⁹ Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

⁸⁰ This is achieved by using the PHY clock network.

⁸¹ Requires package skew compensation with PCB trace length.

⁸² The F_max specification is based on the fast clock used for serial data. The interface F_max is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

⁸³ The V_CC and V_CCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.

⁸⁴ The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.

⁸⁵ The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (f_OUT) provided you can close the design timing and the signal integrity meets the interface requirements.

⁸⁶ Not applicable for DIVCLK = 1.

⁸⁷ This applies to default pre-emphasis and V_OD settings only.

⁸⁸ You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

DPA Lock Time Specifications

Figure 2. DPA Lock Time Specifications with DPA PLL Calibration Enabled

Table 48. DPA Lock Time Specifications for Intel^® Arria^® 10 Devices. The specifications are applicable to both extended and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition.
Standard	Training Pattern	Number of Data Transitions in One Repetition of the Training Pattern	Number of Repetitions per 256 Data Transitions ⁸⁹	Maximum Data Transition
SPI-4	00000000001111111111	2	128	640
Parallel Rapid I/O	00001111	2	128	640
Parallel Rapid I/O	10010000	4	64	640
Miscellaneous	10101010	8	32	640
Miscellaneous	01010101	8	32	640

⁸⁹ This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications

Figure 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps

Table 49. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps
Jitter Frequency (Hz)		Sinusoidal Jitter (UI)
F1	10,000	25.00
F2	17,565	25.00
F3	1,493,000	0.28
F4	50,000,000	0.28

Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps

Memory Standards Supported by the Hard Memory Controller

Table 50. Memory Standards Supported by the Hard Memory Controller for Intel^® Arria^® 10 Devices. This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Memory Standard	Rate Support	Ping Pong PHY Support	Maximum Frequency (MHz)
DDR4 SDRAM	Quarter rate	Yes	1,200
DDR3 SDRAM	Quarter rate	Yes	1,066
DDR3L SDRAM	Quarter rate	Yes	933
LPDDR3 SDRAM	Quarter rate	—	800

Memory Standards Supported by the Soft Memory Controller

Table 51. Memory Standards Supported by the Soft Memory Controller for Intel^® Arria^® 10 Devices. This table lists the overall capability of the soft memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Memory Standard	Rate Support	Maximum Frequency (MHz)
RLDRAM 3 ⁹⁰	Quarter rate	1,200
QDR IV SRAM⁹⁰	Quarter rate	1,066
QDR II SRAM	Half rate	633
QDR II+ SRAM	Half rate	633
QDR II+ Xtreme SRAM	Half rate	633

⁹⁰ Intel^® Arria^® 10 devices support this external memory interface using hard PHY with soft memory controller.

Memory Standards Supported by the HPS Hard Memory Controller

Table 52. Memory Standards Supported by the HPS Hard Memory Controller for Intel^® Arria^® 10 Devices. This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Memory Standard	Rate Support	Maximum Frequency (MHz)
DDR4 SDRAM	Half rate	1,200
DDR3 SDRAM	Half rate	1,066
DDR3L SDRAM	Half rate	933

DLL Range Specifications

Table 53. DLL Frequency Range Specifications for Intel^® Arria^® 10 Devices. Intel^® Arria^® 10 devices support memory interface frequencies lower than 600 MHz, although the reference clock that feeds the DLL must be at least 600 MHz. To support interfaces below 600 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range.
Parameter	Performance (for All Speed Grades)	Unit
DLL operating frequency range	600 – 1333	MHz

DQS Logic Block Specifications

Table 54. DQS Phase Shift Error Specifications for DLL-Delayed Clock (t_{DQS_PSERR}) for Intel^® Arria^® 10 Devices. This error specification is the absolute maximum and minimum error.
Symbol	Performance (for All Speed Grades)	Unit
t_{DQS_PSERR}	5	ps

Memory Output Clock Jitter Specifications

Table 55. Memory Output Clock Jitter Specifications for Intel^® Arria^® 10 Devices.
The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.

The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10^–12, equivalent to 14 sigma.
Protocol	Parameter	Symbol	Non-SmartVID			SmartVID (–3V Speed Grade)			Unit
Protocol	Parameter	Symbol	Data Rate (Mbps)	Min	Max	Data Rate (Mbps)	Min	Max	Unit
DDR3	Clock period jitter	t_JIT(per)	2,133	–40	40	1,600	–70	70	ps
	Cycle-to-cycle period jitter	t_JIT(cc)	2,133	–40	40	1,600	–70	70	ps
	Duty cycle jitter	t_JIT(duty)	2,133	–40	40	1,600	–100	100	ps
DDR4	Clock period jitter	t_JIT(per)	2,400	–40	40	1,600	–63	63	ps
	Cycle-to-cycle period jitter	t_JIT(cc)	2,400	–40	40	1,600	–63	63	ps
	Duty cycle jitter	t_JIT(duty)	2,400	–40	40	1,600	–100	100	ps

OCT Calibration Block Specifications

Table 56. OCT Calibration Block Specifications for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
OCTUSRCLK	Clock required by OCT calibration blocks	—	—	20	MHz
T_OCTCAL	Number of OCTUSRCLK clock cycles required for R_SOCT /R_T OCT calibration	> 2000	—	—	Cycles
T_OCTSHIFT	Number of OCTUSRCLK clock cycles required for OCT code to shift out	—	32	—	Cycles
T_{RS_RT}	Time required between the `dyn_term_ctrl` and `oe` signal transitions in a bidirectional I/O buffer to dynamically switch between R_S OCT and R_TOCT	—	2.5	—	ns

Figure 5. Timing Diagram for on oe and dyn_term_ctrl Signals

HPS Specifications

This section provides HPS specifications and timing for Intel^® Arria^® 10 devices.

If you are using the early I/O release configuration flow, you cannot initially use SmartVID to power your device. Instead, you can use a fixed power supply until after the FPGA is configured. When the FPGA is configured, you can then enable SmartVID.

HPS Reset Input Requirements

Table 57. HPS Reset Input Requirements for Intel^® Arria^® 10 Devices
Description	Min	Max	Unit
HPS cold reset pulse width	600	—	ns
HPS warm reset pulse width	600	—	ns
Cold reset deassertion to BSEL sampling, using `osc1_clk` ⁹¹	—	1000	`osc1_clk` cycles
Cold reset deassertion to BSEL sampling, using secure clock, without RAM clearing	—	100	μs
Cold reset deassertion to BSEL sampling, using secure clock, with RAM clearing	—	50	ms

⁹¹ osc1_clk is supplied from the HPS_CLK1 pin.

HPS Clock Performance

Table 58. Maximum HPS Clock Frequencies Across Device Speed Grades for Intel^® Arria^® 10 Devices
HPS Clock	Temperature Grade	V_{CCL_HPS} = 0.9 V (typical)			V_{CCL_HPS} = 0.95 V (typical) ⁹²			Unit
HPS Clock	Temperature Grade	–1 Speed Grade	–2 Speed Grade	–3 Speed Grade	–1 Speed Grade	–2 Speed Grade	–3 Speed Grade	Unit
mpu_base_clk	All	1,200	1,000	800	1,500	1,200	1,000	MHz
noc_base_clk	All	400	400	300	500	400	300	MHz
hmc_free_clk ⁹³	All	600	533	467	600	533	467	MHz

⁹² You must use 0.95 V V_{CCL_HPS} for CSEL values of 0x7 – 0xE.

⁹³ The hmc_free_clk is 1/2 of the SDRAM interface clock. For the external memory interface clock specifications, refer to the External Memory Interface Spec Estimator.

HPS PLL Specifications

HPS PLL Input Requirements

The HPS main PLL receives the clock signal from the HPS_CLK1 pin. For details on this pin, refer to the Intel^® Arria^® 10 GX, GT, and SX Device Family Pin Connection Guidelines.

Table 59. HPS PLL Input Requirements for Intel^® Arria^® 10 Devices
Description	Min	Typ	Max	Unit
Clock input range	10	—	50	MHz
Clock input jitter tolerance	—	—	2	%
Clock input duty cycle	45	50	55	%

HPS PLL Performance

Table 60. HPS PLL Performance for Intel^® Arria^® 10 Devices
Description	V_{CCL_HPS}	–1 Speed Grade		–2 Speed Grade		–3 Speed Grade		Unit
Description	V_{CCL_HPS}	Min	Max	Min	Max	Min	Max	Unit
HPS PLL VCO output	0.95 V	320	3,000	320	2,400	320	2,000	MHz
HPS PLL VCO output	0.90 V	320	2,400	320	2,000	320	1,600	MHz
h2f_user0_clk	—	—	400	—	400	—	400	MHz
h2f_user1_clk	—	—	400	—	400	—	400	MHz

HPS PLL Output Specifications

Table 61. HPS PLL Output Specifications for Intel^® Arria^® 10 Devices
Description	Min	Max	Max	Unit
Clock jitter tolerance	–2.5	—	2.5	%
Clock duty cycle	45	50	55	%
Clock rise time	350	—	1075	ps
Clock fall time	200	—	450	ps
HPS PLL lock time	—	—	3.6	ms

Quad SPI Flash Timing Characteristics

Table 62. Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel^® Arria^® 10 Devices. Note that the Intel^® Arria^® 10 HPS boot loader calibrates the input timing automatically.
Symbol	Description	Min	Typ	Max	Unit
T_{qspi_ref_clk}	QSPI_REF_CLK clock period	2.5	—	—	ns
T_clk	QSPI_CLK clock period	9.25	—	—	ns
T_dutycycle	QSPI_CLK duty cycle	45	50	55	%
T_dssfrst ⁹⁴	QSPI_SS asserted to first QSPI_CLK edge	3.6	—	5.25	ns
T_dsslst ⁹⁴	Last QSPI_CLK edge to QSPI_SS deasserted	–1	—	1	ns
T_do	QSPI_DATA output delay	0	—	2.6	ns
T_su	Input setup with respect to QSPI_CLK capture edge	6.5 – (R_delay × T_{qspi_ref_clk}) ⁹⁵	—	—	ns
T_h	Input hold with respect to QSPI_CLK capture edge	(R_delay + 1) × T_{qspi_ref_clk} ⁹⁵	—	—	ns
T_dssb2b ⁹⁴	Minimum delay of slave select deassertion between two back-to-back transfer	1	—	—	QSPI_CLK

Figure 6. Quad SPI Flash Serial Output Timing Diagram

Figure 7. Quad SPI Flash Serial Input Timing Diagram

⁹⁴ This delay is programmable in whole QSPI_REF_CLK increments using the delay register in the Quad SPI module.

⁹⁵ R_delay is programmable in whole QSPI_REF_CLK increments using the delay field in the rddatacap register in the Quad SPI module.

SPI Timing Characteristics

Table 63. SPI Master Timing Requirements for Intel^® Arria^® 10 Devices. You can adjust the input delay timing by programming the `rx_sample_dly` register.
Symbol	Description	Min	Typ	Max	Unit
T_clk	SPI_CLK clock period	16.67	—	—	ns
T_dutycycle	SPI_CLK duty cycle	45	50	55	%
T_dssfrst ⁹⁶	SPI_SS asserted to first SPI_CLK edge	1.5 × T_{SPI_CLK} – 2	—	—	ns
T_dsslst ⁹⁶	Last SPI_CLK edge to SPI_SS deasserted	T_{SPI_CLK} – 2	—	—	ns
T_dio	Master-out slave-in (MOSI) output delay	–1	—	1	ns
T_su ⁹⁷	Input setup in respect to SPI_CLK capture edge	16 – (`rx_sample_dly` × T_{spi_ref_clk}) ⁹⁸ ⁹⁹	—	—	ns
T_h ⁹⁷	Input hold in respect to SPI_CLK capture edge	0	—	—	ns
T_dssb2b	Minimum delay of slave select deassertion between two back-to-back transfers (frames)	1	—	—	SPI_CLK

Figure 8. SPI Master Output Timing Diagram

Figure 9. SPI Master Input Timing Diagram

Table 64. SPI Slave Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk	SPI_CLK clock period	20	—	—	ns
T_dutycycle	SPI_CLK duty cycle	45	50	55	%
T_s	SPI slave input setup time	5	—	—	ns
T_h	SPI slave input hold time	8	—	—	ns
T_suss	SPI_SS asserted to first SCLK_IN edge	5	—	—	ns
T_hss	Last SCLK_IN edge to SPI_SS deasserted	5	—	—	ns
T_d	Master-in slave-out (MISO) output delay	2 × T_{spi_ref_clk} + 5.3 ¹⁰⁰	—	3 × T_{spi_ref_clk} + 11.8 ¹⁰⁰	ns

Figure 10. SPI Slave Output Timing Diagram

Figure 11. SPI Slave Input Timing Diagram

⁹⁶ SPI_SS behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.

⁹⁷ The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.

⁹⁸ A rx_sample_dly value of 0 is an invalid setting.

⁹⁹ SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk.

¹⁰⁰ SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk.

SD/MMC Timing Characteristics

Table 65. Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel^® Arria^® 10 Devices. These timings apply to SD, MMC, and embedded MMC cards operating at 1.8 V and 3.0 V.
Symbol	Description	Min	Typ	Max	Unit
T_{sdmmc_cclk}	SDMMC_CCLK clock period (Identification mode)	—	2500	—	ns
	SDMMC_CCLK clock period (Standard SD mode)	—	40	—	ns
	SDMMC_CCLK clock period (High speed SD mode)	—	20	—	ns
T_dutycycle	SDMMC_CCLK duty cycle	45	50	55	%
T_su	SDMMC_CMD/SDMMC_D[7:0] input setup ¹⁰¹	7 – (`l4_mp_clk` × `smplsel`/2)	—	—	ns
T_h	SDMMC_CMD/SDMMC_D[7:0] input hold ¹⁰¹	–2.5 + (`l4_mp_clk` × `smplsel`/2)	—	—	ns
T_d	SDMMC_CMD/SDMMC_D[7:0] output delay ¹⁰²	–1 + (`l4_mp_clk` × `drvsel`/2) ¹⁰³	—	4 + (`l4_mp_clk` × `drvsel`/2) ¹⁰³	ns

Figure 12. SD/MMC Timing Diagram

¹⁰¹ When smplsel is set to 2 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the setup time is 2 ns and the hold time is 2.5 ns. The Boot ROM uses a smplsel setting of 0 and U-Boot can adjust this setting later in the boot process.

¹⁰² When drvsel is set to 3 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the output delay time is 6.5 to 11.5 ns. The Boot ROM uses a drvsel setting of 3 and the Intel^® Quartus^® Prime software can adjust this setting later in the boot process. drvsel set to 0 is not a valid setting.

¹⁰³ l4_mp_clk is the SD/MMC controller reference clock.

USB ULPI Timing Characteristics

Table 66. USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk	USB_CLK clock period	—	16.667	—	ns
T_d ¹⁰⁴	Clock to USB_STP/USB_DATA[7:0] output delay	1.5	—	8	ns
T_su	Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]	2	—	—	ns
T_h	Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]	1	—	—	ns

Figure 13. USB ULPI Timing Diagram

¹⁰⁴ For the maximum trace length, refer to the Intel^® Arria^® 10 SoC Device Design Guidelines.

Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 67. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk (1000Base-T)	TX_CLK clock period	—	8	—	ns
T_clk (100Base-T)	TX_CLK clock period	—	40	—	ns
T_clk (10Base-T)	TX_CLK clock period	—	400	—	ns
T_dutycycle	TX_CLK duty cycle	45	50	55	%
T_d ¹⁰⁵	TX_CLK to TXD/TX_CTL output data delay	–0.5	—	0.5	ns

Figure 14. RGMII TX Timing Diagram

Table 68. RGMII RX Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk (1000Base-T)	RX_CLK clock period	—	8	—	ns
T_clk (100Base-T)	RX_CLK clock period	—	40	—	ns
T_clk (10Base-T)	RX_CLK clock period	—	400	—	ns
T_su	RX_D/RX_CTL setup time	1	—	—	ns
T_h ¹⁰⁶	RX_D/RX_CTL hold time	1	—	—	ns

Figure 15. RGMII RX Timing Diagram

Table 69. Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk (100Base-T)	TX_CLK clock period	—	20	—	ns
T_clk (10Base-T)	TX_CLK clock period	—	20	—	ns
T_dutycycle	Clock duty cycle, internal clock source	35	50	65	%
T_dutycycle	Clock duty cycle, external clock source	35	50	65	%

Table 70. RMII TX Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_d	TX_CLK to TXD/TX_CTL output data delay	7	—	10	ns

Table 71. RMII RX Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_su	RX_D/RX_CTL setup time	1	—	—	ns
T_h	RX_D/RX_CTL hold time	0.4	—	—	ns

Table 72. Management Data Input/Output (MDIO) Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk	MDC clock period	—	400	—	ns
T_d	MDC to MDIO output data delay	10.2	—	20	ns
T_su	Setup time for MDIO data	10	—	—	ns
T_h	Hold time for MDIO data	10	—	—	ns

Figure 16. MDIO Timing Diagram

¹⁰⁵ Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.

¹⁰⁶ For more information, refer to the Intel^® Arria^® 10 SoC Device Design Guidelines.

I2C Timing Characteristics

Table 73. I²C Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Standard Mode		Fast Mode		Unit
Symbol	Description	Min	Max	Min	Max	Unit
T_clk	Serial clock (SCL) clock period	10	—	2.5	—	μs
t_HIGH ¹⁰⁷	SCL high period	4 ¹⁰⁸	—	0.6 ¹⁰⁹	—	μs
t_LOW ¹¹⁰	SCL low period	4.7 ¹¹¹	—	1.3 ¹¹²	—	μs
t_SU;DAT	Setup time for serial data line (SDA) data to SCL	0.25	—	0.1	—	μs
t_HD;DAT ¹¹³	Hold time for SCL to SDA data	0	3.15	0	0.6	μs
t_VD;DAT and t_VD;ACK ¹¹⁴	SCL to SDA output data delay	—	3.45 ¹¹⁵	—	0.9 ¹¹⁶	μs
t_SU;STA	Setup time for a repeated start condition	4.7	—	0.6	—	μs
t_HD;STA	Hold time for a repeated start condition	4	—	0.6	—	μs
t_SU;STO	Setup time for a stop condition	4	—	0.6	—	μs
t_BUF	SDA high pulse duration between STOP and START	4.7	—	1.3	—	μs
t_r ¹¹⁷	SCL rise time	—	1000	20	300	ns
t_f ¹¹⁷	SCL fall time	—	300	20 × (V_dd / 5.5) ¹¹⁸	300	ns
t_r ¹¹⁷	SDA rise time	—	1000	20	300	ns
t_f ¹¹⁷	SDA fall time	—	300	20 × (V_dd / 5.5) ¹¹⁸	300	ns

Figure 17. I²C Timing Diagram

¹⁰⁷ You can adjust T_clkhigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.

¹⁰⁸ The recommended minimum setting for ic_ss_scl_hcnt is 440.

¹⁰⁹ The recommended minimum setting for ic_fs_scl_hcnt is 71.

¹¹⁰ You can adjust T_clklow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.

¹¹¹ The recommended minimum setting for ic_ss_scl_lcnt is 500.

¹¹² The recommended minimum setting for ic_fs_scl_lcnt is 141.

¹¹³ T_HD;DAT is affected by the rise and fall time.

¹¹⁴ t_VD;DAT and t_VD;ACK is affected by the rise and fall time, in addition to the SDA hold time that is set by adjusting the ic_sda_hold register.

¹¹⁵ Use maximum SDA_HOLD = 240 to be within the specification.

¹¹⁶ Use maximum SDA_HOLD = 60 to be within the specification.

¹¹⁷ Rise and fall time parameters vary depending on the external factors such as: characteristics of IO driver, pull-out resistor value, and total capacitance on the transmission line.

¹¹⁸ V_dd is the I²C bus voltage.

NAND Timing Characteristics

Table 74. NAND ONFI 1.0 Timing Requirements for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Max	Unit
t_WP ¹¹⁹	Write enable pulse width	10	—	ns
t_WH ¹¹⁹	Write enable hold time	7	—	ns
t_RP ¹¹⁹	Read enable pulse width	10	—	ns
t_REH ¹¹⁹	Read enable hold time	7	—	ns
t_CLS ¹¹⁹	Command latch enable to write enable setup time	10	—	ns
t_CLH ¹¹⁹	Command latch enable to write enable hold time	5	—	ns
t_CS ¹¹⁹	Chip enable to write enable setup time	15	—	ns
t_CH ¹¹⁹	Chip enable to write enable hold time	5	—	ns
t_ALS ¹¹⁹	Address latch enable to write enable setup time	10	—	ns
t_ALH ¹¹⁹	Address latch enable to write enable hold time	5	—	ns
t_DS ¹¹⁹	Data to write enable setup time	7	—	ns
t_DH ¹¹⁹	Data to write enable hold time	5	—	ns
t_CEA	Chip enable to data access time	—	100	ns
t_REA	Read enable to data access time	—	40	ns
t_RHZ	Read enable to data high impedance	—	200	ns
t_RR	Ready to read enable low	20	—	ns
t_WB ¹¹⁹	Write enable high to R/B low	—	200	ns

Figure 18. NAND Command Latch Timing Diagram

Figure 19. NAND Address Latch Timing Diagram

Figure 20. NAND Data Output Cycle Timing Diagram

Figure 21. NAND Data Input Cycle Timing Diagram

Figure 22. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle

Figure 23. NAND Read Status Timing Diagram

Figure 24. NAND Read Status Enhanced Timing Diagram

¹¹⁹ This timing is software programmable.

Trace Timing Characteristics

Table 75. Trace Timing Requirements for Intel^® Arria^® 10 Devices.
To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer (Standard) component. The FPGA trace interface offers a 32-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module datasheet for termination recommendations.
Symbol	Description	Min	Typ	Max	Unit
T_clk	CLK clock period	10	—	—	ns
T_dutycycle	CLK maximum duty cycle	45	50	55	%
T_d	CLK to D0–D3 output data delay	–0.5	—	1	ns

Figure 25. Trace Timing Diagram

GPIO Interface

The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is one debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 µs (at 32 kHz). Any pulses shorter than two debounce clock cycles are filtered by the GPIO peripheral.

If the external signal is less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal will not be filtered.

To ensure that the external signal is correctly debounced, set the debounce clock low enough so that by the time two debounce clock periods have passed, the signal has settled.

Configuration Specifications

This section provides configuration specifications and timing for Intel^® Arria^® 10 devices.

POR Specifications

Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.

Table 76. Fast and Standard POR Delay Specification for Intel^® Arria^® 10 Devices
POR Delay	Minimum	Maximum	Unit
Fast	4	12 ¹²⁰	ms
Standard	100	300	ms

¹²⁰ The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe^® hard IP to initialize after the POR trip.

JTAG Configuration Timing

Table 77. JTAG Timing Parameters and Values for Intel^® Arria^® 10 Devices
Symbol	Description	Min	Max	Unit
t_JCP	`TCK` clock period	30, 167 ¹²¹	—	ns
t_JCH	`TCK` clock high time	14	—	ns
t_JCL	`TCK` clock low time	14	—	ns
t_{JPSU (TDI)}	`TDI` JTAG port setup time	2	—	ns
t_{JPSU (TMS)}	`TMS` JTAG port setup time	3	—	ns
t_JPH	JTAG port hold time	5	—	ns
t_JPCO	JTAG port clock to output	—	11	ns
t_JPZX	JTAG port high impedance to valid output	—	14	ns
t_JPXZ	JTAG port valid output to high impedance	—	14	ns

¹²¹ The minimum TCK clock period is 167 ns if V_CCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.

FPP Configuration Timing

DCLK-to-DATA[] Ratio (r) for FPP Configuration

Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.

Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.

Table 78. DCLK-to-DATA[] Ratio for Intel^® Arria^® 10 Devices. You cannot turn on encryption and compression at the same time for Intel^® Arria^® 10 devices.
Configuration Scheme	Encryption	Compression	DCLK-to-DATA[] Ratio (r)
FPP (8-bit wide)	Off	Off	1
	On	Off	1
	Off	On	2
FPP (16-bit wide)	Off	Off	1
	On	Off	2
	Off	On	4
FPP (32-bit wide)	Off	Off	1
	On	Off	4
	Off	On	8

FPP Configuration Timing when DCLK-to-DATA[] = 1

Note: When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Intel^® Arria^® 10 Devices table.

Table 79. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel^® Arria^® 10 Devices. Use these timing parameters when the decompression and design security features are disabled.
Symbol	Parameter	Minimum	Maximum	Unit
t_CF2CD	`nCONFIG` low to `CONF_DONE` low	—	1,440	ns
t_CF2ST0	`nCONFIG` low to `nSTATUS` low	—	960	ns
t_CFG	`nCONFIG` low pulse width	2	—	μs
t_STATUS	`nSTATUS` low pulse width	268	3,000 ¹²²	μs
t_CF2ST1	`nCONFIG` high to `nSTATUS` high	—	3,000 ¹²³	μs
t_CF2CK ¹²⁴	`nCONFIG` high to first rising edge on `DCLK`	3,010	—	μs
t_ST2CK ¹²⁴	`nSTATUS` high to first rising edge of `DCLK`	10	—	μs
t_DSU	`DATA[]` setup time before rising edge on `DCLK`	5.5	—	ns
t_DH	`DATA[]` hold time after rising edge on `DCLK`	0	—	ns
t_CH	`DCLK` high time	0.45 × 1/f_MAX	—	s
t_CL	`DCLK` low time	0.45 × 1/f_MAX	—	s
t_CLK	`DCLK`period	1/f_MAX	—	s
f_MAX	`DCLK` frequency (FPP ×8/×16/×32)	—	100	MHz
t_CD2UM	`CONF_DONE` high to user mode ¹²⁵	175	830	μs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	t_CD2CU + (600 × `CLKUSR` period)	—	—

¹²² This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

¹²³ This value is applicable if you do not delay configuration by externally holding the nSTATUS low.

¹²⁴ If nSTATUS is monitored, follow the t_ST2CK specification. If nSTATUS is not monitored, follow the t_CF2CK specification.

¹²⁵ The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

FPP Configuration Timing when DCLK-to-DATA[] >1

Table 80. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel^® Arria^® 10 Devices. Use these timing parameters when you use the decompression and design security features.
Symbol	Parameter	Minimum	Maximum	Unit
t_CF2CD	`nCONFIG` low to `CONF_DONE` low	—	1,440	ns
t_CF2ST0	`nCONFIG` low to `nSTATUS` low	—	960	ns
t_CFG	`nCONFIG` low pulse width	2	—	μs
t_STATUS	`nSTATUS` low pulse width	268	3,000 ¹²⁶	μs
t_CF2ST1	`nCONFIG` high to `nSTATUS` high	—	3,000 ¹²⁶	μs
t_CF2CK ¹²⁷	`nCONFIG` high to first rising edge on `DCLK`	3,010	—	μs
t_ST2CK ¹²⁷	`nSTATUS` high to first rising edge of `DCLK`	10	—	μs
t_DSU	`DATA[]` setup time before rising edge on `DCLK`	5.5	—	ns
t_DH	`DATA[]` hold time after rising edge on `DCLK`	`N`–1/f_DCLK ¹²⁸	—	s
t_CH	`DCLK` high time	0.45 × 1/f_MAX	—	s
t_CL	`DCLK` low time	0.45 × 1/f_MAX	—	s
t_CLK	`DCLK` period	1/f_MAX	—	s
f_MAX	`DCLK` frequency (FPP ×8/×16/×32)	—	100	MHz
t_R	Input rise time	—	40	ns
t_F	Input fall time	—	40	ns
t_CD2UM	`CONF_DONE` high to user mode ¹²⁹	175	830	μs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	t_CD2CU + (600 × `CLKUSR` period)	—	—

¹²⁶ You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

¹²⁷ If nSTATUS is monitored, follow the t_ST2CK specification. If nSTATUS is not monitored, follow the t_CF2CK specification.

¹²⁸ N is the DCLK-to-DATA ratio and f_DCLK is the DCLK frequency the system is operating.

¹²⁹ The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.

AS Configuration Timing

Table 81. AS Timing Parameters for AS ×1 and AS ×4 Configurations in Intel^® Arria^® 10 Devices.
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.

The t_CF2CD, t_CF2ST0, t_CFG, t_STATUS, and t_CF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Intel^® Arria^® 10 Devices table.
Symbol	Parameter	Minimum	Maximum	Unit
t_CO	`DCLK` falling edge to `AS_DATA0`/`ASDO` output	—	2	ns
t_SU	Data setup time before falling edge on `DCLK`	1	—	ns
t_DH	Data hold time after falling edge on `DCLK`	1.5	—	ns
t_CD2UM	`CONF_DONE` high to user mode	175	830	μs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	t_CD2CU + (600 × `CLKUSR` period)	—	—

DCLK Frequency Specification in the AS Configuration Scheme

Table 82. DCLK Frequency Specification in the AS Configuration Scheme.
This table lists the internal clock frequency specification for the AS configuration scheme.

The `DCLK` frequency specification applies when you use the internal oscillator as the configuration clock source.

The AS multi-device configuration scheme does not support `DCLK` frequency of 100 MHz.

You can only set 12.5, 25, 50, and 100 MHz in the Intel^® Quartus^® Prime software.
Parameter	Minimum	Typical	Maximum	Intel^® Quartus^® Prime Software Settings	Unit
DCLK frequency in AS configuration scheme	5.3	7.5	9.7	12.5	MHz
	10.5	15.0	19.3	25.0	MHz
	21.0	30.0	38.5	50.0	MHz
	42.0	60.0	77.0	100.0	MHz

PS Configuration Timing

Table 83. PS Timing Parameters for Intel^® Arria^® 10 Devices
Symbol	Parameter	Minimum	Maximum	Unit
t_CF2CD	`nCONFIG` low to `CONF_DONE` low	—	1,440	ns
t_CF2ST0	`nCONFIG` low to `nSTATUS` low	—	960	ns
t_CFG	`nCONFIG` low pulse width	2	—	μs
t_STATUS	`nSTATUS` low pulse width	268	3,000 ¹³⁰	μs
t_CF2ST1	`nCONFIG` high to `nSTATUS` high	—	3,000 ¹³¹	μs
t_CF2CK ¹³²	`nCONFIG` high to first rising edge on `DCLK`	3,010	—	μs
t_ST2CK ¹³²	`nSTATUS` high to first rising edge of `DCLK`	10	—	μs
t_DSU	`DATA[]` setup time before rising edge on `DCLK`	5.5	—	ns
t_DH	`DATA[]` hold time after rising edge on `DCLK`	0	—	ns
t_CH	`DCLK` high time	0.45 × 1/f_MAX	—	s
t_CL	`DCLK` low time	0.45 × 1/f_MAX	—	s
t_CLK	`DCLK` period	1/f_MAX	—	s
f_MAX	`DCLK` frequency	—	125	MHz
t_CD2UM	`CONF_DONE` high to user mode ¹³³	175	830	μs
t_CD2CU	`CONF_DONE` high to `CLKUSR` enabled	4 × maximum `DCLK` period	—	—
t_CD2UMC	`CONF_DONE` high to user mode with `CLKUSR` option on	t_CD2CU + (600 × `CLKUSR` period)	—	—

¹³⁰ This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

¹³¹ This value is applicable if you do not delay configuration by externally holding the nSTATUS low.

¹³² If nSTATUS is monitored, follow the t_ST2CK specification. If nSTATUS is not monitored, follow the t_CF2CK specification.

¹³³ The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.

Initialization

Table 84. Initialization Clock Source Option and the Maximum Frequency for Intel^® Arria^® 10 Devices
Initialization Clock Source	Configuration Scheme	Maximum Frequency (MHz)	Number of Clock Cycles for Initialization
Internal Oscillator	AS, PS, and FPP	12.5	600
`CLKUSR` ¹³⁴ ¹³⁵	AS, PS, and FPP	100	600

¹³⁴ To enable CLKUSR as the initialization clock source, in the Intel^® Quartus^® Prime software, select Device and Pin Options > General > Device initialization clock source > CLKUSR pin.

¹³⁵ If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz.

Configuration Files

There are two types of configuration bit stream formats for different configuration schemes:

PS and FPP—Raw Binary File (.rbf)
AS—Raw Programming Data File (.rpd)

The .rpd file size follows the Intel configuration devices capacity. However, the actual configuration bit stream size for .rpd file is the same as .rbf file.

Table 85. Configuration Bit Stream Sizes for Intel^® Arria^® 10 Devices.
Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes.

For the different types of configuration file and file sizes, refer to the Intel^® Quartus^® Prime software. However, for a specific version of the Intel^® Quartus^® Prime software, any design targeted for the same device has the same uncompressed configuration file size.

I/O configuration shift register (IOCSR) is a long shift register that facilitates the device I/O peripheral settings. The IOCSR bit stream is part of the uncompressed configuration bit stream, and it is specifically for the Configuration via Protocol (CvP) feature.

Uncompressed configuration bit stream sizes are subject to change for improvements and optimizations in the configuration algorithm.
Variant	Product Line	Uncompressed Configuration Bit Stream Size (bits)	IOCSR Bit Stream Size (bits)	Recommended EPCQ-L Serial Configuration Device
Intel^® Arria^® 10 GX	GX 160	91,729,632	2,507,264	EPCQ-L256 or higher density
	GX 220	91,729,632	2,507,264	EPCQ-L256 or higher density
	GX 270	132,638,432	2,507,264	EPCQ-L256 or higher density
	GX 320	132,638,432	2,507,264	EPCQ-L256 or higher density
	GX 480	189,710,176	2,695,680	EPCQ-L256 or higher density
	GX 570	252,959,072	2,884,096	EPCQ-L256 or higher density
	GX 660	252,959,072	2,884,096	EPCQ-L256 or higher density
	GX 900	351,292,512	2,756,096	EPCQ-L512 or higher density
	GX 1150	351,292,512	2,756,096	EPCQ-L512 or higher density
Intel^® Arria^® 10 GT	GT 900	351,292,512	2,756,096	EPCQ-L512 or higher density
Intel^® Arria^® 10 GT	GT 1150	351,292,512	2,756,096	EPCQ-L512 or higher density
Intel^® Arria^® 10 SX	SX 160