Intel Arria 10 Device Datasheet
Intel Arria 10 Device Datasheet
Intel® Arria® 10 devices are offered in extended and industrial grades. Extended devices are offered in –E1 (fastest), –E2, and –E3 speed grades. Industrial grade devices are offered in the –I1, –I2, and –I3 speed grades.
The suffix after the speed grade denotes the power options offered in Intel® Arria® 10 devices.
- L—enables the device to operate at low static power while maintaining excellent performance.
- S—standard power specification.
- V—enables the device to run at lower than default VCC, reducing static and dynamic power while retaining equivalent performance.
- H—small device with high performance at the fastest speed grade (–1).
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel® Arria® 10 devices.
Operating Conditions
Intel® Arria® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel® Arria® 10 devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel® Arria® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
Symbol | Description | Condition | Minimum | Maximum | Unit |
---|---|---|---|---|---|
VCC | Core voltage power supply | — | –0.50 | 1.21 | V |
VCCP | Periphery circuitry and transceiver fabric interface power supply | — | –0.50 | 1.21 | V |
VCCERAM | Embedded memory power supply | — | –0.50 | 1.36 | V |
VCCPT | Power supply for programmable power technology and I/O pre-driver | — | –0.50 | 2.46 | V |
VCCBAT | Battery back-up power supply for design security volatile key register | — | –0.50 | 2.46 | V |
VCCPGM | Configuration pins power supply | 1 | –0.50 | 2.46 | V |
VCCIO | I/O buffers power supply | 3 V I/O | –0.50 | 4.10 | V |
LVDS I/O | –0.50 | 2.46 | V | ||
VCCA_PLL | Phase-locked loop (PLL) analog power supply | — | –0.50 | 2.46 | V |
VCCT_GXB | Transmitter power supply | — | –0.50 | 1.34 | V |
VCCR_GXB | Receiver power supply | — | –0.50 | 1.34 | V |
VCCH_GXB | Transceiver output buffer power supply | — | –0.50 | 2.46 | V |
VCCL_HPS | HPS core voltage and periphery circuitry power supply | — | –0.50 | 1.27 | V |
VCCIO_HPS | HPS I/O buffers power supply | 3 V I/O | –0.50 | 4.10 | V |
LVDS I/O | –0.50 | 2.46 | V | ||
VCCIOREF_HPS | HPS I/O pre-driver power supply | — | –0.50 | 2.46 | V |
VCCPLL_HPS | HPS PLL power supply | — | –0.50 | 2.46 | V |
IOUT | DC output current per pin | — | –25 2 3 4 5 6 | 25 | mA |
TJ | Operating junction temperature | — | –55 | 125 | °C |
TSTG | Storage temperature (no bias) | — | –65 | 150 | °C |
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.
Symbol | Description | Condition (V) | Overshoot Duration as % at TJ = 100°C | Unit | |
---|---|---|---|---|---|
LVDS I/O 7 | 3 V I/O | ||||
Vi (AC) | AC input voltage | 2.50 | 3.80 | 100 | % |
2.55 | 3.85 | 42 | % | ||
2.60 | 3.90 | 18 | % | ||
2.65 | 3.95 | 9 | % | ||
2.70 | 4.00 | 4 | % | ||
> 2.70 | > 4.00 | No overshoot allowed | % |
For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal.
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Intel® Arria® 10 devices.
Recommended Operating Conditions
Symbol | Description | Condition | Minimum 8 | Typical | Maximum 8 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage power supply | Standard and low power 9 | 0.87 | 0.9 | 0.93 | V |
0.92 | 0.95 | 0.98 | V | |||
SmartVID 10 | 0.82 | — | 0.93 | V | ||
VCCP | Periphery circuitry and transceiver fabric interface power supply | Standard and low power 9 | 0.87 | 0.9 | 0.93 | V |
0.92 | 0.95 | 0.98 | V | |||
SmartVID 10 | 0.82 | — | 0.93 | V | ||
VCCPGM | Configuration pins power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCERAM | Embedded memory power supply | 0.9 V 9 | 0.87 | 0.9 | 0.93 | V |
0.95 V 9 | 0.92 | 0.95 | 0.98 | V | ||
VCCBAT 11 | Battery back-up power supply (For design security volatile key register) | — | 1.14 | — | 1.89 | V |
VCCPT | Power supply for programmable power technology and I/O pre-driver | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO | I/O buffers power supply | 3.0 V (for 3 V I/O only) | 2.85 | 3.0 | 3.15 | V |
2.5 V (for 3 V I/O only) | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.35 V | 12 | 1.35 | 12 | V | ||
1.25 V | 1.19 | 1.25 | 1.31 | V | ||
1.2 V | 12 | 1.2 | 12 | V | ||
VCCA_PLL | PLL analog voltage regulator power supply | — | 1.71 | 1.8 | 1.89 | V |
VREFP_ADC | Precision voltage reference for voltage sensor | — | 1.2475 | 1.25 | 1.2525 | V |
VI 13 14 | DC input voltage | 3 V I/O | –0.3 | — | 3.3 | V |
LVDS I/O | –0.3 | — | 2.19 | V | ||
VO | Output voltage | — | 0 | — | VCCIO | V |
TJ | Operating junction temperature | Extended | 0 | — | 100 | °C |
Industrial | –40 | — | 100 | °C | ||
tRAMP 15 | Power supply ramp time | Standard POR | 200 µs | — | 100 ms | — |
Fast POR | 200 µs | — | 4 ms | — |
Transceiver Power Supply Operating Conditions
Symbol | Description | Condition 16 | Minimum 17 | Typical | Maximum 17 | Unit |
---|---|---|---|---|---|---|
VCCT_GXB [L1,R4] [C, D, E, F, G, H, I, J] 18 | Transmitter power supply | Chip-to-Chip ≤ 17.4 Gbps Or Backplane 19 ≤ 12.5 Gbps |
1.0 | 1.03 | 1.06 | V |
Chip-to-Chip ≤ 11.3 Gbps | 0.92 | 0.95 | 0.98 | V | ||
VCCR_GXB[L1,R4] [C, D, E, F, G, H, I, J] 18 | Receiver power supply | Chip-to-Chip ≤ 17.4 Gbps Or Backplane 19 ≤ 12.5 Gbps |
1.0 | 1.03 | 1.06 | V |
Chip-to-Chip ≤ 11.3 Gbps | 0.92 | 0.95 | 0.98 | V | ||
VCCH_GXB[L,R] | Transceiver output buffer power supply | — | 1.710 | 1.8 | 1.890 | V |
Symbol | Description | Condition 20 | Minimum 17 | Typical | Maximum 17 | Unit |
---|---|---|---|---|---|---|
VCCT_GXB[L,R] | Transmitter power supply | Chip-to-Chip ≤ 25.8 Gbps
21
Or Backplane 19 ≤ 12.5 Gbps |
1.10 | 1.12 | 1.14 | V |
Chip-to-Chip ≤ 15 Gbps Or Backplane 19 ≤ 12.5 Gbps |
1.0 | 1.03 | 1.06 | V | ||
Chip-to-Chip ≤ 11.3 Gbps | 0.92 | 0.95 | 0.98 | V | ||
VCCR_GXB[L,R] | Receiver power supply | Chip-to-Chip ≤ 25.8 Gbps Or Backplane 19 ≤ 12.5 Gbps |
1.10 | 1.12 | 1.14 | V |
Chip-to-Chip ≤ 15 Gbps Or Backplane 19 ≤ 12.5 Gbps |
1.0 | 1.03 | 1.06 | V | ||
Chip-to-Chip ≤ 11.3 Gbps | 0.92 | 0.95 | 0.98 | V | ||
VCCH_GXB[L,R] | Transceiver output buffer power supply | — | 1.710 | 1.8 | 1.890 | V |
HPS Power Supply Operating Conditions
Symbol | Description | Condition | Minimum 22 | Typical | Maximum 22 | Unit |
---|---|---|---|---|---|---|
VCCL_HPS | HPS core voltage and periphery circuitry power supply | 0.9 V 23 | 0.87 | 0.9 | 0.93 | V |
0.95 V 23 | 0.92 | 0.95 | 0.98 | V | ||
VCCIO_HPS | HPS I/O buffers power supply | 3.0 V | 2.85 | 3.0 | 3.15 | V |
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
VCCIOREF_HPS | HPS I/O pre-driver power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCPLL_HPS | HPS PLL analog voltage regulator power supply | — | 1.71 | 1.8 | 1.89 | V |
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel® Quartus® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
Symbol | Description | Condition | Min | Max | Unit |
---|---|---|---|---|---|
II | Input pin | VI = 0 V to VCCIOMAX | –80 | 80 | µA |
IOZ | Tri-stated I/O pin | VO = 0 V to VCCIOMAX | –80 | 80 | µA |
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC* standard.
Parameter | Symbol | Condition | VCCIO (V) | Unit | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.2 | 1.5 | 1.8 | 2.5 | 3.0 | |||||||||
Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | ||||
Bus-hold, low, sustaining current | ISUSL | VIN > VIL (max) | 8 24, 26 25 | — | 12 24, 32 25 | — | 30 24, 55 25 | — | 60 | — | 70 | — | µA |
Bus-hold, high, sustaining current | ISUSH | VIN < VIH (min) | –8 24, –26 25 | — | –12 24, –32 25 | — | –30 24, –55 25 | — | –60 | — | –70 | — | µA |
Bus-hold, low, overdrive current | IODL | 0 V < VIN < VCCIO | — | 125 | — | 175 | — | 200 | — | 300 | — | 500 | µA |
Bus-hold, high, overdrive current | IODH | 0 V < VIN < VCCIO | — | –125 | — | –175 | — | –200 | — | –300 | — | –500 | µA |
Bus-hold trip point | VTRIP | — | 0.3 | 0.9 | 0.38 | 1.13 | 0.68 | 1.07 | 0.70 | 1.7 | 0.8 | 2 | V |
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.
Symbol | Description | Condition (V) | Resistance Tolerance | Unit | ||
---|---|---|---|---|---|---|
–E1, –I1 | –E2, –I2 | –E3, –I3 | ||||
25-Ω and 50-Ω RS | Internal series termination with calibration (25-Ω and 50-Ω setting) | VCCIO = 1.8, 1.5, 1.2 | ± 15 | ± 15 | ± 15 | % |
34-Ω and 40-Ω RS | Internal series termination with calibration (34-Ω and 40-Ω setting) | VCCIO = 1.5, 1.25, 1.2 | ± 15 | ± 15 | ± 15 | % |
VCCIO = 1.35 | ± 20 | ± 20 | ± 20 | % | ||
48-Ω, 60-Ω, 80-Ω, and 120-Ω RS | Internal series termination with calibration (48-Ω, 60-Ω, 80-Ω, and 120-Ω setting) | VCCIO = 1.2 | ± 15 | ± 15 | ± 15 | % |
240-Ω RS | Internal series termination with calibration (240-Ω setting) | VCCIO = 1.2 | ± 20 | ± 20 | ± 20 | % |
30-Ω RT | Internal parallel termination with calibration (30-Ω setting) | VCCIO = 1.5, 1.35, 1.25 | –10 to +40 | –10 to +40 | –10 to +40 | % |
34-Ω, 48-Ω, 80-Ω, and 240-Ω RT | Internal parallel termination with calibration (34-Ω, 48-Ω, 80-Ω, and 240-Ω setting) | VCCIO = 1.2 | ± 15 | ± 15 | ± 15 | % |
40-Ω, 60-Ω, and 120-Ω RT | Internal parallel termination with calibration (40-Ω, 60-Ω, and 120-Ω setting) | VCCIO = 1.5, 1.35, 1.25, 1.2 | –10 to +40 | –10 to +40 | –10 to +40 | % |
VCCIO = 1.2 26 | ± 15 | ± 15 | ± 15 | % | ||
80-Ω RT | Internal parallel termination with calibration (80-Ω setting) | VCCIO = 1.2 | ± 15 | ± 15 | ± 15 | % |
OCT Without Calibration Resistance Tolerance Specifications
Symbol | Description | Condition (V) | Resistance Tolerance | Unit | ||
---|---|---|---|---|---|---|
–E1, –I1 | –E2, –I2 | –E3, –I3 | ||||
25-Ω and 50-Ω RS | Internal series termination without calibration (25-Ω and 50-Ω setting) | VCCIO = 3.0, 2.5 | –40 to +30 | ± 40 | ± 40 | % |
VCCIO = 1.8, 1.5, 1.2 | –50 to +30 | ± 50 | ± 50 | % | ||
34-Ω and 40-Ω RS | Internal series termination without calibration (34-Ω and 40-Ω setting) | VCCIO = 1.5, 1.35, 1.25, 1.2 | –50 to +30 | ± 50 | ± 50 | % |
48-Ω and 60-Ω RS | Internal series termination without calibration (48-Ω and 60-Ω setting) | VCCIO = 1.2 | –50 to +30 | ± 50 | ± 50 | % |
120-Ω Rs | Internal series termination without calibration (120-Ω setting) | VCCIO = 1.2 | –50 to +30 | ± 50 | ± 50 | % |
100-Ω RD | Internal differential termination (100-Ω setting) | VCCIO = 1.8 | ± 25 | ± 35 | ± 40 | % |
Pin Capacitance
Symbol | Description | Maximum | Unit |
---|---|---|---|
CIO_COLUMN | Input capacitance on column I/O pins | 2.5 | pF |
COUTFB | Input capacitance on dual-purpose clock output/feedback pins | 2.5 | pF |
Internal Weak Pull-Up and Weak Pull-Down Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the pins as described in the Internal Weak Pull-Down Resistor Values for Intel® Arria® 10 Devices table.
Symbol | Description | Condition (V) 27 | Value 28 | Unit |
---|---|---|---|---|
RPU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | VCCIO = 3.0 ±5% | 25 | kΩ |
VCCIO = 2.5 ±5% | 25 | kΩ | ||
VCCIO = 1.8 ±5% | 25 | kΩ | ||
VCCIO = 1.5 ±5% | 25 | kΩ | ||
VCCIO = 1.35 ±5% | 25 | kΩ | ||
VCCIO = 1.25 ±5% | 25 | kΩ | ||
VCCIO = 1.2 ±5% | 25 | kΩ |
Pin Name | Description | Condition (V) | Value 28 | Unit |
---|---|---|---|---|
nIO_PULLUP | Dedicated input pin that determines the internal pull-ups on user I/O pins and dual-purpose I/O pins. | VCC = 0.9 ±3.33% | 25 | kΩ |
TCK | Dedicated JTAG test clock input pin. | VCCPGM = 1.8 ±5 % | 25 | kΩ |
VCCPGM = 1.5 ±5% | 25 | kΩ | ||
VCCPGM = 1.2 ±5% | 25 | kΩ | ||
MSEL[0:2] | Configuration input pins that set the configuration scheme for the FPGA device. | VCCPGM = 1.8 ±5% | 25 | kΩ |
VCCPGM = 1.5 ±5% | 25 | kΩ | ||
VCCPGM = 1.2 ±5% | 25 | kΩ |
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel® Arria® 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Single-Ended I/O Standards Specifications
I/O Standard | VCCIO (V) | VIL (V) | VIH (V) | VOL (V) | VOH (V) | IOL 29 (mA) | IOH 29 (mA) | ||||
---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Max | Min | |||
3.0-V LVTTL | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.3 | 0.4 | 2.4 | 2 | –2 |
3.0-V LVCMOS | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.3 | 0.2 | VCCIO – 0.2 | 0.1 | –0.1 |
2.5 V | 2.375 | 2.5 | 2.625 | –0.3 | 0.7 | 1.7 | 3.3 | 0.4 | 2 | 1 | –1 |
1.8 V | 1.71 | 1.8 | 1.89 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.45 | VCCIO – 0.45 | 2 | –2 |
1.5 V | 1.425 | 1.5 | 1.575 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
1.2 V | 1.14 | 1.2 | 1.26 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
I/O Standard | VCCIO (V) | VREF (V) | VTT (V) | ||||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.833 | 0.9 | 0.969 | VREF – 0.04 | VREF | VREF + 0.04 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-135/ SSTL-135 Class I, II | 1.283 | 1.35 | 1.418 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-125/ SSTL-125 Class I, II | 1.19 | 1.25 | 1.31 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-12/ SSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.85 | 0.9 | 0.95 | — | VCCIO/2 | — |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.68 | 0.75 | 0.9 | — | VCCIO/2 | — |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.47 × VCCIO | 0.5 × VCCIO | 0.53 × VCCIO | — | VCCIO/2 | — |
HSUL-12 | 1.14 | 1.2 | 1.3 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | — | — | — |
POD12 | 1.16 | 1.2 | 1.24 | 0.69 × VCCIO | 0.7 × VCCIO | 0.71 × VCCIO | — | VCCIO | — |
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) | VOL (V) | VOH (V) | IOL 30 (mA) | IOH 30 (mA) | ||
---|---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Max | Min | Max | Min | |||
SSTL-18 Class I | –0.3 | VREF –0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | VTT – 0.603 | VTT + 0.603 | 6.7 | –6.7 |
SSTL-18 Class II | –0.3 | VREF –0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | 0.28 | VCCIO –0.28 | 13.4 | –13.4 |
SSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 8 | –8 |
SSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 16 | –16 |
SSTL-135/ SSTL-135 Class I, II | — | VREF – 0.09 | VREF + 0.09 | — | VREF – 0.16 | VREF + 0.16 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
SSTL-125/ SSTL-125 Class I, II | — | VREF – 0.09 | VREF + 0.09 | — | VREF – 0.15 | VREF + 0.15 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
SSTL-12/ SSTL-12 Class I, II | — | VREF – 0.10 | VREF + 0.10 | — | VREF – 0.15 | VREF + 0.15 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
HSTL-18 Class I | — | VREF –0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-18 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 16 | –16 |
HSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO –0.4 | 16 | –16 |
HSTL-12 Class I | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 8 | –8 |
HSTL-12 Class II | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 16 | –16 |
HSUL-12 | — | VREF – 0.13 | VREF + 0.13 | — | VREF – 0.22 | VREF + 0.22 | 0.1 × VCCIO | 0.9 × VCCIO | — | — |
POD12 | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | (0.7 – 0.15) × VCCIO | (0.7 + 0.15) × VCCIO | — | — |
Differential SSTL I/O Standards Specifications
I/O Standard | VCCIO (V) | VSWING(DC) (V) | VSWING(AC) (V) | VIX(AC) (V) | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.25 | VCCIO + 0.6 | 0.5 | VCCIO + 0.6 | VCCIO/2 – 0.175 | — | VCCIO/2 + 0.175 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | 31 | 2(VIH(AC) – VREF) | 2(VREF – VIL(AC)) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-135/ SSTL-135 Class I, II | 1.283 | 1.35 | 1.45 | 0.18 | 31 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | VCCIO/2 | VCCIO/2 + 0.15 |
SSTL-125/ SSTL-125 Class I, II | 1.19 | 1.25 | 1.31 | 0.18 | 31 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | VCCIO/2 | VCCIO/2 + 0.15 |
SSTL-12/ SSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.16 | 31 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VREF – 0.15 | VCCIO/2 | VREF + 0.15 |
POD12 | 1.16 | 1.2 | 1.24 | 0.16 | — | 0.3 | — | VREF – 0.08 | — | VREF + 0.08 |
Differential HSTL and HSUL I/O Standards Specifications
I/O Standard | VCCIO (V) | VDIF(DC) (V) | VDIF(AC) (V) | VIX(AC) (V) | VCM(DC) (V) | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.2 | — | 0.4 | — | 0.78 | — | 1.12 | 0.78 | — | 1.12 |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | — | 0.4 | — | 0.68 | — | 0.9 | 0.68 | — | 0.9 |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.16 | VCCIO + 0.3 | 0.3 | VCCIO + 0.48 | — | 0.5 × VCCIO | — | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO |
HSUL-12 | 1.14 | 1.2 | 1.3 | 2(VIH(DC) – VREF) | 2(VREF – VIH(DC)) | 2(VIH(AC) – VREF) | 2(VREF – VIH(AC)) | 0.5 × VCCIO – 0.12 | 0.5 × VCCIO | 0.5 × VCCIO +0.12 | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO |
Differential I/O Standards Specifications
I/O Standard | VCCIO (V) | VID (mV) 32 | VICM(DC) (V) | VOD (V) 33 | VOCM (V) 33 | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Condition | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
LVDS 34 | 1.71 | 1.8 | 1.89 | 100 | VCM = 1.25 V | — | 0 | DMAX ≤700 Mbps | 1.85 | 0.247 | — | 0.6 | 1.125 | 1.25 | 1.375 |
1 | DMAX >700 Mbps | 1.6 | |||||||||||||
RSDS (HIO) 35 | 1.71 | 1.8 | 1.89 | 100 | VCM = 1.25 V | — | 0.3 | — | 1.4 | 0.1 | 0.2 | 0.6 | 0.5 | 1.2 | 1.4 |
Mini-LVDS (HIO) 36 | 1.71 | 1.8 | 1.89 | 200 | — | 600 | 0.4 | — | 1.325 | 0.25 | — | 0.6 | 1 | 1.2 | 1.4 |
LVPECL 37 | 1.71 | 1.8 | 1.89 | 300 | — | — | 0.6 | DMAX ≤700 Mbps | 1.7 | — | — | — | — | — | — |
1 | DMAX >700 Mbps | 1.6 |
Switching Characteristics
This section provides the performance characteristics of Intel® Arria® 10 core and periphery blocks for extended grade devices.
Transceiver Performance Specifications
Transceiver Performance for Intel Arria 10 GX/SX Devices
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Transceiver Speed Grade 4 | Unit |
---|---|---|---|---|---|---|
Chip-to-Chip 38 | Maximum data
rate VCCR_GXB = VCCT_GXB = 1.03 V |
17.4 | 15 | 14.2 | 12.5 | Gbps |
Maximum data
rate VCCR_GXB = VCCT_GXB = 0.95 V |
11.3 | 11.3 | 11.3 | 11.3 | Gbps | |
Minimum Data Rate | 1.0 39 | Gbps | ||||
Backplane 38 | Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V |
12.5 | 12.5 | 12.5 | 10.3125 | Gbps |
Minimum Data Rate | 1.0 39 | Gbps |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Transceiver Speed Grade 4 | Unit |
---|---|---|---|---|---|---|
Supported Output Frequency | Maximum Frequency | 8.7 | 7.5 | 7.1 | 6.25 | GHz |
Minimum Frequency | 500 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Transceiver Speed Grade 4 | Unit |
---|---|---|---|---|---|---|
Supported Output Frequency | Maximum Frequency | 6.25 | 6.25 | 6.25 | 6.25 | GHz |
Minimum Frequency | 500 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Transceiver Speed Grade 4 | Unit |
---|---|---|---|---|---|---|
Supported Output Frequency | Maximum Frequency | 5.15625 | 5.15625 | 5.15625 | 5.15625 | GHz |
Minimum Frequency | 2450 | MHz |
High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GX/SX Devices
Symbol/Description | Condition (V) | Core Speed Grade with Power Options | Unit | ||
---|---|---|---|---|---|
-E1H | -E2 / -I2 | -E3 / -I3 | |||
20-bit interface - FIFO | VCC = 0.9/0.95 | 516 | 400 | 400 | MHz |
20-bit interface - Registered | VCC = 0.9/0.95 | 491 | 400 | 400 | MHz |
32-bit interface - FIFO | VCC = 0.9/0.95 | 441 | 404 | 335 | MHz |
32-bit interface - Registered | VCC = 0.9/0.95 | 441 | 404 | 335 | MHz |
64-bit interface - FIFO | VCC = 0.9/0.95 | 272 | 234 | 222 | MHz |
64-bit interface - Registered | VCC = 0.9/0.95 | 272 | 234 | 222 | MHz |
PCIe Gen3 HIP-Fabric interface | VCC = 0.9/0.95 | 300 | 250 | 125 | MHz |
Transceiver Performance for Intel Arria 10 GT Devices
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Unit | |
---|---|---|---|---|---|
Chip-to-chip 40 | Maximum data rate VCCR_GXB = VCCT_GXB = 1.12 V |
GT Channel 41 | 25.8 | 25.8 | Gbps |
GX Channel | 17.4 | 15 | Gbps | ||
Maximum
data rate VCCR_GXB = VCCT_GXB = 1.03 V |
GX Channel | 16 | 14.2 | Gbps | |
Maximum
data rate VCCR_GXB = VCCT_GXB = 0.95 V |
GX Channel | 11.3 | 11.3 | Gbps | |
Minimum data rate | GT Channel | 1.0 42 | Gbps | ||
GX Channel | |||||
Backplane 40 | Maximum data rate VCCR_GXB = VCCT_GXB = 1.12 V |
GX Channel | 12.5 | 12.5 | Gbps |
Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V |
GX Channel | 12.5 | 12.5 | Gbps | |
Minimum data rate | GX Channel | 1.0 42 | Gbps |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Unit |
---|---|---|---|---|
Supported Output Frequency | Maximum frequency | 12.9 | GHz | |
Minimum frequency | 500 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Unit |
---|---|---|---|---|
Supported Output Frequency | Maximum frequency | 6.25 | GHz | |
Minimum frequency | 500 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Unit |
---|---|---|---|---|
Supported Output Frequency | Maximum frequency | 5.15625 | GHz | |
Minimum frequency | 2450 | MHz |
High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GT Devices
Symbol/Description | Condition (V) | Core Speed Grade with Power Options | Unit | |
---|---|---|---|---|
-1 | -2 | |||
20-bit interface - FIFO | VCC = 0.9/0.95 | 400 | MHz | |
20-bit interface - Registered | VCC = 0.9/0.95 | 400 | MHz | |
32-bit interface - FIFO | VCC = 0.9/0.95 | 404 | MHz | |
32-bit interface - Registered | VCC = 0.9/0.95 | 404 | MHz | |
64-bit interface - FIFO | VCC = 0.9/0.95 | 407 | MHz | |
64-bit interface - Registered | VCC = 0.9/0.95 | 407 | MHz | |
PCIe Gen3 HIP-Fabric interface | VCC = 0.9/0.95 | 250 | MHz |
Transceiver Specifications for Intel Arria 10 GX, SX, and GT Devices
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | Dedicated reference clock pin | CML, Differential LVPECL, LVDS, and HCSL | |||
RX reference clock pin | CML, Differential LVPECL, and LVDS | ||||
Input Reference Clock Frequency (CMU PLL) |
61 | — | 800 | MHz | |
Input Reference Clock Frequency (ATX PLL) |
100 | — | 800 | MHz | |
Input Reference Clock Frequency (fPLL PLL) |
25 43 / 50 44 |
— | 800 | MHz | |
Rise time | 20% to 80% | — | — | 400 | ps |
Fall time | 80% to 20% | — | — | 400 | ps |
Duty cycle | — | 45 | — | 55 | % |
Spread-spectrum modulating clock frequency | PCIe | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe | — | 0 to –0.5 | — | % |
On-chip termination resistors | — | — | 100 | — | Ω |
Absolute VMAX | Dedicated reference clock pin | — | — | 1.6 | V |
RX reference clock pin | — | — | 1.2 | V | |
Absolute VMIN | — | –0.4 | — | — | V |
Peak-to-peak differential input voltage | — | 200 | — | 1600 | mV |
VICM (AC coupled) | VCCR_GXB = 0.95 V | — | 0.95 | — | V |
VCCR_GXB = 1.03 V | — | 1.03 | — | V | |
VCCR_GXB = 1.12 V | — | 1.12 | — | V | |
VICM (DC coupled) | HCSL I/O standard for PCIe reference clock | 250 | — | 550 | mV |
Transmitter REFCLK Phase Noise (622 MHz) 45 | 100 Hz | — | — | –70 | dBc/Hz |
1 kHz | — | — | –90 | dBc/Hz | |
10 kHz | — | — | –100 | dBc/Hz | |
100 kHz | — | — | –110 | dBc/Hz | |
≥ 1 MHz | — | — | –120 | dBc/Hz | |
Transmitter REFCLK Phase Jitter (100 MHz) | 1.5 MHz to 100 MHz (PCIe) | — | — | 4.2 | ps (rms) |
RREF | — | — | 2.0 k ±1% | — | Ω |
TSSC-MAX-PERIOD-SLEW | Max SSC df/dt | 0.75 |
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
CLKUSR pin for transceiver calibration | Transceiver Calibration | 100 | — | 125 | MHz |
reconfig_clk | Reconfiguration interface | 100 | — | 125 | MHz |
Clock Network | Maximum Performance 46 | Channel Span | Unit | ||
---|---|---|---|---|---|
ATX | fPLL | CMU | |||
x1 | 17.4 | 12.5 | 10.3125 | 6 channels in a single bank | Gbps |
x6 | 17.4 | 12.5 | N/A | 6 channels in a single bank | Gbps |
PLL feedback compensation mode | 17.4 | 12.5 | N/A | Side-wide | Gbps |
xN at 0.95 V VCCR_GXB/VCCT_GXB | 10.5 | 10.5 | N/A | Up two banks and down two banks 46 47 | Gbps |
xN at 1.03 V VCCR_GXB/VCCT_GXB | 15.0 | 12.5 | N/A | Up two banks and down two banks46 47 | Gbps |
xN at 1.12 V VCCR_GXB/VCCT_GXB | 16.0 | 12.5 | N/A | Up two banks and down two banks46 47 | Gbps |
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O, CML , Differential LVPECL , and LVDS 48 | |||
Absolute VMAX for a receiver pin 49 | — | — | — | 1.2 | V |
Absolute VMIN for a receiver pin 49 | — | -0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration | — | — | — | 1.6 | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration | VCCR_GXB = 1.12 V | — | — | 2.0 | V |
VCCR_GXB = 1.03 V | — | — | 2.0 | V | |
VCCR_GXB = 0.95 V | — | — | 2.4 | V | |
Minimum differential eye opening at receiver serial input pins 50 | — | 50 | — | — | mV |
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 30% | — | Ω |
100-Ω setting | — | 100 ± 30% | — | Ω | |
VICM (AC and DC coupled) 51 | VCM = 0.65 V | — | 600 | — | mV |
VCM = 0.7 V | — | 700 | — | mV | |
VCM = 0.75 V | — | 700 | — | mV | |
tLTR 52 | — | — | — | 10 | µs |
tLTD 53 | — | 4 | — | — | µs |
tLTD_manual 54 | — | 4 | — | — | µs |
tLTR_LTD_manual 55 | — | 15 | — | — | µs |
Run Length | — | — | — | 200 | UI |
CDR PPM tolerance | PCIe-only | -300 | — | 300 | PPM |
All other protocols | -1000 | — | 1000 | PPM | |
Programmable DC Gain | Setting = 0-4 | 0 | — | 10 | dB |
Programmable AC Gain at High Gain mode and Data Rate ≤ 6 Gbps with 0.95 V VCCR | Setting = 0-28 | 0 | — | 19 | dB |
Programmable AC Gain at High Gain mode and Data Rate ≤ 6 Gpbs with 1.03 V VCCR | Setting = 0-28 | 0 | — | 21 | dB |
Programmable AC Gain at High Gain mode and Data Rate ≤ 17.4 Gpbs with 1.03 V VCCR | Setting = 0-28 | 0 | — | 17 | dB |
Programmable AC Gain at High Data Rate mode | Setting = 0-15 | 0 | — | 8 | dB |
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O 56 | — | ||
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VOCM (AC coupled) | VCCT = 0.95 V | — | 450 | — | mV |
VCCT = 1.03 V | — | 500 | — | mV | |
VCCT = 1.12 V | — | 550 | — | mV | |
VOCM (DC coupled) | VCCT = 0.95 V | — | 450 | — | mV |
VCCT = 1.03 V | — | 500 | — | mV | |
VCCT = 1.12 V | — | 550 | — | mV | |
Rise time 57 | 20% to 80% | 20 | — | 130 | ps |
Fall time 57 | 80% to 20% | 20 | — | 130 | ps |
Intra-differential pair skew 58 | TX VCM = 0.5 V and slew rate setting of SLEW_R5 59 | — | — | 15 | ps |
Symbol | VOD Setting | VOD-to-VCCT Ratio |
---|---|---|
VOD differential value = VOD-to-VCCT ratio x VCCT | 31 | 1.00 |
30 | 0.97 | |
29 | 0.93 | |
28 | 0.90 | |
27 | 0.87 | |
26 | 0.83 | |
25 | 0.80 | |
24 | 0.77 | |
23 | 0.73 | |
22 | 0.70 | |
21 | 0.67 | |
20 | 0.63 | |
19 | 0.60 | |
18 | 0.57 | |
17 | 0.53 | |
16 | 0.50 | |
15 | 0.47 | |
14 | 0.43 | |
13 | 0.40 | |
12 | 0.37 |
Core Performance Specifications
Clock Tree Specifications
Parameter | Performance (All Speed Grades) | Unit |
---|---|---|
Global clock, regional clock, and small periphery clock | 644 | MHz |
Large periphery clock | 525 | MHz |
PLL Specifications
Fractional PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | — | 30 | — | 800 63 | MHz |
fINPFD | Input clock frequency to the phase frequency detector (PFD) | — | 30 | — | 700 | MHz |
fCASC_INPFD | Input clock frequency to the PFD of destination cascade PLL | — | 30 | — | 60 | MHz |
fVCO | PLL voltage-controlled oscillator (VCO) operating range | — | 6 | — | 14.025 | GHz |
tEINDUTY | Input clock duty cycle | — | 45 | — | 55 | % |
fOUT | Output frequency for internal global or regional clock | — | — | — | 644 | MHz |
fDYCONFIGCLK | Dynamic configuration clock for reconfig_clk | — | — | — | 100 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of pll_powerdown | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
fCLBW | PLL closed-loop bandwidth | — | 0.3 | — | 4 | MHz |
tPLL_PSERR | Accuracy of PLL phase shift | Non-SmartVID | — | — | 50 | ps |
SmartVID | — | — | 75 | ps | ||
tARESET | Minimum pulse width on the pll_powerdown signal | — | 10 | — | — | ns |
tINCCJ 64 65 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.13 | UI (p-p) |
FREF < 100 MHz | — | — | 650 | ps (p-p) | ||
tOUTPJ 66 | Period jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ 66 | Cycle-to-cycle jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | — | 32 | — | bit |
I/O PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | –1 speed grade | 10 | — | 800 67 | MHz |
–2 speed grade | 10 | — | 700 67 | MHz | ||
–3 speed grade | 10 | — | 650 67 | MHz | ||
fINPFD | Input clock frequency to the PFD | — | 10 | — | 325 | MHz |
fCASC_INPFD | Input clock frequency to the PFD of destination cascade PLL | — | 10 | — | 60 | MHz |
fVCO | PLL VCO operating range | –1 speed grade | 600 | — | 1600 | MHz |
–2 speed grade | 600 | — | 1434 | MHz | ||
–3 speed grade | 600 | — | 1250 | MHz | ||
fCLBW | PLL closed-loop bandwidth | — | 0.1 | — | 8 | MHz |
tEINDUTY | Input clock or external feedback clock input duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal global or regional clock (C counter) | –1, –2, –3 speed grade | — | — | 644 | MHz |
fOUT_EXT | Output frequency for external clock output | –1 speed grade | — | — | 800 | MHz |
–2 speed grade | — | — | 720 | MHz | ||
–3 speed grade | — | — | 650 | MHz | ||
tOUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | Non-SmartVID | 45 | 50 | 55 | % |
SmartVID | 42 | 50 | 58 | % | ||
tFCOMP | External feedback clock compensation time | — | — | — | 10 | ns |
fDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | — | 100 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ 68 69 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.15 | UI (p-p) |
FREF < 100 MHz | — | — | 750 | ps (p-p) | ||
tOUTPJ_DC | Period jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTCCJ_DC | Cycle-to-cycle jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTPJ_IO 70 | Period jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ_IO 70 | Cycle-to-cycle jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tCASC_OUTPJ_DC | Period jitter for dedicated clock output in cascaded PLLs | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) |
DSP Block Specifications
Mode | Performance | Unit | |||||
---|---|---|---|---|---|---|---|
–E1S, –E1H | –I1S, –I1H | –E2L, –E2S | –I2L, –I2S | –E3S, –E3V | –I3S, –I3V | ||
Fixed-point 18 × 19 multiplication mode | 548 | 528 | 456 | 438 | 364 | 346 | MHz |
Fixed-point 27 × 27 multiplication mode | 541 | 522 | 450 | 434 | 358 | 344 | MHz |
Fixed-point 18 × 18 multiplier adder mode | 548 | 529 | 459 | 440 | 370 | 351 | MHz |
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode | 539 | 517 | 444 | 422 | 349 | 326 | MHz |
Fixed-point 18 × 19 systolic mode | 548 | 529 | 459 | 440 | 370 | 351 | MHz |
Complex 18 × 19 multiplication mode | 548 | 528 | 456 | 438 | 364 | 346 | MHz |
Floating point multiplication mode | 548 | 527 | 447 | 427 | 347 | 326 | MHz |
Floating point adder or subtract mode | 488 | 471 | 388 | 369 | 288 | 266 | MHz |
Floating point multiplier adder or subtract mode | 483 | 465 | 386 | 368 | 290 | 270 | MHz |
Floating point multiplier accumulate mode | 510 | 490 | 418 | 393 | 326 | 294 | MHz |
Floating point vector one mode | 502 | 482 | 404 | 382 | 306 | 282 | MHz |
Floating point vector two mode | 474 | 455 | 383 | 367 | 293 | 278 | MHz |
Mode | Performance | Unit | |
---|---|---|---|
–I1S, –I1H | –I2L, –I2S | ||
Fixed-point 18 × 19 multiplication mode | 635 | 517 | MHz |
Fixed-point 27 × 27 multiplication mode | 633 | 517 | MHz |
Fixed-point 18 × 18 multiplier adder mode | 635 | 516 | MHz |
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode | 631 | 509 | MHz |
Fixed-point 18 × 19 systolic mode | 635 | 516 | MHz |
Complex 18 × 19 multiplication mode | 635 | 517 | MHz |
Floating point multiplication mode | 635 | 501 | MHz |
Floating point adder or subtract mode | 564 | 468 | MHz |
Floating point multiplier adder or subtract mode | 564 | 475 | MHz |
Floating point multiplier accumulate mode | 581 | 482 | MHz |
Floating point vector one mode | 574 | 471 | MHz |
Floating point vector two mode | 550 | 450 | MHz |
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Memory | Mode | Performance | |||||
---|---|---|---|---|---|---|---|
–E1S, –E1H | –I1S, –I1H | –E2L, –E2S, –I2L, –I2S | –E3S, –E3V | –I3S, –I3V | Unit | ||
MLAB | Single port, all supported widths (×16/×32) | 700 | 660 | 570 | 490 | 490 | MHz |
Simple dual-port, all supported widths (×16/×32) | 700 | 660 | 570 | 490 | 490 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 460 | 450 | 400 | 330 | 330 | MHz | |
ROM, all supported width (×16/×32) | 700 | 660 | 570 | 490 | 490 | MHz | |
M20K Block | Single-port, all supported widths | 730 | 690 | 625 | 530 | 510 | MHz |
Simple dual-port, all supported widths | 730 | 690 | 625 | 530 | 510 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 550 | 520 | 470 | 410 | 410 | MHz | |
Simple dual-port with ECC enabled, 512 × 32 | 470 | 450 | 410 | 360 | 360 | MHz | |
Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 | 620 | 590 | 520 | 470 | 470 | MHz | |
True dual port, all supported widths | 730 | 690 | 600 | 480 | 480 | MHz | |
ROM, all supported widths | 730 | 690 | 625 | 530 | 510 | MHz |
Memory | Mode | Performance | ||
---|---|---|---|---|
–I1S, –I1H | –I2L, –I2S | Unit | ||
MLAB | Single port, all supported widths (×16/×32) | 706 | 610 | MHz |
Simple dual-port, all supported widths (×16/×32) | 706 | 610 | MHz | |
Simple dual-port with read and write at the same address | 482 | 428 | MHz | |
ROM, all supported width (×16/×32) | 706 | 610 | MHz | |
M20K Block | Single-port, all supported widths | 735 | 670 | MHz |
Simple dual-port, all supported widths | 735 | 670 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 555 | 500 | MHz | |
Simple dual-port with ECC enabled, 512 × 32 | 480 | 440 | MHz | |
Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 | 630 | 555 | MHz | |
True dual port, all supported widths | 735 | 640 | MHz | |
ROM, all supported widths | 735 | 670 | MHz |
Temperature Sensing Diode Specifications
Internal Temperature Sensing Diode Specifications
Temperature Range | Accuracy | Offset Calibrated Option | Sampling Rate | Conversion Time | Resolution |
---|---|---|---|---|---|
–40 to 125°C | ±5°C | No | 1 MHz | < 5 ms | 10 bits |
External Temperature Sensing Diode Specifications
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Ibias, diode source current | 10 | — | 100 | μA |
Vbias, voltage across diode | 0.3 | — | 0.9 | V |
Series resistance | — | — | < 1 | Ω |
Diode ideality factor | — | 1.03 | — | — |
Internal Voltage Sensor Specifications
Parameter | Minimum | Typical | Maximum | Unit | |
---|---|---|---|---|---|
Resolution | — | — | 6 | Bit | |
Sampling rate | — | — | 500 | Ksps | |
Differential non-linearity (DNL) | — | — | ±1 | LSB | |
Integral non-linearity (INL) | — | — | ±1 | LSB | |
Gain error | — | — | ±1 | % | |
Offset error | — | — | ±1 | LSB | |
Input capacitance | — | 20 | — | pF | |
Clock frequency | 0.1 | — | 11 | MHz | |
Unipolar Input Mode | Input signal range for Vsigp | 0 | — | 1.5 | V |
Common mode voltage on Vsign | 0 | — | 0.25 | V | |
Input signal range for Vsigp – Vsign | 0 | — | 1.25 | V |
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Symbol | Condition | –E1S 71, –E1H, –I1S71, –I1H | –E2L, –E2S71, –I2L, –I2S71 | –E3L, –E3S71, –E3V, –I3L, –I3S71, –I3V | Unit | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK_in (input clock frequency) True Differential I/O Standards | Clock boost factor W = 1 to 40 72 | 10 | — | 800 | 10 | — | 700 | 10 | — | 625 | MHz | |
fHSCLK_in (input clock frequency) Single Ended I/O Standards | Clock boost factor W = 1 to 40 72 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) | — | — | — | 800 73 | — | — | 700 73 | — | — | 625 73 | MHz | |
Transmitter | True Differential I/O Standards - fHSDR (data rate) 74 | SERDES factor J = 4 to 10 75 76 77 | 77 | — | 1600 | 77 | — | 1434 | 77 | — | 1250 | Mbps |
SERDES factor J = 3 75 76 77 | 77 | — | 1200 | 77 | — | 1076 | 77 | — | 938 | Mbps | ||
SERDES factor J = 2, uses DDR registers | 77 | — | 333 78 | 77 | — | 275 78 | 77 | — | 250 78 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 77 | — | 333 78 | 77 | — | 275 78 | 77 | — | 250 78 | Mbps | ||
tx Jitter - True Differential I/O Standards | Total jitter for data rate, 600 Mbps – 1.6 Gbps | — | — | 160 | — | — | 200 | — | — | 250 | ps | |
Total jitter for data rate, < 600 Mbps | — | — | 0.1 | — | — | 0.12 | — | — | 0.15 | UI | ||
tDUTY 79 | TX output clock duty cycle for Differential I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE & & tFALL 76 80 | True Differential I/O Standards | — | — | 160 | — | — | 180 | — | — | 200 | ps | |
TCCS 79 74 | True Differential I/O Standards | — | — | 150 | — | — | 150 | — | — | 150 | ps | |
Receiver | True Differential I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 to 10 75 76 77 | 150 | — | 1600 | 150 | — | 1434 | 150 | — | 1250 | Mbps |
SERDES factor J = 3 75 76 77 | 150 | — | 1200 | 150 | — | 1076 | 150 | — | 938 | Mbps | ||
fHSDR (data rate) (without DPA) 74 | SERDES factor J = 3 to 10 | 77 | — | 81 | 77 | — | 81 | 77 | — | 81 | Mbps | |
SERDES factor J = 2, uses DDR registers | 77 | — | 78 | 77 | — | 78 | 77 | — | 78 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 77 | — | 78 | 77 | — | 78 | 77 | — | 78 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | 10000 | — | — | 10000 | — | — | 10000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | — | — | 300 | — | — | 300 | — | — | 300 | ± ppm |
Non DPA mode | Sampling Window | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
DPA Lock Time Specifications
Standard | Training Pattern | Number of Data Transitions in One Repetition of the Training Pattern | Number of Repetitions per 256 Data Transitions 82 | Maximum Data Transition |
---|---|---|---|---|
SPI-4 | 00000000001111111111 | 2 | 128 | 640 |
Parallel Rapid I/O | 00001111 | 2 | 128 | 640 |
10010000 | 4 | 64 | 640 | |
Miscellaneous | 10101010 | 8 | 32 | 640 |
01010101 | 8 | 32 | 640 |
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Jitter Frequency (Hz) | Sinusoidal Jitter (UI) | |
---|---|---|
F1 | 10,000 | 25.00 |
F2 | 17,565 | 25.00 |
F3 | 1,493,000 | 0.28 |
F4 | 50,000,000 | 0.28 |
Memory Standards Supported by the Hard Memory Controller
Memory Standard | Rate Support | Ping Pong PHY Support | Maximum Frequency (MHz) |
---|---|---|---|
DDR4 SDRAM | Quarter rate | Yes | 1,200 |
DDR3 SDRAM | Quarter rate | Yes | 1,066 |
DDR3L SDRAM | Quarter rate | Yes | 933 |
LPDDR3 SDRAM | Quarter rate | — | 800 |
Memory Standards Supported by the Soft Memory Controller
Memory Standard | Rate Support | Maximum Frequency (MHz) |
---|---|---|
RLDRAM 3 83 | Quarter rate | 1,200 |
QDR IV SRAM83 | Quarter rate | 1,066 |
QDR II SRAM | Half rate | 633 |
QDR II+ SRAM | Half rate | 633 |
QDR II+ Xtreme SRAM | Half rate | 633 |
Memory Standards Supported by the HPS Hard Memory Controller
Memory Standard | Rate Support | Maximum Frequency (MHz) |
---|---|---|
DDR4 SDRAM | Half rate | 1,200 |
DDR3 SDRAM | Half rate | 1,066 |
DDR3L SDRAM | Half rate | 933 |
DLL Range Specifications
Parameter | Performance (for All Speed Grades) | Unit |
---|---|---|
DLL operating frequency range | 600 – 1333 | MHz |
DQS Logic Block Specifications
Symbol | Performance (for All Speed Grades) | Unit |
---|---|---|
tDQS_PSERR | 5 | ps |
Memory Output Clock Jitter Specifications
Protocol | Parameter | Symbol | Non-SmartVID | SmartVID (–3V Speed Grade) | Unit | ||||
---|---|---|---|---|---|---|---|---|---|
Data Rate (Mbps) | Min | Max | Data Rate (Mbps) | Min | Max | ||||
DDR3 | Clock period jitter | tJIT(per) | 2,133 | –40 | 40 | 1,600 | –70 | 70 | ps |
Cycle-to-cycle period jitter | tJIT(cc) | 2,133 | –40 | 40 | 1,600 | –70 | 70 | ps | |
Duty cycle jitter | tJIT(duty) | 2,133 | –40 | 40 | 1,600 | –100 | 100 | ps | |
DDR4 | Clock period jitter | tJIT(per) | 2,400 | –40 | 40 | 1,600 | –63 | 63 | ps |
Cycle-to-cycle period jitter | tJIT(cc) | 2,400 | –40 | 40 | 1,600 | –63 | 63 | ps | |
Duty cycle jitter | tJIT(duty) | 2,400 | –40 | 40 | 1,600 | –100 | 100 | ps |
OCT Calibration Block Specifications
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
OCTUSRCLK | Clock required by OCT calibration blocks | — | — | 20 | MHz |
TOCTCAL | Number of OCTUSRCLK clock cycles required for RS OCT /RT OCT calibration | > 2000 | — | — | Cycles |
TOCTSHIFT | Number of OCTUSRCLK clock cycles required for OCT code to shift out | — | 32 | — | Cycles |
TRS_RT | Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT | — | 2.5 | — | ns |
HPS Specifications
This section provides HPS specifications and timing for Intel® Arria® 10 devices.
If you are using the early I/O release configuration flow, you cannot initially use SmartVID to power your device. Instead, you can use a fixed power supply until after the FPGA is configured. When the FPGA is configured, you can then enable SmartVID.
HPS Reset Input Requirements
Description | Min | Max | Unit |
---|---|---|---|
HPS cold reset pulse width | 600 | — | ns |
HPS warm reset pulse width | 600 | — | ns |
Cold reset deassertion to BSEL sampling, using osc1_clk 84 | — | 1000 | osc1_clk cycles |
Cold reset deassertion to BSEL sampling, using secure clock, without RAM clearing | — | 100 | μs |
Cold reset deassertion to BSEL sampling, using secure clock, with RAM clearing | — | 50 | ms |
HPS Clock Performance
HPS Clock | Temperature Grade | VCCL_HPS = 0.9 V (typical) | VCCL_HPS = 0.95 V (typical) 85 | Unit | ||||
---|---|---|---|---|---|---|---|---|
–1 Speed Grade | –2 Speed Grade | –3 Speed Grade | –1 Speed Grade | –2 Speed Grade | –3 Speed Grade | |||
mpu_base_clk | All | 1,200 | 1,000 | 800 | 1,500 | 1,200 | 1,000 | MHz |
noc_base_clk | All | 400 | 400 | 300 | 500 | 400 | 300 | MHz |
hmc_free_clk 86 | All | 600 | 533 | 467 | 600 | 533 | 467 | MHz |
HPS PLL Specifications
HPS PLL Input Requirements
The HPS main PLL receives the clock signal from the HPS_CLK1 pin. For details on this pin, refer to the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines.
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Clock input range | 10 | — | 50 | MHz |
Clock input jitter tolerance | — | — | 2 | % |
Clock input duty cycle | 45 | 50 | 55 | % |
HPS PLL Performance
Description | VCCL_HPS | –1 Speed Grade | –2 Speed Grade | –3 Speed Grade | Unit | |||
---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Min | Max | |||
HPS PLL VCO output | 0.95 V | 320 | 3,000 | 320 | 2,400 | 320 | 2,000 | MHz |
0.90 V | 320 | 2,400 | 320 | 2,000 | 320 | 1,600 | MHz | |
h2f_user0_clk | — | — | 400 | — | 400 | — | 400 | MHz |
h2f_user1_clk | — | — | 400 | — | 400 | — | 400 | MHz |
HPS PLL Output Specifications
Description | Min | Max | Max | Unit |
---|---|---|---|---|
Clock jitter tolerance | –2.5 | — | 2.5 | % |
Clock duty cycle | 45 | 50 | 55 | % |
Clock rise time | 350 | — | 1075 | ps |
Clock fall time | 200 | — | 450 | ps |
HPS PLL lock time | — | — | 3.6 | ms |
Quad SPI Flash Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tqspi_ref_clk | QSPI_REF_CLK clock period | 2.5 | — | — | ns |
Tclk | QSPI_CLK clock period | 9.25 | — | — | ns |
Tdutycycle | QSPI_CLK duty cycle | 45 | 50 | 55 | % |
Tdssfrst 87 | QSPI_SS asserted to first QSPI_CLK edge | 3.6 | — | 5.25 | ns |
Tdsslst 87 | Last QSPI_CLK edge to QSPI_SS deasserted | –1 | — | 1 | ns |
Tdo | QSPI_DATA output delay | 0 | — | 2.6 | ns |
Tsu | Input setup with respect to QSPI_CLK capture edge | 6.5 – (Rdelay × Tqspi_ref_clk) 88 | — | — | ns |
Th | Input hold with respect to QSPI_CLK capture edge | (Rdelay + 1) × Tqspi_ref_clk 88 | — | — | ns |
Tdssb2b 87 | Minimum delay of slave select deassertion between two back-to-back transfer | 1 | — | — | QSPI_CLK |
SPI Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | SPI_CLK clock period | 16.67 | — | — | ns |
Tdutycycle | SPI_CLK duty cycle | 45 | 50 | 55 | % |
Tdssfrst 89 | SPI_SS asserted to first SPI_CLK edge | 1.5 × TSPI_CLK – 2 | — | — | ns |
Tdsslst 89 | Last SPI_CLK edge to SPI_SS deasserted | TSPI_CLK – 2 | — | — | ns |
Tdio | Master-out slave-in (MOSI) output delay | –1 | — | 1 | ns |
Tsu 90 | Input setup in respect to SPI_CLK capture edge | 16 – (rx_sample_dly × Tspi_ref_clk) 91 92 | — | — | ns |
Th 90 | Input hold in respect to SPI_CLK capture edge | 0 | — | — | ns |
Tdssb2b | Minimum delay of slave select deassertion between two back-to-back transfers (frames) | 1 | — | — | SPI_CLK |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | SPI_CLK clock period | 20 | — | — | ns |
Tdutycycle | SPI_CLK duty cycle | 45 | 50 | 55 | % |
Ts | SPI slave input setup time | 5 | — | — | ns |
Th | SPI slave input hold time | 8 | — | — | ns |
Tsuss | SPI_SS asserted to first SCLK_IN edge | 5 | — | — | ns |
Thss | Last SCLK_IN edge to SPI_SS deasserted | 5 | — | — | ns |
Td | Master-in slave-out (MISO) output delay | 2 × Tspi_ref_clk + 5.3 93 | — | 3 × Tspi_ref_clk + 11.8 93 | ns |
SD/MMC Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsdmmc_cclk | SDMMC_CCLK clock period (Identification mode) | — | 2500 | — | ns |
SDMMC_CCLK clock period (Standard SD mode) | — | 40 | — | ns | |
SDMMC_CCLK clock period (High speed SD mode) | — | 20 | — | ns | |
Tdutycycle | SDMMC_CCLK duty cycle | 45 | 50 | 55 | % |
Tsu | SDMMC_CMD/SDMMC_D[7:0] input setup 94 | 7 – (l4_mp_clk × smplsel/2) | — | — | ns |
Th | SDMMC_CMD/SDMMC_D[7:0] input hold 94 | –2.5 + (l4_mp_clk × smplsel/2) | — | — | ns |
Td | SDMMC_CMD/SDMMC_D[7:0] output delay 95 | –1 + (l4_mp_clk × drvsel/2) 96 | — | 4 + (l4_mp_clk × drvsel/2) 96 | ns |
USB ULPI Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | USB_CLK clock period | — | 16.667 | — | ns |
Td 97 | Clock to USB_STP/USB_DATA[7:0] output delay | 1.5 | — | 8 | ns |
Tsu | Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] | 2 | — | — | ns |
Th | Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] | 1 | — | — | ns |
Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | TX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | TX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | TX_CLK clock period | — | 400 | — | ns |
Tdutycycle | TX_CLK duty cycle | 45 | 50 | 55 | % |
Td 98 | TX_CLK to TXD/TX_CTL output data delay | –0.5 | — | 0.5 | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | RX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | RX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | RX_CLK clock period | — | 400 | — | ns |
Tsu | RX_D/RX_CTL setup time | 1 | — | — | ns |
Th 99 | RX_D/RX_CTL hold time | 1 | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (100Base-T) | TX_CLK clock period | — | 20 | — | ns |
Tclk (10Base-T) | TX_CLK clock period | — | 20 | — | ns |
Tdutycycle | Clock duty cycle, internal clock source | 35 | 50 | 65 | % |
Tdutycycle | Clock duty cycle, external clock source | 35 | 50 | 65 | % |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Td | TX_CLK to TXD/TX_CTL output data delay | 7 | — | 10 | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsu | RX_D/RX_CTL setup time | 1 | — | — | ns |
Th | RX_D/RX_CTL hold time | 0.4 | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | MDC clock period | — | 400 | — | ns |
Td | MDC to MDIO output data delay | 10.2 | — | 20 | ns |
Tsu | Setup time for MDIO data | 10 | — | — | ns |
Th | Hold time for MDIO data | 0 | — | — | ns |
I2C Timing Characteristics
Symbol | Description | Standard Mode | Fast Mode | Unit | ||
---|---|---|---|---|---|---|
Min | Max | Min | Max | |||
Tclk | Serial clock (SCL) clock period | 10 | — | 2.5 | — | μs |
tHIGH 100 | SCL high period | 4 101 | — | 0.6 102 | — | μs |
tLOW 103 | SCL low period | 4.7 104 | — | 1.3 105 | — | μs |
tSU;DAT | Setup time for serial data line (SDA) data to SCL | 0.25 | — | 0.1 | — | μs |
tHD;DAT 106 | Hold time for SCL to SDA data | 0 | 3.15 | 0 | 0.6 | μs |
tVD;DAT and tVD;ACK 107 | SCL to SDA output data delay | — | 3.45 108 | — | 0.9 109 | μs |
tSU;STA | Setup time for a repeated start condition | 4.7 | — | 0.6 | — | μs |
tHD;STA | Hold time for a repeated start condition | 4 | — | 0.6 | — | μs |
tSU;STO | Setup time for a stop condition | 4 | — | 0.6 | — | μs |
tBUF | SDA high pulse duration between STOP and START | 4.7 | — | 1.3 | — | μs |
tr 110 | SCL rise time | — | 1000 | 20 | 300 | ns |
tf 110 | SCL fall time | — | 300 | 20 × (Vdd / 5.5) 111 | 300 | ns |
tr 110 | SDA rise time | — | 1000 | 20 | 300 | ns |
tf 110 | SDA fall time | — | 300 | 20 × (Vdd / 5.5) 111 | 300 | ns |
NAND Timing Characteristics
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
tWP 112 | Write enable pulse width | 10 | — | ns |
tWH 112 | Write enable hold time | 7 | — | ns |
tRP 112 | Read enable pulse width | 10 | — | ns |
tREH 112 | Read enable hold time | 7 | — | ns |
tCLS 112 | Command latch enable to write enable setup time | 10 | — | ns |
tCLH 112 | Command latch enable to write enable hold time | 5 | — | ns |
tCS 112 | Chip enable to write enable setup time | 15 | — | ns |
tCH 112 | Chip enable to write enable hold time | 5 | — | ns |
tALS 112 | Address latch enable to write enable setup time | 10 | — | ns |
tALH 112 | Address latch enable to write enable hold time | 5 | — | ns |
tDS 112 | Data to write enable setup time | 7 | — | ns |
tDH 112 | Data to write enable hold time | 5 | — | ns |
tCEA | Chip enable to data access time | — | 100 | ns |
tREA | Read enable to data access time | — | 40 | ns |
tRHZ | Read enable to data high impedance | — | 200 | ns |
tRR | Ready to read enable low | 20 | — | ns |
tWB 112 | Write enable high to R/B low | — | 200 | ns |
Trace Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | CLK clock period | 10 | — | — | ns |
Tdutycycle | CLK maximum duty cycle | 45 | 50 | 55 | % |
Td | CLK to D0–D3 output data delay | –0.5 | — | 1 | ns |
GPIO Interface
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is one debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 µs (at 32 kHz). Any pulses shorter than two debounce clock cycles are filtered by the GPIO peripheral.
If the external signal is less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal will not be filtered.
To ensure that the external signal is correctly debounced, set the debounce clock low enough so that by the time two debounce clock periods have passed, the signal has settled.
Configuration Specifications
This section provides configuration specifications and timing for Intel® Arria® 10 devices.
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.
POR Delay | Minimum | Maximum | Unit |
---|---|---|---|
Fast | 4 | 12 113 | ms |
Standard | 100 | 300 | ms |
JTAG Configuration Timing
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
tJCP | TCK clock period | 30, 167 114 | — | ns |
tJCH | TCK clock high time | 14 | — | ns |
tJCL | TCK clock low time | 14 | — | ns |
tJPSU (TDI) | TDI JTAG port setup time | 2 | — | ns |
tJPSU (TMS) | TMS JTAG port setup time | 3 | — | ns |
tJPH | JTAG port hold time | 5 | — | ns |
tJPCO | JTAG port clock to output | — | 11 | ns |
tJPZX | JTAG port high impedance to valid output | — | 14 | ns |
tJPXZ | JTAG port valid output to high impedance | — | 14 | ns |
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.
Configuration Scheme | Encryption | Compression | DCLK-to-DATA[] Ratio (r) |
---|---|---|---|
FPP (8-bit wide) | Off | Off | 1 |
On | Off | 1 | |
Off | On | 2 | |
FPP (16-bit wide) | Off | Off | 1 |
On | Off | 2 | |
Off | On | 4 | |
FPP (32-bit wide) | Off | Off | 1 |
On | Off | 4 | |
Off | On | 8 |
FPP Configuration Timing when DCLK-to-DATA[] = 1
Symbol | Parameter | Minimum | Maximum | Unit |
---|---|---|---|---|
tCF2CD | nCONFIG low to CONF_DONE low | — | 1,440 | ns |
tCF2ST0 | nCONFIG low to nSTATUS low | — | 960 | ns |
tCFG | nCONFIG low pulse width | 2 | — | μs |
tSTATUS | nSTATUS low pulse width | 268 | 3,000 115 | μs |
tCF2ST1 | nCONFIG high to nSTATUS high | — | 3,000 116 | μs |
tCF2CK 117 | nCONFIG high to first rising edge on DCLK | 3,010 | — | μs |
tST2CK 117 | nSTATUS high to first rising edge of DCLK | 10 | — | μs |
tDSU | DATA[] setup time before rising edge on DCLK | 5.5 | — | ns |
tDH | DATA[] hold time after rising edge on DCLK | 0 | — | ns |
tCH | DCLK high time | 0.45 × 1/fMAX | — | s |
tCL | DCLK low time | 0.45 × 1/fMAX | — | s |
tCLK | DCLK period | 1/fMAX | — | s |
fMAX | DCLK frequency (FPP ×8/×16/×32) | — | 100 | MHz |
tCD2UM | CONF_DONE high to user mode 118 | 175 | 830 | μs |
tCD2CU | CONF_DONE high to CLKUSR enabled | 4 × maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (600 × CLKUSR period) | — | — |
FPP Configuration Timing when DCLK-to-DATA[] >1
Symbol | Parameter | Minimum | Maximum | Unit |
---|---|---|---|---|
tCF2CD | nCONFIG low to CONF_DONE low | — | 1,440 | ns |
tCF2ST0 | nCONFIG low to nSTATUS low | — | 960 | ns |
tCFG | nCONFIG low pulse width | 2 | — | μs |
tSTATUS | nSTATUS low pulse width | 268 | 3,000 119 | μs |
tCF2ST1 | nCONFIG high to nSTATUS high | — | 3,000 119 | μs |
tCF2CK 120 | nCONFIG high to first rising edge on DCLK | 3,010 | — | μs |
tST2CK 120 | nSTATUS high to first rising edge of DCLK | 10 | — | μs |
tDSU | DATA[] setup time before rising edge on DCLK | 5.5 | — | ns |
tDH | DATA[] hold time after rising edge on DCLK | N–1/fDCLK 121 | — | s |
tCH | DCLK high time | 0.45 × 1/fMAX | — | s |
tCL | DCLK low time | 0.45 × 1/fMAX | — | s |
tCLK | DCLK period | 1/fMAX | — | s |
fMAX | DCLK frequency (FPP ×8/×16/×32) | — | 100 | MHz |
tCD2UM | CONF_DONE high to user mode 122 | 175 | 830 | μs |
tCD2CU | CONF_DONE high to CLKUSR enabled | 4 × maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (600 × CLKUSR period) | — | — |
AS Configuration Timing
Symbol | Parameter | Minimum | Maximum | Unit |
---|---|---|---|---|
tCO | DCLK falling edge to AS_DATA0/ASDO output | — | 2 | ns |
tSU | Data setup time before falling edge on DCLK | 1 | — | ns |
tDH | Data hold time after falling edge on DCLK | 1.5 | — | ns |
tCD2UM | CONF_DONE high to user mode | 175 | 830 | μs |
tCD2CU | CONF_DONE high to CLKUSR enabled | 4 × maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (600 × CLKUSR period) | — | — |
DCLK Frequency Specification in the AS Configuration Scheme
Parameter | Minimum | Typical | Maximum | Intel® Quartus® Prime Software Settings | Unit |
---|---|---|---|---|---|
DCLK frequency in AS configuration scheme | 5.3 | 7.5 | 9.7 | 12.5 | MHz |
10.5 | 15.0 | 19.3 | 25.0 | MHz | |
21.0 | 30.0 | 38.5 | 50.0 | MHz | |
42.0 | 60.0 | 77.0 | 100.0 | MHz |
PS Configuration Timing
Symbol | Parameter | Minimum | Maximum | Unit |
---|---|---|---|---|
tCF2CD | nCONFIG low to CONF_DONE low | — | 1,440 | ns |
tCF2ST0 | nCONFIG low to nSTATUS low | — | 960 | ns |
tCFG | nCONFIG low pulse width | 2 | — | μs |
tSTATUS | nSTATUS low pulse width | 268 | 3,000 123 | μs |
tCF2ST1 | nCONFIG high to nSTATUS high | — | 3,000 124 | μs |
tCF2CK 125 | nCONFIG high to first rising edge on DCLK | 3,010 | — | μs |
tST2CK 125 | nSTATUS high to first rising edge of DCLK | 10 | — | μs |
tDSU | DATA[] setup time before rising edge on DCLK | 5.5 | — | ns |
tDH | DATA[] hold time after rising edge on DCLK | 0 | — | ns |
tCH | DCLK high time | 0.45 × 1/fMAX | — | s |
tCL | DCLK low time | 0.45 × 1/fMAX | — | s |
tCLK | DCLK period | 1/fMAX | — | s |
fMAX | DCLK frequency | — | 125 | MHz |
tCD2UM | CONF_DONE high to user mode 126 | 175 | 830 | μs |
tCD2CU | CONF_DONE high to CLKUSR enabled | 4 × maximum DCLK period | — | — |
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (600 × CLKUSR period) | — | — |
Initialization
Configuration Files
There are two types of configuration bit stream formats for different configuration schemes:
- PS and FPP—Raw Binary File (.rbf)
- AS—Raw Programming Data File (.rpd)
The .rpd file size follows the Intel configuration devices capacity. However, the actual configuration bit stream size for .rpd file is the same as .rbf file.
Variant | Product Line | Uncompressed Configuration Bit Stream Size (bits) | IOCSR Bit Stream Size (bits) | Recommended EPCQ-L Serial Configuration Device |
---|---|---|---|---|
Intel® Arria® 10 GX | GX 160 | 91,729,632 | 2,507,264 | EPCQ-L256 or higher density |
GX 220 | 91,729,632 | 2,507,264 | EPCQ-L256 or higher density | |
GX 270 | 132,638,432 | 2,507,264 | EPCQ-L256 or higher density | |
GX 320 | 132,638,432 | 2,507,264 | EPCQ-L256 or higher density | |
GX 480 | 189,710,176 | 2,695,680 | EPCQ-L256 or higher density | |
GX 570 | 252,959,072 | 2,884,096 | EPCQ-L256 or higher density | |
GX 660 | 252,959,072 | 2,884,096 | EPCQ-L256 or higher density | |
GX 900 | 351,292,512 | 2,756,096 | EPCQ-L512 or higher density | |
GX 1150 | 351,292,512 | 2,756,096 | EPCQ-L512 or higher density | |
Intel® Arria® 10 GT | GT 900 | 351,292,512 | 2,756,096 | EPCQ-L512 or higher density |
GT 1150 | 351,292,512 | 2,756,096 | EPCQ-L512 or higher density | |
Intel® Arria® 10 SX | SX 160 | 91,729,632 | 2,507,264 | EPCQ-L256 or higher density |
SX 220 | 91,729,632 | 2,507,264 | EPCQ-L256 or higher density | |
SX 270 | 132,638,432 | 2,507,264 | EPCQ-L256 or higher density | |
SX 320 | 132,638,432 | 2,507,264 | EPCQ-L256 or higher density | |
SX 480 | 189,710,176 | 2,695,680 | EPCQ-L256 or higher density | |
SX 570 | 252,959,072 | 2,884,096 | EPCQ-L256 or higher density | |
SX 660 | 252,959,072 | 2,884,096 | EPCQ-L256 or higher density |