Intel MAX 10 FPGA Device Datasheet
Intel MAX 10 FPGA Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® MAX® 10 devices.
Device Grade | Speed Grade Supported |
---|---|
Commercial |
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Industrial |
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Automotive |
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Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel® MAX® 10 devices.
Operating Conditions
Intel® MAX® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel® MAX® 10 devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel® MAX® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
Single Supply Devices Absolute Maximum Ratings
Symbol | Parameter | Min | Max | Unit |
---|---|---|---|---|
VCC_ONE | Supply voltage for core and periphery through on-die voltage regulator | –0.5 | 3.9 | V |
VCCIO | Supply voltage for input and output buffers | –0.5 | 3.9 | V |
VCCA | Supply voltage for phase-locked loop (PLL) regulator and analog-to-digital converter (ADC) block (analog) | –0.5 | 3.9 | V |
Dual Supply Devices Absolute Maximum Ratings
Symbol | Parameter | Min | Max | Unit |
---|---|---|---|---|
VCC | Supply voltage for core and periphery | –0.5 | 1.63 | V |
VCCIO | Supply voltage for input and output buffers | –0.5 | 3.9 | V |
VCCA | Supply voltage for PLL regulator (analog) | –0.5 | 3.41 | V |
VCCD_PLL | Supply voltage for PLL regulator (digital) | –0.5 | 1.63 | V |
VCCA_ADC | Supply voltage for ADC analog block | –0.5 | 3.41 | V |
VCCINT | Supply voltage for ADC digital block | –0.5 | 1.63 | V |
Absolute Maximum Ratings
Symbol | Parameter | Min | Max | Unit |
---|---|---|---|---|
VI | DC input voltage | –0.5 | 4.12 | V |
IOUT | DC output current per pin | –25 | 25 | mA |
TSTG | Storage temperature | –65 | 150 | °C |
TJ | Operating junction temperature | –40 | 125 | °C |
Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 4.17 V can only be at 4.17 V for ~11.7% over the lifetime of the device; for a device lifetime of 11.4 years, this amounts to 1.33 years.
Condition (V) | Overshoot Duration as % of High Time | Unit |
---|---|---|
4.12 | 100.0 | % |
4.17 | 11.7 | % |
4.22 | 7.1 | % |
4.27 | 4.3 | % |
4.32 | 2.6 | % |
4.37 | 1.6 | % |
4.42 | 1.0 | % |
4.47 | 0.6 | % |
4.52 | 0.3 | % |
4.57 | 0.2 | % |
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Intel® MAX® 10 devices. The tables list the steady-state voltage values expected from Intel® MAX® 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Single Supply Devices Power Supplies Recommended Operating Conditions
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
VCC_ONE 1 | Supply voltage for core and periphery through on-die voltage regulator | — | 2.85/3.135 | 3.0/3.3 | 3.15/3.465 | V |
VCCIO 2 | Supply voltage for input and output buffers | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.35 V | 1.2825 | 1.35 | 1.4175 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
1.0 V | 0.95 | 1.0 | 1.05 | V | ||
VCCA 1 | Supply voltage for PLL regulator and ADC block (analog) | — | 2.85/3.135 | 3.0/3.3 | 3.15/3.465 | V |
Dual Supply Devices Power Supplies Recommended Operating Conditions
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
VCC | Supply voltage for core and periphery | — | 1.15 | 1.2 | 1.25 | V |
VCCIO 3 | Supply voltage for input and output buffers | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3 | 3.15 | V | ||
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.35 V | 1.2825 | 1.35 | 1.4175 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
1.0 V | 0.95 | 1.0 | 1.05 | V | ||
VCCA 4 | Supply voltage for PLL regulator (analog) | — | 2.375 | 2.5 | 2.625 | V |
VCCD_PLL 5 | Supply voltage for PLL regulator (digital) | — | 1.15 | 1.2 | 1.25 | V |
VCCA_ADC | Supply voltage for ADC analog block | — | 2.375 | 2.5 | 2.625 | V |
VCCINT | Supply voltage for ADC digital block | — | 1.15 | 1.2 | 1.25 | V |
Recommended Operating Conditions
Symbol | Parameter | Condition | Min | Max | Unit |
---|---|---|---|---|---|
VI | DC input voltage | — | –0.5 | 3.6 | V |
VO | Output voltage for I/O pins | — | 0 | VCCIO | V |
TJ | Operating junction temperature | Commercial | 0 | 85 | °C |
Industrial | –40 6 | 100 | °C | ||
Automotive | –406 | 125 | °C | ||
tRAMP | Power supply ramp time | — | 7 | 10 | ms |
IDiode | Magnitude of DC current across PCI* clamp diode when enabled | — | — | 10 | mA |
Programming/Erasure Specifications
Erase and reprogram cycles (E/P) 8 (Cycles/page) | Temperature (°C) | Data retention duration (Years) |
---|---|---|
10,000 | 85 | 20 |
10,000 | 100 | 10 |
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel® Quartus® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).
10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on.
Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable to all Intel® MAX® 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A.
Symbol | Parameter | Condition | Min | Max | Unit |
---|---|---|---|---|---|
II | Input pin leakage current | VI = 0 V to VCCIOMAX | –10 | 10 | µA |
IOZ | Tristated I/O pin leakage current | VO = 0 V to VCCIOMAX | –10 | 10 | µA |
Symbol | Parameter | Condition | Min | Max | Unit |
---|---|---|---|---|---|
Iadc_vref | ADC_VREF pin leakage current | Single supply mode | — | 10 | µA |
Dual supply mode | — | 20 | µA |
Bus Hold Parameters
Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.
Parameter | Condition | VCCIO (V) | Unit | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.2 | 1.5 | 1.8 | 2.5 | 3.0 | 3.3 | |||||||||
Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | |||
Bus-hold low, sustaining current | VIN > VIL (maximum) | 8 | — | 12 | — | 30 | — | 50 | — | 70 | — | 70 | — | µA |
Bus-hold high, sustaining current | VIN < VIH (minimum) | –8 | — | –12 | — | –30 | — | –50 | — | –70 | — | –70 | — | µA |
Bus-hold low, overdrive current | 0 V < VIN < VCCIO | — | 125 | — | 175 | — | 200 | — | 300 | — | 500 | — | 500 | µA |
Bus-hold high, overdrive current | 0 V < VIN < VCCIO | — | –125 | — | –175 | — | –200 | — | –300 | — | –500 | — | –500 | µA |
Bus-hold trip point | — | 0.3 | 0.9 | 0.375 | 1.125 | 0.68 | 1.07 | 0.7 | 1.7 | 0.8 | 2 | 0.8 | 2 | V |
Series OCT without Calibration Specifications
Description | VCCIO (V) | Resistance Tolerance | Unit | |
---|---|---|---|---|
–C7, –I6, –I7, –A6, –A7 | –C8 | |||
Series OCT without calibration | 3.00 | ±35 | ±30 | % |
2.50 | ±35 | ±30 | % | |
1.80 | ±40 | ±35 | % | |
1.50 | ±40 | ±40 | % | |
1.35 | ±40 | ±50 | % | |
1.20 | ±45 | ±60 | % |
Series OCT with Calibration at Device Power-Up Specifications
Description | VCCIO (V) | Calibration Accuracy | Unit |
---|---|---|---|
Series OCT with calibration at device power-up | 3.00 | ±12 | % |
2.50 | ±12 | % | |
1.80 | ±12 | % | |
1.50 | ±12 | % | |
1.35 | ±12 | % | |
1.20 | ±12 | % |
OCT Variation after Calibration at Device Power-Up
The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up.
Use the following table and equation to determine the final OCT resistance considering the variations after calibration at device power-up.
Description | Nominal Voltage | dR/dT (%/°C) | dR/dV (%/mV) |
---|---|---|---|
OCT variation after calibration at device power-up | 3.00 | 0.25 | –0.027 |
2.50 | 0.245 | –0.04 | |
1.80 | 0.242 | –0.079 | |
1.50 | 0.235 | –0.125 | |
1.35 | 0.229 | –0.16 | |
1.20 | 0.197 | –0.208 |
The definitions for equation are as follows:
- T1 is the initial temperature.
- T2 is the final temperature.
- MF is multiplication factor.
- Rinitial is initial resistance.
- Rfinal is final resistance.
- Subscript x refers to both V and T.
- ∆RV is variation of resistance with voltage.
- ∆RT is variation of resistance with temperature.
- dR/dT is the change percentage of resistance with temperature after calibration at device power-up.
- dR/dV is the change percentage of resistance with voltage after calibration at device power-up.
- V1 is the initial voltage.
- V2 is final voltage.
The following figure shows the example to calculate the change of 50 Ω I/O impedance from 25°C at 3.0 V to 85°C at 3.15 V.
Pin Capacitance
Symbol | Parameter | Maximum | Unit |
---|---|---|---|
CIOB | Input capacitance on bottom I/O pins | 8 | pF |
CIOLRT | Input capacitance on left/right/top I/O pins | 7 | pF |
CLVDSB | Input capacitance on bottom I/O pins with dedicated LVDS output 9 | 8 | pF |
CADCL | Input capacitance on left I/O pins with ADC input 10 | 9 | pF |
CVREFLRT | Input capacitance on left/right/top dual purpose VREF pin when used as VREF or user I/O pin 11 | 48 | pF |
CVREFB | Input capacitance on bottom dual purpose VREF pin when used as VREF or user I/O pin | 50 | pF |
CCLKB | Input capacitance on bottom dual purpose clock input pins 12 | 7 | pF |
CCLKLRT | Input capacitance on left/right/top dual purpose clock input pins 12 | 6 | pF |
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
R_PU | Value of I/O pin (dedicated and dual-purpose) pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled | VCCIO = 3.3 V ± 5% | 7 | 12 | 34 | kΩ |
VCCIO = 3.0 V ± 5% | 8 | 13 | 37 | kΩ | ||
VCCIO = 2.5 V ± 5% | 10 | 15 | 46 | kΩ | ||
VCCIO = 1.8 V ± 5% | 16 | 25 | 75 | kΩ | ||
VCCIO = 1.5 V ± 5% | 20 | 36 | 106 | kΩ | ||
VCCIO = 1.2 V ± 5% | 33 | 82 | 179 | kΩ |
Hot-Socketing Specifications
Symbol | Parameter | Maximum |
---|---|---|
IIOPIN(DC) | DC current per I/O pin | 300 µA |
IIOPIN(AC) | AC current per I/O pin | 8 mA 13 |
Hysteresis Specifications for Schmitt Trigger Input
Intel® MAX® 10 devices support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate.
Symbol | Parameter | Condition | Minimum | Unit |
---|---|---|---|---|
VHYS | Hysteresis for Schmitt trigger input | VCCIO = 3.3 V | 180 | mV |
VCCIO = 2.5 V | 150 | mV | ||
VCCIO = 1.8 V | 120 | mV | ||
VCCIO = 1.5 V | 110 | mV |
I/O Standards Specifications
Tables in this section list input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel® MAX® 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Single-Ended I/O Standards Specifications
I/O Standard | VCCIO (V) | VIL (V) | VIH (V) | VOL (V) | VOH (V) | IOL (mA) | IOH (mA) | ||||
---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Max | Min | |||
3.3 V LVTTL | 3.135 | 3.3 | 3.465 | –0.3 | 0.8 | 1.7 | 3.6 | 0.45 | 2.4 | 4 | –4 |
3.3 V LVCMOS | 3.135 | 3.3 | 3.465 | –0.3 | 0.8 | 1.7 | 3.6 | 0.2 | VCCIO – 0.2 | 2 | –2 |
3.0 V LVTTL | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | VCCIO + 0.3 | 0.45 | 2.4 | 4 | –4 |
3.0 V LVCMOS | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | VCCIO + 0.3 | 0.2 | VCCIO – 0.2 | 0.1 | –0.1 |
2.5 V LVTTL and LVCMOS | 2.375 | 2.5 | 2.625 | –0.3 | 0.7 | 1.7 | VCCIO + 0.3 | 0.4 | 2 | 1 | –1 |
1.8 V LVTTL and LVCMOS | 1.71 | 1.8 | 1.89 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | 2.25 | 0.45 | VCCIO –0.45 | 2 | –2 |
1.5 V LVCMOS | 1.425 | 1.5 | 1.575 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
1.2 V LVCMOS | 1.14 | 1.2 | 1.26 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
1.0 V LVCMOS 14 | 0.95 | 1.0 | 1.05 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 4 | –4 |
3.3 V Schmitt Trigger | 3.135 | 3.3 | 3.465 | –0.3 | 0.8 | 1.7 | VCCIO + 0.3 | — | — | — | — |
2.5 V Schmitt Trigger | 2.375 | 2.5 | 2.625 | –0.3 | 0.7 | 1.7 | VCCIO + 0.3 | — | — | — | — |
1.8 V Schmitt Trigger | 1.71 | 1.8 | 1.89 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | — | — | — | — |
1.5 V Schmitt Trigger | 1.425 | 1.5 | 1.575 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | — | — | — | — |
3.0 V PCI | 2.85 | 3 | 3.15 | — | 0.3 × VCCIO | 0.5 × VCCIO | VCCIO + 0.3 | 0.1 × VCCIO | 0.9 × VCCIO | 1.5 | –0.5 |
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
I/O Standard | VCCIO (V) | VREF (V) | VTT (V) 15 | ||||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |
SSTL-2 Class I, II | 2.375 | 2.5 | 2.625 | 1.19 | 1.25 | 1.31 | VREF – 0.04 | VREF | VREF + 0.04 |
SSTL-18 Class I, II | 1.7 | 1.8 | 1.9 | 0.833 | 0.9 | 0.969 | VREF – 0.04 | VREF | VREF + 0.04 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-135 Class I, II | 1.283 | 1.35 | 1.45 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.85 | 0.9 | 0.95 | 0.85 | 0.9 | 0.95 |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.71 | 0.75 | 0.79 | 0.71 | 0.75 | 0.79 |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.48 × VCCIO 16 | 0.5 × VCCIO 16 | 0.52 × VCCIO 16 | — | 0.5 × VCCIO | — |
0.47 × VCCIO 17 | 0.5 × VCCIO 17 | 0.53 × VCCIO 17 | |||||||
HSUL-12 | 1.14 | 1.2 | 1.3 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | — | — | — |
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) | VOL (V) | VOH (V) | IOL (mA) | IOH (mA) | ||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Min | Max | Min | Max | Max | Min | |||
SSTL-2 Class I | — | VREF – 0.18 | VREF + 0.18 | — | — | VREF – 0.31 | VREF + 0.31 | — | VTT – 0.57 | VTT + 0.57 | 8.1 | –8.1 |
SSTL-2 Class II | — | VREF – 0.18 | VREF + 0.18 | — | — | VREF – 0.31 | VREF + 0.31 | — | VTT – 0.76 | VTT + 0.76 | 16.4 | –16.4 |
SSTL-18 Class I | — | VREF – 0.125 | VREF + 0.125 | — | — | VREF – 0.25 | VREF + 0.25 | — | VTT –0.475 | VTT + 0.475 | 6.7 | –6.7 |
SSTL-18 Class II | — | VREF – 0.125 | VREF + 0.125 | — | — | VREF – 0.25 | VREF + 0.25 | — | 0.28 | VCCIO – 0.28 | 13.4 | –13.4 |
SSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | — | VREF – 0.175 | VREF + 0.175 | — | 0.2 × VCCIO | 0.8 × VCCIO | 8 | –8 |
SSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | — | VREF – 0.175 | VREF + 0.175 | — | 0.2 × VCCIO | 0.8 × VCCIO | 16 | –16 |
SSTL-135 | — | VREF – 0.09 | VREF + 0.09 | — | — | VREF – 0.16 | VREF + 0.16 | — | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
HSTL-18 Class I | — | VREF – 0.1 | VREF + 0.1 | — | — | VREF – 0.2 | VREF + 0.2 | — | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-18 Class II | — | VREF – 0.1 | VREF + 0.1 | — | — | VREF – 0.2 | VREF + 0.2 | — | 0.4 | VCCIO – 0.4 | 16 | –16 |
HSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | — | VREF – 0.2 | VREF + 0.2 | — | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | — | VREF – 0.2 | VREF + 0.2 | — | 0.4 | VCCIO – 0.4 | 16 | –16 |
HSTL-12 Class I | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | –0.24 | VREF – 0.15 | VREF + 0.15 | VCCIO + 0.24 | 0.25 × VCCIO | 0.75 × VCCIO | 8 | –8 |
HSTL-12 Class II | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | –0.24 | VREF – 0.15 | VREF + 0.15 | VCCIO + 0.24 | 0.25 × VCCIO | 0.75 × VCCIO | 14 | –14 |
HSUL-12 | — | VREF – 0.13 | VREF + 0.13 | — | — | VREF – 0.22 | VREF + 0.22 | — | 0.1 × VCCIO | 0.9 × VCCIO | — | — |
Differential SSTL I/O Standards Specifications
Differential SSTL requires a VREF input.
I/O Standard | VCCIO (V) | VSwing(DC) (V) | VX(AC) (V) | VSwing(AC) (V) | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max18 | Min | Typ | Max | Min | Max | |
SSTL-2 Class I, II | 2.375 | 2.5 | 2.625 | 0.36 | VCCIO | VCCIO/2 – 0.2 | — | VCCIO/2+ 0.2 | 0.7 | VCCIO |
SSTL-18 Class I, II | 1.7 | 1.8 | 1.9 | 0.25 | VCCIO | VCCIO/2 – 0.175 | — | VCCIO/2+ 0.175 | 0.5 | VCCIO |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | — | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) |
SSTL-135 | 1.283 | 1.35 | 1.45 | 0.18 | — | VREF – 0.135 | 0.5 × VCCIO | VREF + 0.135 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) |
Differential HSTL and HSUL I/O Standards Specifications
Differential HSTL requires a VREF input.
I/O Standard | VCCIO (V) | VDIF(DC) (V) | VX(AC) (V) | VCM(DC) (V) | VDIF(AC) (V) | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | Min | |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.2 | — | 0.85 | — | 0.95 | 0.85 | — | 0.95 | 0.4 |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | — | 0.71 | — | 0.79 | 0.71 | — | 0.79 | 0.4 |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.16 | VCCIO | 0.48 × VCCIO | 0.5 × VCCIO | 0.52 × VCCIO | 0.48 × VCCIO | 0.5 × VCCIO | 0.52 × VCCIO | 0.3 |
HSUL-12 | 1.14 | 1.2 | 1.3 | 0.26 | — | 0.5 × VCCIO – 0.12 | 0.5 × VCCIO | 0.5 × VCCIO + 0.12 | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO | 0.44 |
Differential I/O Standards Specifications
I/O Standard | VCCIO (V) | VID (mV) | VICM (V) 19 | VOD (mV) 20 21 | VOS (V) 20 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
LVPECL 22 | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | — | — | — | — | — | — |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 | ||||||||||||
LVDS | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | 247 | — | 600 | 1.125 | 1.25 | 1.375 |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 | ||||||||||||
BLVDS 23 | 2.375 | 2.5 | 2.625 | 100 | — | — | — | — | — | — | — | — | — | — |
mini-LVDS 24 | 2.375 | 2.5 | 2.625 | — | — | — | — | — | 300 | — | 600 | 1 | 1.2 | 1.4 |
RSDS 24 | 2.375 | 2.5 | 2.625 | — | — | — | — | — | 100 | 200 | 600 | 0.5 | 1.2 | 1.5 |
PPDS (Row I/Os) 24 | 2.375 | 2.5 | 2.625 | — | — | — | — | — | 100 | 200 | 600 | 0.5 | 1.2 | 1.4 |
TMDS25 | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | — | — | — | — | — | — |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 | ||||||||||||
Sub-LVDS 26 | 1.71 | 1.8 | 1.89 | 100 | — | 0.55 | — | 1.25 | 27 | 0.8 | 0.9 | 1 | ||
SLVS | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | — | 1.1 | 27 | 28 | ||||
HiSpi | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | — | — | — | — | — | — |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 |
Switching Characteristics
This section provides the performance characteristics of Intel® MAX® 10 core and periphery blocks.
Core Performance Specifications
Clock Tree Specifications
Device | Performance | Unit | ||||
---|---|---|---|---|---|---|
–I6 | –A6, –C7 | –I7 | –A7 | –C8 | ||
10M02 | 450 | 416 | 416 | 382 | 402 | MHz |
10M04 | 450 | 416 | 416 | 382 | 402 | MHz |
10M08 | 450 | 416 | 416 | 382 | 402 | MHz |
10M16 | 450 | 416 | 416 | 382 | 402 | MHz |
10M25 | 450 | 416 | 416 | 382 | 402 | MHz |
10M40 | 450 | 416 | 416 | 382 | 402 | MHz |
10M50 | 450 | 416 | 416 | 382 | 402 | MHz |
PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN 29 | Input clock frequency | — | 5 | — | 472.5 | MHz |
fINPFD | Phase frequency detector (PFD) input frequency | — | 5 | — | 325 | MHz |
fVCO 30 | PLL internal voltage-controlled oscillator (VCO) operating range | — | 600 | — | 1300 | MHz |
fINDUTY | Input clock duty cycle | — | 40 | — | 60 | % |
tINJITTER_CCJ 31 | Input clock cycle-to-cycle jitter | FINPFD ≥ 100 MHz | — | — | 0.15 | UI |
FINPFD < 100 MHz | — | — | ±750 | ps | ||
fOUT_EXT 29 | PLL output frequency for external clock output | — | — | — | 472.5 | MHz |
fOUT | PLL output frequency to global clock | –6 speed grade | — | — | 472.5 | MHz |
–7 speed grade | — | — | 450 | MHz | ||
–8 speed grade | — | — | 402.5 | MHz | ||
tOUTDUTY | Duty cycle for external clock output | Duty cycle set to 50% | 45 | 50 | 55 | % |
tLOCK | Time required to lock from end of device configuration | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically | After switchover, reconfiguring any non-post-scale counters or delays, or when areset is deasserted | — | — | 1 | ms |
tOUTJITTER_PERIOD_IO 32 | Regular I/O period jitter | FOUT ≥ 100 MHz | — | — | 650 | ps |
FOUT < 100 MHz | — | — | 75 | mUI | ||
tOUTJITTER_CCJ_IO 32 | Regular I/O cycle-to-cycle jitter | FOUT ≥ 100 MHz | — | — | 650 | ps |
FOUT < 100 MHz | — | — | 75 | mUI | ||
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on areset signal. | — | 10 | — | — | ns |
tCONFIGPLL | Time required to reconfigure scan chains for PLLs | — | — | 3.5 33 | — | SCANCLK cycles |
fSCANCLK | scanclk frequency | — | — | — | 100 | MHz |
Symbol | Parameter | Condition | Max | Unit |
---|---|---|---|---|
tOUTJITTER_PERIOD_DEDCLK 32 | Dedicated clock output period jitter | FOUT ≥ 100 MHz | 660 | ps |
FOUT < 100 MHz | 66 | mUI | ||
tOUTJITTER_CCJ_DEDCLK 32 | Dedicated clock output cycle-to-cycle jitter | FOUT ≥ 100 MHz | 660 | ps |
FOUT < 100 MHz | 66 | mUI |
Symbol | Parameter | Condition | Max | Unit |
---|---|---|---|---|
tOUTJITTER_PERIOD_DEDCLK 32 | Dedicated clock output period jitter | FOUT ≥ 100 MHz | 300 | ps |
FOUT < 100 MHz | 30 | mUI | ||
tOUTJITTER_CCJ_DEDCLK 32 | Dedicated clock output cycle-to-cycle jitter | FOUT ≥ 100 MHz | 300 | ps |
FOUT < 100 MHz | 30 | mUI |
Embedded Multiplier Specifications
Mode | Number of Multipliers | Power Supply Mode | Performance | Unit | ||
---|---|---|---|---|---|---|
–I6 | –A6, –C7, –I7, –A7 | –C8 | ||||
9 × 9-bit multiplier | 1 | Single supply mode | 198 | 183 | 160 | MHz |
Dual supply mode | 310 | 260 | 210 | MHz | ||
18 × 18-bit multiplier | 1 | Single supply mode | 198 | 183 | 160 | MHz |
Dual supply mode | 265 | 240 | 190 | MHz |
Memory Block Performance Specifications
Memory | Mode | Resources Used | Power Supply Mode | Performance | Unit | |||
---|---|---|---|---|---|---|---|---|
LEs | M9K Memory | –I6 | –A6, –C7, –I7, –A7 | –C8 | ||||
M9K Block | FIFO 256 × 36 | 47 | 1 | Single supply mode | 232 | 219 | 204 | MHz |
Dual supply mode | 330 | 300 | 250 | MHz | ||||
Single-port 256 × 36 | 0 | 1 | Single supply mode | 232 | 219 | 204 | MHz | |
Dual supply mode | 330 | 300 | 250 | MHz | ||||
Simple dual-port 256 × 36 CLK | 0 | 1 | Single supply mode | 232 | 219 | 204 | MHz | |
Dual supply mode | 330 | 300 | 250 | MHz | ||||
True dual port 512 × 18 single CLK | 0 | 1 | Single supply mode | 232 | 219 | 204 | MHz | |
Dual supply mode | 330 | 300 | 250 | MHz |
Internal Oscillator Specifications
Device | Frequency | Unit | ||
---|---|---|---|---|
Minimum | Typical | Maximum | ||
10M02 | 55 | 82 | 116 | MHz |
10M04 | ||||
10M08 | ||||
10M16 | ||||
10M25 | ||||
10M40 | 35 | 52 | 77 | MHz |
10M50 |
UFM Performance Specifications
Block | Mode | Interface | Device | Frequency | Unit | |
---|---|---|---|---|---|---|
Minimum | Maximum | |||||
UFM | Avalon® -MM slave | Parallel 34 | 10M02 35 | 3.43 | 7.25 | MHz |
10M04, 10M08, 10M16, 10M25, 10M40, 10M50 | 5 | 116 | MHz | |||
Serial 35 | 10M02, 10M04, 10M08, 10M16, 10M25 | 3.43 | 7.25 | MHz | ||
10M40, 10M50 | 2.18 | 4.81 | MHz |
ADC Performance Specifications
Single Supply Devices ADC Performance Specifications
Parameter | Symbol | Condition | Min | Typ | Max | Unit | |
---|---|---|---|---|---|---|---|
ADC resolution | — | — | — | — | 12 | bits | |
ADC supply voltage | VCC_ONE | — | 2.85 | 3.0/3.3 | 3.465 | V | |
External reference voltage | VREF | — | VCC_ONE – 0.5 | — | VCC_ONE | V | |
Sampling rate | FS | Accumulative sampling rate | — | — | 1 | MSPS | |
Operating junction temperature range | TJ | — | –40 | 25 | 125 | °C | |
Analog input voltage | VIN | Prescalar disabled | 0 | — | VREF | V | |
Prescalar enabled 36 | 0 | — | 3.6 | V | |||
Input resistance | RIN | — | — | 37 | — | — | |
Input capacitance | CIN | — | — | 37 | — | — | |
DC Accuracy | Offset error and drift | Eoffset | Prescalar disabled | –0.2 | — | 0.2 | %FS |
Prescalar enabled | –0.5 | — | 0.5 | %FS | |||
Gain error and drift | Egain | Prescalar disabled | –0.5 | — | 0.5 | %FS | |
Prescalar enabled | –0.75 | — | 0.75 | %FS | |||
Differential non linearity | DNL | External VREF, no missing code | –0.9 | — | 0.9 | LSB | |
Internal VREF, no missing code | –1 | — | 1.7 | LSB | |||
Integral non linearity | INL | — | –2 | — | 2 | LSB | |
AC Accuracy | Total harmonic distortion | THD | FIN = 50 kHz, FS = 1 MHz, PLL | –65 38 | — | — | dB |
Signal-to-noise ratio | SNR | FIN = 50 kHz, FS = 1 MHz, PLL | 54 39 | — | — | dB | |
Signal-to-noise and distortion | SINAD | FIN = 50 kHz, FS = 1 MHz, PLL | 53 40 | — | — | dB | |
On-Chip Temperature Sensor | Temperature sampling rate | TS | — | — | — | 50 | kSPS |
Absolute accuracy | — | –40 to 125°C, with 64 samples averaging 41 |
— | — | ±10 | °C | |
Conversion Rate 42 | Conversion time | — | Single measurement | — | — | 1 | Cycle |
Continuous measurement | — | — | 1 | Cycle | |||
Temperature measurement | — | — | 1 | Cycle |
Dual Supply Devices ADC Performance Specifications
Parameter | Symbol | Condition | Min | Typ | Max | Unit | |
---|---|---|---|---|---|---|---|
ADC resolution | — | — | — | — | 12 | bits | |
Analog supply voltage | VCCA_ADC | — | 2.375 | 2.5 | 2.625 | V | |
Digital supply voltage | VCCINT | — | 1.15 | 1.2 | 1.25 | V | |
External reference voltage | VREF | — | VCCA_ADC – 0.5 | — | VCCA_ADC | V | |
Sampling rate | FS | Accumulative sampling rate | — | — | 1 | MSPS | |
Operating junction temperature range | TJ | — | –40 | 25 | 125 | °C | |
Analog input voltage | VIN | Prescalar disabled | 0 | — | VREF | V | |
Prescalar enabled 43 | 0 | — | 3 | V | |||
Analog supply current (DC) | IACC_ADC | Average current | — | 275 | 450 | µA | |
Digital supply current (DC) | ICCINT | Average current | — | 65 | 150 | µA | |
Input resistance | RIN | — | — | 44 | — | — | |
Input capacitance | CIN | — | — | 44 | — | — | |
DC Accuracy | Offset error and drift | Eoffset | Prescalar disabled | –0.2 | — | 0.2 | %FS |
Prescalar enabled | –0.5 | — | 0.5 | %FS | |||
Gain error and drift | Egain | Prescalar disabled | –0.5 | — | 0.5 | %FS | |
Prescalar enabled | –0.75 | — | 0.75 | %FS | |||
Differential non linearity | DNL | External VREF, no missing code | –0.9 | — | 0.9 | LSB | |
Internal VREF, no missing code | –1 | — | 1.7 | LSB | |||
Integral non linearity | INL | — | –2 | — | 2 | LSB | |
AC Accuracy | Total harmonic distortion | THD | FIN = 50 kHz, FS = 1 MHz, PLL | –70 45 46 47 | — | — | dB |
Signal-to-noise ratio | SNR | FIN = 50 kHz, FS = 1 MHz, PLL | 62 48 49 47 | — | — | dB | |
Signal-to-noise and distortion | SINAD | FIN = 50 kHz, FS = 1 MHz, PLL | 61.5 50 51 47 | — | — | dB | |
On-Chip Temperature Sensor | Temperature sampling rate | TS | — | — | — | 50 | kSPS |
Absolute accuracy | — | –40 to 125°C, with 64 samples averaging 52 |
— | — | ±5 | °C | |
Conversion Rate 53 | Conversion time | — | Single measurement | — | — | 1 | Cycle |
Continuous measurement | — | — | 1 | Cycle | |||
Temperature measurement | — | — | 1 | Cycle |
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
For more information about the high-speed and low-speed I/O performance pins, refer to the respective device pin-out files.
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
Symbol | Parameter | Mode | –I6, –A6, –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz |
×8 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×7 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×4 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×2 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×1 | 5 | — | 310 | 5 | — | 310 | 5 | — | 310 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | — | 310 | 100 | — | 310 | 100 | — | 310 | Mbps |
×8 | 80 | — | 310 | 80 | — | 310 | 80 | — | 310 | Mbps | ||
×7 | 70 | — | 310 | 70 | — | 310 | 70 | — | 310 | Mbps | ||
×4 | 40 | — | 310 | 40 | — | 310 | 40 | — | 310 | Mbps | ||
×2 | 20 | — | 310 | 20 | — | 310 | 20 | — | 310 | Mbps | ||
×1 | 10 | — | 310 | 10 | — | 310 | 10 | — | 310 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz |
×8 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×7 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×4 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×2 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×1 | 5 | — | 300 | 5 | — | 300 | 5 | — | 300 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | — | 300 | 100 | — | 300 | 100 | — | 300 | Mbps |
×8 | 80 | — | 300 | 80 | — | 300 | 80 | — | 300 | Mbps | ||
×7 | 70 | — | 300 | 70 | — | 300 | 70 | — | 300 | Mbps | ||
×4 | 40 | — | 300 | 40 | — | 300 | 40 | — | 300 | Mbps | ||
×2 | 20 | — | 300 | 20 | — | 300 | 20 | — | 300 | Mbps | ||
×1 | 10 | — | 300 | 10 | — | 300 | 10 | — | 300 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS54 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 55 | Output jitter (high-speed I/O performance pin) | — | — | — | 425 | — | — | 425 | — | — | 425 | ps |
Output jitter (low-speed I/O performance pin) | — | — | — | 470 | — | — | 470 | — | — | 470 | ps | |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Single Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Symbol | Parameter | Mode | –I6, –A6, –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz |
×8 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×7 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×4 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×2 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×1 | 5 | — | 100 | 5 | — | 100 | 5 | — | 100 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | — | 100 | 100 | — | 100 | 100 | — | 100 | Mbps |
×8 | 80 | — | 100 | 80 | — | 100 | 80 | — | 100 | Mbps | ||
×7 | 70 | — | 100 | 70 | — | 100 | 70 | — | 100 | Mbps | ||
×4 | 40 | — | 100 | 40 | — | 100 | 40 | — | 100 | Mbps | ||
×2 | 20 | — | 100 | 20 | — | 100 | 20 | — | 100 | Mbps | ||
×1 | 10 | — | 100 | 10 | — | 100 | 10 | — | 100 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz |
×8 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×7 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×4 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×2 | 5 | — | 50 | 5 | — | 50 | 5 | — | 50 | MHz | ||
×1 | 5 | — | 100 | 5 | — | 100 | 5 | — | 100 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | — | 100 | 100 | — | 100 | 100 | — | 100 | Mbps |
×8 | 80 | — | 100 | 80 | — | 100 | 80 | — | 100 | Mbps | ||
×7 | 70 | — | 100 | 70 | — | 100 | 70 | — | 100 | Mbps | ||
×4 | 40 | — | 100 | 40 | — | 100 | 40 | — | 100 | Mbps | ||
×2 | 20 | — | 100 | 20 | — | 100 | 20 | — | 100 | Mbps | ||
×1 | 10 | — | 100 | 10 | — | 100 | 10 | — | 100 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS56 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 57 | Output jitter (high-speed I/O performance pin) | — | — | — | 425 | — | — | 425 | — | — | 425 | ps |
Output jitter (low-speed I/O performance pin) | — | — | — | 470 | — | — | 470 | — | — | 470 | ps | |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Symbol | Parameter | Mode | –I6, –A6, –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz |
×8 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×7 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×4 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×2 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×1 | 5 | — | 310 | 5 | — | 310 | 5 | — | 310 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | — | 310 | 100 | — | 310 | 100 | — | 310 | Mbps |
×8 | 80 | — | 310 | 80 | — | 310 | 80 | — | 310 | Mbps | ||
×7 | 70 | — | 310 | 70 | — | 310 | 70 | — | 310 | Mbps | ||
×4 | 40 | — | 310 | 40 | — | 310 | 40 | — | 310 | Mbps | ||
×2 | 20 | — | 310 | 20 | — | 310 | 20 | — | 310 | Mbps | ||
×1 | 10 | — | 310 | 10 | — | 310 | 10 | — | 310 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz |
×8 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×7 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×4 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×2 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×1 | 5 | — | 300 | 5 | — | 300 | 5 | — | 300 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | — | 300 | 100 | — | 300 | 100 | — | 300 | Mbps |
×8 | 80 | — | 300 | 80 | — | 300 | 80 | — | 300 | Mbps | ||
×7 | 70 | — | 300 | 70 | — | 300 | 70 | — | 300 | Mbps | ||
×4 | 40 | — | 300 | 40 | — | 300 | 40 | — | 300 | Mbps | ||
×2 | 20 | — | 300 | 20 | — | 300 | 20 | — | 300 | Mbps | ||
×1 | 10 | — | 300 | 10 | — | 300 | 10 | — | 300 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS58 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 59 | Output jitter (high-speed I/O performance pin) | — | — | — | 425 | — | — | 425 | — | — | 425 | ps |
Output jitter (low-speed I/O performance pin) | — | — | — | 470 | — | — | 470 | — | — | 470 | ps | |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
Emulated RSDS_E_1R Transmitter Timing Specifications
Symbol | Parameter | Mode | –I6, –A6, –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz |
×8 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×7 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×4 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×2 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×1 | 5 | — | 170 | 5 | — | 170 | 5 | — | 170 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | — | 170 | 100 | — | 170 | 100 | — | 170 | Mbps |
×8 | 80 | — | 170 | 80 | — | 170 | 80 | — | 170 | Mbps | ||
×7 | 70 | — | 170 | 70 | — | 170 | 70 | — | 170 | Mbps | ||
×4 | 40 | — | 170 | 40 | — | 170 | 40 | — | 170 | Mbps | ||
×2 | 20 | — | 170 | 20 | — | 170 | 20 | — | 170 | Mbps | ||
×1 | 10 | — | 170 | 10 | — | 170 | 10 | — | 170 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz |
×8 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×7 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×4 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×2 | 5 | — | 85 | 5 | — | 85 | 5 | — | 85 | MHz | ||
×1 | 5 | — | 170 | 5 | — | 170 | 5 | — | 170 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | — | 170 | 100 | — | 170 | 100 | — | 170 | Mbps |
×8 | 80 | — | 170 | 80 | — | 170 | 80 | — | 170 | Mbps | ||
×7 | 70 | — | 170 | 70 | — | 170 | 70 | — | 170 | Mbps | ||
×4 | 40 | — | 170 | 40 | — | 170 | 40 | — | 170 | Mbps | ||
×2 | 20 | — | 170 | 20 | — | 170 | 20 | — | 170 | Mbps | ||
×1 | 10 | — | 170 | 10 | — | 170 | 10 | — | 170 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS60 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 61 | Output jitter (high-speed I/O performance pin) | — | — | — | 425 | — | — | 425 | — | — | 425 | ps |
Output jitter (low-speed I/O performance pin) | — | — | — | 470 | — | — | 470 | — | — | 470 | ps | |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications
Symbol | Parameter | Mode | –I6, –A6, –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz |
×8 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×7 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×4 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×2 | 5 | — | 155 | 5 | — | 155 | 5 | — | 155 | MHz | ||
×1 | 5 | — | 310 | 5 | — | 310 | 5 | — | 310 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | — | 310 | 100 | — | 310 | 100 | — | 310 | Mbps |
×8 | 80 | — | 310 | 80 | — | 310 | 80 | — | 310 | Mbps | ||
×7 | 70 | — | 310 | 70 | — | 310 | 70 | — | 310 | Mbps | ||
×4 | 40 | — | 310 | 40 | — | 310 | 40 | — | 310 | Mbps | ||
×2 | 20 | — | 310 | 20 | — | 310 | 20 | — | 310 | Mbps | ||
×1 | 10 | — | 310 | 10 | — | 310 | 10 | — | 310 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz |
×8 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×7 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×4 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×2 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×1 | 5 | — | 300 | 5 | — | 300 | 5 | — | 300 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | — | 300 | 100 | — | 300 | 100 | — | 300 | Mbps |
×8 | 80 | — | 300 | 80 | — | 300 | 80 | — | 300 | Mbps | ||
×7 | 70 | — | 300 | 70 | — | 300 | 70 | — | 300 | Mbps | ||
×4 | 40 | — | 300 | 40 | — | 300 | 40 | — | 300 | Mbps | ||
×2 | 20 | — | 300 | 20 | — | 300 | 20 | — | 300 | Mbps | ||
×1 | 10 | — | 300 | 10 | — | 300 | 10 | — | 300 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS62 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 63 | Output jitter (high-speed I/O performance pin) | — | — | — | 425 | — | — | 425 | — | — | 425 | ps |
Output jitter (low-speed I/O performance pin) | — | — | — | 470 | — | — | 470 | — | — | 470 | ps | |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
True LVDS Transmitter Timing
Single Supply Devices True LVDS Transmitter Timing Specifications
Symbol | Parameter | Mode | –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency | ×10 | 5 | — | 145 | 5 | — | 100 | 5 | — | 100 | MHz |
×8 | 5 | — | 145 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×7 | 5 | — | 145 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×4 | 5 | — | 145 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×2 | 5 | — | 145 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×1 | 5 | — | 290 | 5 | — | 200 | 5 | — | 200 | MHz | ||
HSIODR | Data rate | ×10 | 100 | — | 290 | 100 | — | 200 | 100 | — | 200 | Mbps |
×8 | 80 | — | 290 | 80 | — | 200 | 80 | — | 200 | Mbps | ||
×7 | 70 | — | 290 | 70 | — | 200 | 70 | — | 200 | Mbps | ||
×4 | 40 | — | 290 | 40 | — | 200 | 40 | — | 200 | Mbps | ||
×2 | 20 | — | 290 | 20 | — | 200 | 20 | — | 200 | Mbps | ||
×1 | 10 | — | 290 | 10 | — | 200 | 10 | — | 200 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS64 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 65 | Output jitter | — | — | — | 1,000 | — | — | 1,000 | — | — | 1,000 | ps |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
Dual Supply Devices True LVDS Transmitter Timing Specifications
Symbol | Parameter | Mode | –I6 | –A6, –C7, –I7 | –A7 | –C8 | Unit | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency | ×10 | 5 | — | 360 | 5 | — | 340 | 5 | — | 310 | 5 | — | 300 | MHz |
×8 | 5 | — | 360 | 5 | — | 360 | 5 | — | 320 | 5 | — | 320 | MHz | ||
×7 | 5 | — | 360 | 5 | — | 340 | 5 | — | 310 | 5 | — | 300 | MHz | ||
×4 | 5 | — | 360 | 5 | — | 350 | 5 | — | 320 | 5 | — | 320 | MHz | ||
×2 | 5 | — | 360 | 5 | — | 350 | 5 | — | 320 | 5 | — | 320 | MHz | ||
×1 | 5 | — | 360 | 5 | — | 350 | 5 | — | 320 | 5 | — | 320 | MHz | ||
HSIODR | Data rate | ×10 | 100 | — | 720 | 100 | — | 680 | 100 | — | 620 | 100 | — | 600 | Mbps |
×8 | 80 | — | 720 | 80 | — | 720 | 80 | — | 640 | 80 | — | 640 | Mbps | ||
×7 | 70 | — | 720 | 70 | — | 680 | 70 | — | 620 | 70 | — | 600 | Mbps | ||
×4 | 40 | — | 720 | 40 | — | 700 | 40 | — | 640 | 40 | — | 640 | Mbps | ||
×2 | 20 | — | 720 | 20 | — | 700 | 20 | — | 640 | 20 | — | 640 | Mbps | ||
×1 | 10 | — | 360 | 10 | — | 350 | 10 | — | 320 | 10 | — | 320 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS66 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 67 | Output jitter | — | — | — | 380 | — | — | 380 | — | — | 380 | — | — | 380 | ps |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | — | — | 1 | ms |
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications
Symbol | Parameter | Mode | –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | — | 142.5 | 5 | — | 100 | 5 | — | 100 | MHz |
×8 | 5 | — | 142.5 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×7 | 5 | — | 142.5 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×4 | 5 | — | 142.5 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×2 | 5 | — | 142.5 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×1 | 5 | — | 285 | 5 | — | 200 | 5 | — | 200 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | — | 285 | 100 | — | 200 | 100 | — | 200 | Mbps |
×8 | 80 | — | 285 | 80 | — | 200 | 80 | — | 200 | Mbps | ||
×7 | 70 | — | 285 | 70 | — | 200 | 70 | — | 200 | Mbps | ||
×4 | 40 | — | 285 | 40 | — | 200 | 40 | — | 200 | Mbps | ||
×2 | 20 | — | 285 | 20 | — | 200 | 20 | — | 200 | Mbps | ||
×1 | 10 | — | 285 | 10 | — | 200 | 10 | — | 200 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | — | 100 | 5 | — | 100 | 5 | — | 100 | MHz |
×8 | 5 | — | 100 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×7 | 5 | — | 100 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×4 | 5 | — | 100 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×2 | 5 | — | 100 | 5 | — | 100 | 5 | — | 100 | MHz | ||
×1 | 5 | — | 200 | 5 | — | 200 | 5 | — | 200 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | — | 200 | 100 | — | 200 | 100 | — | 200 | Mbps |
×8 | 80 | — | 200 | 80 | — | 200 | 80 | — | 200 | Mbps | ||
×7 | 70 | — | 200 | 70 | — | 200 | 70 | — | 200 | Mbps | ||
×4 | 40 | — | 200 | 40 | — | 200 | 40 | — | 200 | Mbps | ||
×2 | 20 | — | 200 | 20 | — | 200 | 20 | — | 200 | Mbps | ||
×1 | 10 | — | 200 | 10 | — | 200 | 10 | — | 200 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS68 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 69 | Output jitter | — | — | — | 1,000 | — | — | 1,000 | — | — | 1,000 | ps |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Symbol | Parameter | Mode | –I6, –A6, –C7, –I7 | –A7 | –C8 | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | — | 300 | 5 | — | 275 | 5 | — | 275 | MHz |
×8 | 5 | — | 300 | 5 | — | 275 | 5 | — | 275 | MHz | ||
×7 | 5 | — | 300 | 5 | — | 275 | 5 | — | 275 | MHz | ||
×4 | 5 | — | 300 | 5 | — | 275 | 5 | — | 275 | MHz | ||
×2 | 5 | — | 300 | 5 | — | 275 | 5 | — | 275 | MHz | ||
×1 | 5 | — | 300 | 5 | — | 275 | 5 | — | 275 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | — | 600 | 100 | — | 550 | 100 | — | 550 | Mbps |
×8 | 80 | — | 600 | 80 | — | 550 | 80 | — | 550 | Mbps | ||
×7 | 70 | — | 600 | 70 | — | 550 | 70 | — | 550 | Mbps | ||
×4 | 40 | — | 600 | 40 | — | 550 | 40 | — | 550 | Mbps | ||
×2 | 20 | — | 600 | 20 | — | 550 | 20 | — | 550 | Mbps | ||
×1 | 10 | — | 300 | 10 | — | 275 | 10 | — | 275 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz |
×8 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×7 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×4 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×2 | 5 | — | 150 | 5 | — | 150 | 5 | — | 150 | MHz | ||
×1 | 5 | — | 300 | 5 | — | 300 | 5 | — | 300 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | — | 300 | 100 | — | 300 | 100 | — | 300 | Mbps |
×8 | 80 | — | 300 | 80 | — | 300 | 80 | — | 300 | Mbps | ||
×7 | 70 | — | 300 | 70 | — | 300 | 70 | — | 300 | Mbps | ||
×4 | 40 | — | 300 | 40 | — | 300 | 40 | — | 300 | Mbps | ||
×2 | 20 | — | 300 | 20 | — | 300 | 20 | — | 300 | Mbps | ||
×1 | 10 | — | 300 | 10 | — | 300 | 10 | — | 300 | Mbps | ||
tDUTY | Duty cycle on transmitter output clock | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS70 | Transmitter channel-to-channel skew | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
tx Jitter 71 | Output jitter (high-speed I/O performance pin) | — | — | — | 425 | — | — | 425 | — | — | 425 | ps |
Output jitter (low-speed I/O performance pin) | — | — | — | 470 | — | — | 470 | — | — | 470 | ps | |
tRISE | Rise time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | Fall time | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | — | 1 | — | — | 1 | — | — | 1 | ms |
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Single Supply Devices LVDS Receiver Timing Specifications
Symbol | Parameter | Mode | –C7, –I7 | –A7 | –C8 | Unit | |||
---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Min | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | 145 | 5 | 100 | 5 | 100 | MHz |
×8 | 5 | 145 | 5 | 100 | 5 | 100 | MHz | ||
×7 | 5 | 145 | 5 | 100 | 5 | 100 | MHz | ||
×4 | 5 | 145 | 5 | 100 | 5 | 100 | MHz | ||
×2 | 5 | 145 | 5 | 100 | 5 | 100 | MHz | ||
×1 | 5 | 290 | 5 | 200 | 5 | 200 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | 290 | 100 | 200 | 100 | 200 | Mbps |
×8 | 80 | 290 | 80 | 200 | 80 | 200 | Mbps | ||
×7 | 70 | 290 | 70 | 200 | 70 | 200 | Mbps | ||
×4 | 40 | 290 | 40 | 200 | 40 | 200 | Mbps | ||
×2 | 20 | 290 | 20 | 200 | 20 | 200 | Mbps | ||
×1 | 10 | 290 | 10 | 200 | 10 | 200 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | 100 | 5 | 100 | 5 | 100 | MHz |
×8 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
×7 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
×4 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
×2 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
×1 | 5 | 200 | 5 | 200 | 5 | 200 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | 200 | 100 | 200 | 100 | 200 | Mbps |
×8 | 80 | 200 | 80 | 200 | 80 | 200 | Mbps | ||
×7 | 70 | 200 | 70 | 200 | 70 | 200 | Mbps | ||
×4 | 40 | 200 | 40 | 200 | 40 | 200 | Mbps | ||
×2 | 20 | 200 | 20 | 200 | 20 | 200 | Mbps | ||
×1 | 10 | 200 | 10 | 200 | 10 | 200 | Mbps | ||
SW | Sampling window (high-speed I/O performance pin) | — | — | 910 | — | 910 | — | 910 | ps |
Sampling window (low-speed I/O performance pin) | — | — | 1,110 | — | 1,110 | — | 1,110 | ps | |
tx Jitter 72 | Input jitter | — | — | 1,000 | — | 1,000 | — | 1,000 | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | 1 | — | 1 | — | 1 | ms |
Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Symbol | Parameter | Mode | –I6, –A6, –C7, –I7 | –A7 | –C8 | Unit | |||
---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Min | Max | ||||
fHSCLK | Input clock frequency (high-speed I/O performance pin) | ×10 | 5 | 350 | 5 | 320 | 5 | 320 | MHz |
×8 | 5 | 360 | 5 | 320 | 5 | 320 | MHz | ||
×7 | 5 | 350 | 5 | 320 | 5 | 320 | MHz | ||
×4 | 5 | 360 | 5 | 320 | 5 | 320 | MHz | ||
×2 | 5 | 360 | 5 | 320 | 5 | 320 | MHz | ||
×1 | 5 | 360 | 5 | 320 | 5 | 320 | MHz | ||
HSIODR | Data rate (high-speed I/O performance pin) | ×10 | 100 | 700 | 100 | 640 | 100 | 640 | Mbps |
×8 | 80 | 720 | 80 | 640 | 80 | 640 | Mbps | ||
×7 | 70 | 700 | 70 | 640 | 70 | 640 | Mbps | ||
×4 | 40 | 720 | 40 | 640 | 40 | 640 | Mbps | ||
×2 | 20 | 720 | 20 | 640 | 20 | 640 | Mbps | ||
×1 | 10 | 360 | 10 | 320 | 10 | 320 | Mbps | ||
fHSCLK | Input clock frequency (low-speed I/O performance pin) | ×10 | 5 | 150 | 5 | 150 | 5 | 150 | MHz |
×8 | 5 | 150 | 5 | 150 | 5 | 150 | MHz | ||
×7 | 5 | 150 | 5 | 150 | 5 | 150 | MHz | ||
×4 | 5 | 150 | 5 | 150 | 5 | 150 | MHz | ||
×2 | 5 | 150 | 5 | 150 | 5 | 150 | MHz | ||
×1 | 5 | 300 | 5 | 300 | 5 | 300 | MHz | ||
HSIODR | Data rate (low-speed I/O performance pin) | ×10 | 100 | 300 | 100 | 300 | 100 | 300 | Mbps |
×8 | 80 | 300 | 80 | 300 | 80 | 300 | Mbps | ||
×7 | 70 | 300 | 70 | 300 | 70 | 300 | Mbps | ||
×4 | 40 | 300 | 40 | 300 | 40 | 300 | Mbps | ||
×2 | 20 | 300 | 20 | 300 | 20 | 300 | Mbps | ||
×1 | 10 | 300 | 10 | 300 | 10 | 300 | Mbps | ||
SW | Sampling window (high-speed I/O performance pin) | — | — | 510 | — | 510 | — | 510 | ps |
Sampling window (low-speed I/O performance pin) | — | — | 910 | — | 910 | — | 910 | ps | |
tx Jitter 73 | Input jitter | — | — | 500 | — | 500 | — | 500 | ps |
tLOCK | Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration | — | — | 1 | — | 1 | — | 1 | ms |
Memory Standards Supported by the Soft Memory Controller
External Memory Interface Standard | Rate Support | Speed Grade | Voltage (V) | Max Frequency (MHz) |
---|---|---|---|---|
DDR3 SDRAM | Half | –I6 | 1.5 | 303 |
DDR3L SDRAM | Half | –I6 | 1.35 | 303 |
DDR2 SDRAM | Half | –I6 | 1.8 | 200 |
–I7 and –C7 | 167 | |||
LPDDR2 74 | Half | –I6 | 1.2 | 200 75 |
Memory Output Clock Jitter Specifications
Intel® MAX® 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for Intel® MAX® 10 devices calibrate automatically.
The memory output clock jitter measurements are for 200 consecutive clock cycles.
The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a PHY clock network.
DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.
Parameter | Symbol | –6 Speed Grade | –7 Speed Grade | Unit | ||
---|---|---|---|---|---|---|
Min | Max | Min | Max | |||
Clock period jitter | tJIT(per) | –127 | 127 | –215 | 215 | ps |
Cycle-to-cycle period jitter | tJIT(cc) | — | 242 | — | 360 | ps |
Configuration Specifications
This section provides configuration specifications and timing for Intel® MAX® 10 devices.
JTAG Timing Parameters
Symbol | Parameter | Non-BST and non-CONFIG_IO Operation | BST and CONFIG_IO Operation | Unit | ||
---|---|---|---|---|---|---|
Minimum | Maximum | Minimum | Maximum | |||
tJCP | TCK clock period | 40 | — | 50 | — | ns |
tJCH | TCK clock high time | 20 | — | 25 | — | ns |
tJCL | TCK clock low time | 20 | — | 25 | — | ns |
tJPSU_TDI | JTAG port setup time | 2 | — | 2 | — | ns |
tJPSU_TMS | JTAG port setup time | 3 | — | 3 | — | ns |
tJPH | JTAG port hold time | 10 | — | 10 | — | ns |
tJPCO | JTAG port clock to output | — |
|
— |
|
ns |
tJPZX | JTAG port high impedance to valid output | — |
|
— |
|
ns |
tJPXZ | JTAG port valid output to high impedance | — |
|
— |
|
ns |
Remote System Upgrade Circuitry Timing Specifications
Parameter | Device | Minimum | Maximum | Unit |
---|---|---|---|---|
tMAX_RU_CLK | All | — | 40 | MHz |
tRU_nCONFIG | 10M02, 10M04, 10M08, 10M16, 10M25 | 250 | — | ns |
10M40, 10M50 | 350 | — | ns | |
tRU_nRSTIMER | 10M02, 10M04, 10M08, 10M16, 10M25 | 300 | — | ns |
10M40, 10M50 | 500 | — | ns |
User Watchdog Internal Circuitry Timing Specifications
Parameter | Device | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
User watchdog frequency | 10M02, 10M04, 10M08, 10M16, 10M25 | 3.4 | 5.1 | 7.3 | MHz |
10M40, 10M50 | 2.2 | 3.3 | 4.8 | MHz |
Uncompressed Raw Binary File (.rbf) Sizes
Device | CFM Data Size (bits) | |
---|---|---|
Without Memory Initialization | With Memory Initialization | |
10M02/10M02SCU324 | 554,000/1,540,000 | — |
10M04 | 1,540,000 | 1,880,000 |
10M08 | 1,540,000 | 1,880,000 |
10M16 | 2,800,000 | 3,430,000 |
10M25 | 4,140,000 | 4,780,000 |
10M40 | 7,840,000 | 9,670,000 |
10M50 | 7,840,000 | 9,670,000 |
Internal Configuration Time
The internal configuration time measurement is from the rising edge of nSTATUS signal to the rising edge of CONF_DONE signal.
Device | Internal Configuration Time (ms) | |||||||
---|---|---|---|---|---|---|---|---|
Unencrypted | Encrypted | |||||||
Without Memory Initialization | With Memory Initialization | Without Memory Initialization | With Memory Initialization | |||||
Min | Max | Min | Max | Min | Max | Min | Max | |
10M02/ 10M02SCU324 | 0.3/0.6 | 1.7/2.7 | — | — | 1.7/5.0 | 5.4/15.0 | — | — |
10M04 | 0.6 | 2.7 | 1.0 | 3.4 | 5.0 | 15.0 | 6.8 | 19.6 |
10M08 | 0.6 | 2.7 | 1.0 | 3.4 | 5.0 | 15.0 | 6.8 | 19.6 |
10M16 | 1.1 | 3.7 | 1.4 | 4.5 | 9.3 | 25.3 | 11.7 | 31.5 |
10M25 | 1.0 | 3.7 | 1.3 | 4.4 | 14.0 | 38.1 | 16.9 | 45.7 |
10M40 | 2.6 | 6.9 | 3.2 | 9.8 | 41.5 | 112.1 | 51.7 |