Intel MAX 10 FPGA Device Datasheet

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M10-DATASHEET | 2018.06.29

Intel MAX 10 FPGA Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel^® MAX^® 10 devices.

Table 1. Intel^® MAX^® 10 Device Grades and Speed Grades Supported
Device Grade	Speed Grade Supported
Commercial	–C7 –C8 (slowest)
Industrial	–I6 (fastest) –I7
Automotive	–A6 –A7

Note: The –I6 and –A6 speed grades of the Intel^® MAX^® 10 FPGA devices are not available by default in the Intel^® Quartus^® Prime software. Contact your local Intel sales representatives for support.

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Intel^® MAX^® 10 devices.

Operating Conditions

Intel^® MAX^® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel^® MAX^® 10 devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions for Intel^® MAX^® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

CAUTION:

Conditions outside the range listed in the absolute maximum ratings tables may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Single Supply Devices Absolute Maximum Ratings

Table 2. Absolute Maximum Ratings for Intel^® MAX^® 10 Single Supply Devices
Symbol	Parameter	Min	Max	Unit
V_{CC_ONE}	Supply voltage for core and periphery through on-die voltage regulator	–0.5	3.9	V
V_CCIO	Supply voltage for input and output buffers	–0.5	3.9	V
V_CCA	Supply voltage for phase-locked loop (PLL) regulator and analog-to-digital converter (ADC) block (analog)	–0.5	3.9	V

Dual Supply Devices Absolute Maximum Ratings

Table 3. Absolute Maximum Ratings for Intel^® MAX^® 10 Dual Supply Devices
Symbol	Parameter	Min	Max	Unit
V_CC	Supply voltage for core and periphery	–0.5	1.63	V
V_CCIO	Supply voltage for input and output buffers	–0.5	3.9	V
V_CCA	Supply voltage for PLL regulator (analog)	–0.5	3.41	V
V_{CCD_PLL}	Supply voltage for PLL regulator (digital)	–0.5	1.63	V
V_{CCA_ADC}	Supply voltage for ADC analog block	–0.5	3.41	V
V_CCINT	Supply voltage for ADC digital block	–0.5	1.63	V

Absolute Maximum Ratings

Table 4. Absolute Maximum Ratings for Intel^® MAX^® 10 Devices
Symbol	Parameter	Min	Max	Unit
V_I	DC input voltage	–0.5	4.12	V
I_OUT	DC output current per pin	–25	25	mA
T_STG	Storage temperature	–65	150	°C
T_J	Operating junction temperature	–40	125	°C

Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame

During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.

The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

For example, a signal that overshoots to 4.17 V can only be at 4.17 V for ~11.7% over the lifetime of the device; for a device lifetime of 11.4 years, this amounts to 1.33 years.

Table 5. Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame for Intel^® MAX^® 10 Devices
Condition (V)	Overshoot Duration as % of High Time	Unit
4.12	100.0	%
4.17	11.7	%
4.22	7.1	%
4.27	4.3	%
4.32	2.6	%
4.37	1.6	%
4.42	1.0	%
4.47	0.6	%
4.52	0.3	%
4.57	0.2	%

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for Intel^® MAX^® 10 devices. The tables list the steady-state voltage values expected from Intel^® MAX^® 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.

Single Supply Devices Power Supplies Recommended Operating Conditions

Table 6. Power Supplies Recommended Operating Conditions for Intel^® MAX^® 10 Single Supply Devices
Symbol	Parameter	Condition	Min	Typ	Max	Unit
V_{CC_ONE} ¹	Supply voltage for core and periphery through on-die voltage regulator	—	2.85/3.135	3.0/3.3	3.15/3.465	V
V_CCIO ²	Supply voltage for input and output buffers	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3	3.15	V
		2.5 V	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
		1.5 V	1.425	1.5	1.575	V
		1.35 V	1.2825	1.35	1.4175	V
		1.2 V	1.14	1.2	1.26	V
V_CCA ¹	Supply voltage for PLL regulator and ADC block (analog)	—	2.85/3.135	3.0/3.3	3.15/3.465	V

¹ V_CCA must be connected to V_{CC_ONE} through a filter.

² V_CCIO for all I/O banks must be powered up during user mode because V_CCIO I/O banks are used for the ADC and I/O functionalities.

Dual Supply Devices Power Supplies Recommended Operating Conditions

Table 7. Power Supplies Recommended Operating Conditions for Intel^® MAX^® 10 Dual Supply Devices
Symbol	Parameter	Condition	Min	Typ	Max	Unit
V_CC	Supply voltage for core and periphery	—	1.15	1.2	1.25	V
V_CCIO ³	Supply voltage for input and output buffers	3.3 V	3.135	3.3	3.465	V
		3.0 V	2.85	3	3.15	V
		2.5 V	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
		1.5 V	1.425	1.5	1.575	V
		1.35 V	1.2825	1.35	1.4175	V
		1.2 V	1.14	1.2	1.26	V
V_CCA ⁴	Supply voltage for PLL regulator (analog)	—	2.375	2.5	2.625	V
V_{CCD_PLL} ⁵	Supply voltage for PLL regulator (digital)	—	1.15	1.2	1.25	V
V_{CCA_ADC}	Supply voltage for ADC analog block	—	2.375	2.5	2.625	V
V_CCINT	Supply voltage for ADC digital block	—	1.15	1.2	1.25	V

³ V_CCIO for all I/O banks must be powered up during user mode because V_CCIO I/O banks are used for the ADC and I/O functionalities.

⁴ All V_CCA pins must be powered to 2.5 V (even when PLLs are not used), and must be powered up and powered down at the same time.

⁵ V_{CCD_PLL} must always be connected to V_CC through a decoupling capacitor and ferrite bead.

Recommended Operating Conditions

Table 8. Recommended Operating Conditions for Intel^® MAX^® 10 Devices
Symbol	Parameter	Condition	Min	Max	Unit
V_I	DC input voltage	—	–0.5	3.6	V
V_O	Output voltage for I/O pins	—	0	V_CCIO	V
T_J	Operating junction temperature	Commercial	0	85	°C
		Industrial	–40 ⁶	100	°C
		Automotive	–40⁶	125	°C
t_RAMP	Power supply ramp time	—	⁷	10	ms
I_Diode	Magnitude of DC current across PCI™ clamp diode when enabled	—	—	10	mA

⁶ –40°C is only applicable to Start of Test, when the device is powered-on. The device does not stay at the minimum junction temperature for a long time.

⁷ There is no absolute minimum value for the ramp time requirement. Intel characterized the minimum ramp time at 200 μs.

Programming/Erasure Specifications

Table 9. Programming/Erasure Specifications for Intel^® MAX^® 10 Devices.
This table shows the programming cycles and data retention duration of the user flash memory (UFM) and configuration flash memory (CFM) blocks.

For more information about data retention duration with 10,000 programming cycles for automotive temperature devices, contact your Intel quality representative.
Erase and reprogram cycles (E/P) ⁸ (Cycles/page)	Temperature (°C)	Data retention duration (Years)
10,000	85	20
10,000	100	10

⁸ The number of E/P cycles applies to the smallest possible flash block that can be erased or programmed in each Intel^® MAX^® 10 device. Each Intel^® MAX^® 10 device has multiple flash pages per device.

DC Characteristics

Supply Current and Power Consumption

Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer feature.

Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel^® Quartus^® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

I/O Pin Leakage Current

The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all V_CCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).

10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on.

Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable to all Intel^® MAX^® 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A.

Table 10. I/O Pin Leakage Current for Intel^® MAX^® 10 Devices
Symbol	Parameter	Condition	Min	Max	Unit
I_I	Input pin leakage current	V_I = 0 V to V_CCIOMAX	–10	10	µA
I_OZ	Tristated I/O pin leakage current	V_O = 0 V to V_CCIOMAX	–10	10	µA

Table 11. ADC_VREF Pin Leakage Current for Intel^® MAX^® 10 Devices
Symbol	Parameter	Condition	Min	Max	Unit
I_{adc_vref}	`ADC_VREF` pin leakage current	Single supply mode	—	10	µA
I_{adc_vref}	`ADC_VREF` pin leakage current	Dual supply mode	—	20	µA

Bus Hold Parameters

Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.

Table 12. Bus Hold Parameters for Intel^® MAX^® 10 Devices
Parameter	Condition	V_CCIO (V)												Unit
		1.2		1.5		1.8		2.5		3.0		3.3
		Min	Max	Min	Max	Min	Max	Min	Max	Min	Max	Min	Max
Bus-hold low, sustaining current	V_IN > V_IL (maximum)	8	—	12	—	30	—	50	—	70	—	70	—	µA
Bus-hold high, sustaining current	V_IN < V_IH (minimum)	–8	—	–12	—	–30	—	–50	—	–70	—	–70	—	µA
Bus-hold low, overdrive current	0 V < V_IN < V_CCIO	—	125	—	175	—	200	—	300	—	500	—	500	µA
Bus-hold high, overdrive current	0 V < V_IN < V_CCIO	—	–125	—	–175	—	–200	—	–300	—	–500	—	–500	µA
Bus-hold trip point	—	0.3	0.9	0.375	1.125	0.68	1.07	0.7	1.7	0.8	2	0.8	2	V

Series OCT without Calibration Specifications

Table 13. Series OCT without Calibration Specifications for Intel^® MAX^® 10 Devices. This table shows the variation of on-chip termination (OCT) without calibration across process, voltage, and temperature (PVT).
Description	V_CCIO (V)	Resistance Tolerance		Unit
Description	V_CCIO (V)	–C7, –I6, –I7, –A6, –A7	–C8	Unit
Series OCT without calibration	3.00	±35	±30	%
	2.50	±35	±30	%
	1.80	±40	±35	%
	1.50	±40	±40	%
	1.35	±40	±50	%
	1.20	±45	±60	%

Series OCT with Calibration at Device Power-Up Specifications

Table 14. Series OCT with Calibration at Device Power-Up Specifications for Intel^® MAX^® 10 Devices. OCT calibration is automatically performed at device power-up for OCT enabled I/Os.
Description	V_CCIO (V)	Calibration Accuracy	Unit
Series OCT with calibration at device power-up	3.00	±12	%
	2.50	±12	%
	1.80	±12	%
	1.50	±12	%
	1.35	±12	%
	1.20	±12	%

OCT Variation after Calibration at Device Power-Up

The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up.

Use the following table and equation to determine the final OCT resistance considering the variations after calibration at device power-up.

Table 15. OCT Variation after Calibration at Device Power-Up for Intel^® MAX^® 10 Devices. This table lists the change percentage of the OCT resistance with voltage and temperature.
Description	Nominal Voltage	dR/dT (%/°C)	dR/dV (%/mV)
OCT variation after calibration at device power-up	3.00	0.25	–0.027
	2.50	0.245	–0.04
	1.80	0.242	–0.079
	1.50	0.235	–0.125
	1.35	0.229	–0.16
	1.20	0.197	–0.208

Figure 1. Equation for OCT Resistance after Calibration at Device Power-Up

The definitions for equation are as follows:

T₁ is the initial temperature.
T₂ is the final temperature.
MF is multiplication factor.
R_initial is initial resistance.
R_final is final resistance.
Subscript x refers to both V and T.
∆R_V is variation of resistance with voltage.
∆R_T is variation of resistance with temperature.
dR/dT is the change percentage of resistance with temperature after calibration at device power-up.
dR/dV is the change percentage of resistance with voltage after calibration at device power-up.
V₁ is the initial voltage.
V₂ is final voltage.

The following figure shows the example to calculate the change of 50 Ω I/O impedance from 25°C at 3.0 V to 85°C at 3.15 V.

Figure 2. Example for OCT Resistance Calculation after Calibration at Device Power-Up

Pin Capacitance

Table 16. Pin Capacitance for Intel^® MAX^® 10 Devices
Symbol	Parameter	Maximum	Unit
C_IOB	Input capacitance on bottom I/O pins	8	pF
C_IOLRT	Input capacitance on left/right/top I/O pins	7	pF
C_LVDSB	Input capacitance on bottom I/O pins with dedicated LVDS output ⁹	8	pF
C_ADCL	Input capacitance on left I/O pins with ADC input ¹⁰	9	pF
C_VREFLRT	Input capacitance on left/right/top dual purpose V_REF pin when used as V_REF or user I/O pin ¹¹	48	pF
C_VREFB	Input capacitance on bottom dual purpose V_REF pin when used as V_REF or user I/O pin	50	pF
C_CLKB	Input capacitance on bottom dual purpose clock input pins ¹²	7	pF
C_CLKLRT	Input capacitance on left/right/top dual purpose clock input pins ¹²	6	pF

⁹ Dedicated LVDS output buffer is only available at bottom I/O banks.

¹⁰ ADC pins are only available at left I/O banks.

¹¹ When V_REF pin is used as regular input or output, F_max performance is reduced due to higher pin capacitance. Using the V_REF pin capacitance specification from device datasheet, perform SI analysis on your board setup to determine the F_max of your system.

¹² 10M40 and 10M50 devices have dual purpose clock input pins at top/bottom I/O banks.

Internal Weak Pull-Up Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.

Table 17. Internal Weak Pull-Up Resistor for Intel^® MAX^® 10 Devices. Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO.
Symbol	Parameter	Condition	Min	Typ	Max	Unit
R__PU	Value of I/O pin (dedicated and dual-purpose) pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled	V_CCIO = 3.3 V ± 5%	7	12	34	kΩ
		V_CCIO = 3.0 V ± 5%	8	13	37	kΩ
		V_CCIO = 2.5 V ± 5%	10	15	46	kΩ
		V_CCIO = 1.8 V ± 5%	16	25	75	kΩ
		V_CCIO = 1.5 V ± 5%	20	36	106	kΩ
		V_CCIO = 1.2 V ± 5%	33	82	179	kΩ

Hot-Socketing Specifications

Table 18. Hot-Socketing Specifications for Intel^® MAX^® 10 Devices
Symbol	Parameter	Maximum
I_IOPIN(DC)	DC current per I/O pin	300 µA
I_IOPIN(AC)	AC current per I/O pin	8 mA ¹³

¹³ The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I_IOPIN| = C dv/dt, in which C is I/O pin capacitance and dv/dt is the slew rate.

Hysteresis Specifications for Schmitt Trigger Input

Intel^® MAX^® 10 devices support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate.

Table 19. Hysteresis Specifications for Schmitt Trigger Input for Intel^® MAX^® 10 Devices
Symbol	Parameter	Condition	Minimum	Unit
V_HYS	Hysteresis for Schmitt trigger input	V_CCIO = 3.3 V	180	mV
		V_CCIO = 2.5 V	150	mV
		V_CCIO = 1.8 V	120	mV
		V_CCIO = 1.5 V	110	mV

Figure 3. LVTTL/LVCMOS Input Standard Voltage Diagram

Figure 4. Schmitt Trigger Input Standard Voltage Diagram

I/O Standards Specifications

Tables in this section list input voltage (V_IH and V_IL), output voltage (V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O standards supported by Intel^® MAX^® 10 devices.

For minimum voltage values, use the minimum V_CCIO values. For maximum voltage values, use the maximum V_CCIO values.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Single-Ended I/O Standards Specifications

Table 20. Single-Ended I/O Standards Specifications for Intel^® MAX^® 10 Devices. To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.
I/O Standard	V_CCIO (V)			V_IL (V)		V_IH (V)		V_OL (V)	V_OH (V)	I_OL (mA)	I_OH (mA)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Max	Min	I_OL (mA)	I_OH (mA)
3.3 V LVTTL	3.135	3.3	3.465	–0.3	0.8	1.7	3.6	0.45	2.4	4	–4
3.3 V LVCMOS	3.135	3.3	3.465	–0.3	0.8	1.7	3.6	0.2	V_CCIO – 0.2	2	–2
3.0 V LVTTL	2.85	3	3.15	–0.3	0.8	1.7	V_CCIO + 0.3	0.45	2.4	4	–4
3.0 V LVCMOS	2.85	3	3.15	–0.3	0.8	1.7	V_CCIO + 0.3	0.2	V_CCIO – 0.2	0.1	–0.1
2.5 V LVTTL and LVCMOS	2.375	2.5	2.625	–0.3	0.7	1.7	V_CCIO + 0.3	0.4	2	1	–1
1.8 V LVTTL and LVCMOS	1.71	1.8	1.89	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	2.25	0.45	V_CCIO –0.45	2	–2
1.5 V LVCMOS	1.425	1.5	1.575	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2
1.2 V LVCMOS	1.14	1.2	1.26	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2
3.3 V Schmitt Trigger	3.135	3.3	3.465	–0.3	0.8	1.7	V_CCIO + 0.3	—	—	—	—
2.5 V Schmitt Trigger	2.375	2.5	2.625	–0.3	0.7	1.7	V_CCIO + 0.3	—	—	—	—
1.8 V Schmitt Trigger	1.71	1.8	1.89	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	—	—	—	—
1.5 V Schmitt Trigger	1.425	1.5	1.575	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	—	—	—	—
3.0 V PCI	2.85	3	3.15	—	0.3 × V_CCIO	0.5 × V_CCIO	V_CCIO + 0.3	0.1 × V_CCIO	0.9 × V_CCIO	1.5	–0.5

Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 21. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel^® MAX^® 10 Devices
I/O Standard	V_CCIO (V)			V_REF (V)			V_TT (V) ¹⁴
I/O Standard	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max
SSTL-2 Class I, II	2.375	2.5	2.625	1.19	1.25	1.31	V_REF – 0.04	V_REF	V_REF + 0.04
SSTL-18 Class I, II	1.7	1.8	1.9	0.833	0.9	0.969	V_REF – 0.04	V_REF	V_REF + 0.04
SSTL-15 Class I, II	1.425	1.5	1.575	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-135 Class I, II	1.283	1.35	1.45	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
HSTL-18 Class I, II	1.71	1.8	1.89	0.85	0.9	0.95	0.85	0.9	0.95
HSTL-15 Class I, II	1.425	1.5	1.575	0.71	0.75	0.79	0.71	0.75	0.79
HSTL-12 Class I, II	1.14	1.2	1.26	0.48 × V_CCIO ¹⁵	0.5 × V_CCIO ¹⁵	0.52 × V_CCIO ¹⁵	—	0.5 × V_CCIO	—
HSTL-12 Class I, II	1.14	1.2	1.26	0.47 × V_CCIO ¹⁶	0.5 × V_CCIO ¹⁶	0.53 × V_CCIO ¹⁶	—	0.5 × V_CCIO	—
HSUL-12	1.14	1.2	1.3	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	—	—	—

¹⁴ V_TT of transmitting device must track V_REF of the receiving device.

¹⁵ Value shown refers to DC input reference voltage, V_REF(DC).

¹⁶ Value shown refers to AC input reference voltage, V_REF(AC).

Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

Table 22. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel^® MAX^® 10 Devices. To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL-15 Class I specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.
I/O Standard	V_IL(DC) (V)		V_IH(DC) (V)		V_IL(AC) (V)		V_IH(AC) (V)		V_OL (V)	V_OH (V)	I_OL (mA)	I_OH (mA)
I/O Standard	Min	Max	Min	Max	Min	Max	Min	Max	Max	Min	I_OL (mA)	I_OH (mA)
SSTL-2 Class I	—	V_REF – 0.18	V_REF + 0.18	—	—	V_REF – 0.31	V_REF + 0.31	—	V_TT – 0.57	V_TT + 0.57	8.1	–8.1
SSTL-2 Class II	—	V_REF – 0.18	V_REF + 0.18	—	—	V_REF – 0.31	V_REF + 0.31	—	V_TT – 0.76	V_TT + 0.76	16.4	–16.4
SSTL-18 Class I	—	V_REF – 0.125	V_REF + 0.125	—	—	V_REF – 0.25	V_REF + 0.25	—	V_TT –0.475	V_TT + 0.475	6.7	–6.7
SSTL-18 Class II	—	V_REF – 0.125	V_REF + 0.125	—	—	V_REF – 0.25	V_REF + 0.25	—	0.28	V_CCIO – 0.28	13.4	–13.4
SSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	—	V_REF – 0.175	V_REF + 0.175	—	0.2 × V_CCIO	0.8 × V_CCIO	8	–8
SSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	—	V_REF – 0.175	V_REF + 0.175	—	0.2 × V_CCIO	0.8 × V_CCIO	16	–16
SSTL-135	—	V_REF – 0.09	V_REF + 0.09	—	—	V_REF – 0.16	V_REF + 0.16	—	0.2 × V_CCIO	0.8 × V_CCIO	—	—
HSTL-18 Class I	—	V_REF – 0.1	V_REF + 0.1	—	—	V_REF – 0.2	V_REF + 0.2	—	0.4	V_CCIO – 0.4	8	–8
HSTL-18 Class II	—	V_REF – 0.1	V_REF + 0.1	—	—	V_REF – 0.2	V_REF + 0.2	—	0.4	V_CCIO – 0.4	16	–16
HSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	—	V_REF – 0.2	V_REF + 0.2	—	0.4	V_CCIO – 0.4	8	–8
HSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	—	V_REF – 0.2	V_REF + 0.2	—	0.4	V_CCIO – 0.4	16	–16
HSTL-12 Class I	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	–0.24	V_REF – 0.15	V_REF + 0.15	V_CCIO + 0.24	0.25 × V_CCIO	0.75 × V_CCIO	8	–8
HSTL-12 Class II	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	–0.24	V_REF – 0.15	V_REF + 0.15	V_CCIO + 0.24	0.25 × V_CCIO	0.75 × V_CCIO	14	–14
HSUL-12	—	V_REF – 0.13	V_REF + 0.13	—	—	V_REF – 0.22	V_REF + 0.22	—	0.1 × V_CCIO	0.9 × V_CCIO	—	—

Differential SSTL I/O Standards Specifications

Differential SSTL requires a V_REF input.

Table 23. Differential SSTL I/O Standards Specifications for Intel^® MAX^® 10 Devices
I/O Standard	V_CCIO (V)			V_Swing(DC) (V)		V_X(AC) (V)			V_Swing(AC) (V)
I/O Standard	Min	Typ	Max	Min	Max¹⁷	Min	Typ	Max	Min	Max
SSTL-2 Class I, II	2.375	2.5	2.625	0.36	V_CCIO	V_CCIO/2 – 0.2	—	V_CCIO/2+ 0.2	0.7	V_CCIO
SSTL-18 Class I, II	1.7	1.8	1.9	0.25	V_CCIO	V_CCIO/2 – 0.175	—	V_CCIO/2+ 0.175	0.5	V_CCIO
SSTL-15 Class I, II	1.425	1.5	1.575	0.2	—	V_CCIO/2 – 0.15	—	V_CCIO/2 + 0.15	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)
SSTL-135	1.283	1.35	1.45	0.18	—	V_REF – 0.135	0.5 × V_CCIO	V_REF + 0.135	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)

¹⁷ The maximum value for V_SWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC) and V_IL(DC)).

Differential HSTL and HSUL I/O Standards Specifications

Differential HSTL requires a V_REF input.

Table 24. Differential HSTL and HSUL I/O Standards Specifications for Intel^® MAX^® 10 Devices
I/O Standard	V_CCIO (V)			V_DIF(DC) (V)		V_X(AC) (V)			V_CM(DC) (V)			V_DIF(AC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Typ	Max	Min	Typ	Max	Min
HSTL-18 Class I, II	1.71	1.8	1.89	0.2	—	0.85	—	0.95	0.85	—	0.95	0.4
HSTL-15 Class I, II	1.425	1.5	1.575	0.2	—	0.71	—	0.79	0.71	—	0.79	0.4
HSTL-12 Class I, II	1.14	1.2	1.26	0.16	V_CCIO	0.48 × V_CCIO	0.5 × V_CCIO	0.52 × V_CCIO	0.48 × V_CCIO	0.5 × V_CCIO	0.52 × V_CCIO	0.3
HSUL-12	1.14	1.2	1.3	0.26	—	0.5 × V_CCIO – 0.12	0.5 × V_CCIO	0.5 × V_CCIO + 0.12	0.4 × V_CCIO	0.5 × V_CCIO	0.6 × V_CCIO	0.44

Differential I/O Standards Specifications

Table 25. Differential I/O Standards Specifications for Intel^® MAX^® 10 Devices
I/O Standard	V_CCIO (V)			V_ID (mV)		V_ICM (V) ¹⁸			V_OD (mV) ¹⁹ ²⁰			V_OS (V) ¹⁹
I/O Standard	Min	Typ	Max	Min	Max	Min	Condition	Max	Min	Typ	Max	Min	Typ	Max
LVPECL ²¹	2.375	2.5	2.625	100	—	0.05	D_MAX ≤ 500 Mbps	1.8	—	—	—	—	—	—
						0.55	500 Mbps ≤ D_MAX ≤ 700 Mbps	1.8
						1.05	D_MAX > 700 Mbps	1.55
LVDS	2.375	2.5	2.625	100	—	0.05	D_MAX ≤ 500 Mbps	1.8	247	—	600	1.125	1.25	1.375
						0.55	500 Mbps ≤ D_MAX ≤ 700 Mbps	1.8
						1.05	D_MAX > 700 Mbps	1.55
BLVDS ²²	2.375	2.5	2.625	100	—	—	—	—	—	—	—	—	—	—
mini-LVDS ²³	2.375	2.5	2.625	—	—	—	—	—	300	—	600	1	1.2	1.4
RSDS ²³	2.375	2.5	2.625	—	—	—	—	—	100	200	600	0.5	1.2	1.5
PPDS (Row I/Os) ²³	2.375	2.5	2.625	—	—	—	—	—	100	200	600	0.5	1.2	1.4
TMDS²⁴	2.375	2.5	2.625	100	—	0.05	D_MAX ≤ 500 Mbps	1.8	—	—	—	—	—	—
						0.55	500 Mbps ≤ D_MAX ≤ 700 Mbps	1.8
						1.05	D_MAX > 700 Mbps	1.55
Sub-LVDS ²⁵	1.71	1.8	1.89	100	—	0.55	—	1.25	²⁶			0.8	0.9	1
SLVS	2.375	2.5	2.625	100	—	0.05	—	1.1	²⁶			²⁷
HiSpi	2.375	2.5	2.625	100	—	0.05	D_MAX ≤ 500 Mbps	1.8	—	—	—	—	—	—
						0.55	500 Mbps ≤ D_MAX ≤ 700 Mbps	1.8
						1.05	D_MAX > 700 Mbps	1.55

¹⁸ V_IN range: 0 V ≤ V_IN ≤ 1.85 V.

¹⁹ R_L range: 90 ≤ R_L ≤ 110 Ω.

²⁰ Low V_OD setting is only supported for RSDS standard.

²¹ LVPECL input standard is only supported at clock input. Output standard is not supported.

²² No fixed V_IN , V_OD , and V_OS specifications for Bus LVDS (BLVDS). They are dependent on the system topology.

²³ Mini-LVDS, RSDS, and Point-to-Point Differential Signaling (PPDS) standards are only supported at the output pins for Intel^® MAX^® 10 devices.

²⁴ Supported with requirement of an external level shift

²⁵ Sub-LVDS input buffer is using 2.5 V differential buffer.

²⁶ Differential output depends on the values of the external termination resistors.

²⁷ Differential output offset voltage depends on the values of the external termination resistors.

Switching Characteristics

This section provides the performance characteristics of Intel^® MAX^® 10 core and periphery blocks.

Core Performance Specifications

Clock Tree Specifications

Table 26. Clock Tree Specifications for Intel^® MAX^® 10 Devices
Device	Performance					Unit
Device	–I6	–A6, –C7	–I7	–A7	–C8	Unit
10M02	450	416	416	382	402	MHz
10M04	450	416	416	382	402	MHz
10M08	450	416	416	382	402	MHz
10M16	450	416	416	382	402	MHz
10M25	450	416	416	382	402	MHz
10M40	450	416	416	382	402	MHz
10M50	450	416	416	382	402	MHz

PLL Specifications

Table 27. PLL Specifications for Intel^® MAX^® 10 Devices. V_{CCD_PLL} should always be connected to V_CCINT through decoupling capacitor and ferrite bead.
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN ²⁸	Input clock frequency	—	5	—	472.5	MHz
f_INPFD	Phase frequency detector (PFD) input frequency	—	5	—	325	MHz
f_VCO ²⁹	PLL internal voltage-controlled oscillator (VCO) operating range	—	600	—	1300	MHz
f_INDUTY	Input clock duty cycle	—	40	—	60	%
t_{INJITTER_CCJ} ³⁰	Input clock cycle-to-cycle jitter	F_INPFD ≥ 100 MHz	—	—	0.15	UI
t_{INJITTER_CCJ} ³⁰	Input clock cycle-to-cycle jitter	F_INPFD < 100 MHz	—	—	±750	ps
f_{OUT_EXT} ²⁸	PLL output frequency for external clock output	—	—	—	472.5	MHz
f_OUT	PLL output frequency to global clock	–6 speed grade	—	—	472.5	MHz
		–7 speed grade	—	—	450	MHz
		–8 speed grade	—	—	402.5	MHz
t_OUTDUTY	Duty cycle for external clock output	Duty cycle set to 50%	45	50	55	%
t_LOCK	Time required to lock from end of device configuration	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically	After switchover, reconfiguring any non-post-scale counters or delays, or when `areset` is deasserted	—	—	1	ms
t_{OUTJITTER_PERIOD_IO} ³¹	Regular I/O period jitter	F_OUT ≥ 100 MHz	—	—	650	ps
t_{OUTJITTER_PERIOD_IO} ³¹	Regular I/O period jitter	F_OUT < 100 MHz	—	—	75	mUI
t_{OUTJITTER_CCJ_IO} ³¹	Regular I/O cycle-to-cycle jitter	F_OUT ≥ 100 MHz	—	—	650	ps
t_{OUTJITTER_CCJ_IO} ³¹	Regular I/O cycle-to-cycle jitter	F_OUT < 100 MHz	—	—	75	mUI
t_{PLL_PSERR}	Accuracy of PLL phase shift	—	—	—	±50	ps
t_ARESET	Minimum pulse width on areset signal.	—	10	—	—	ns
t_CONFIGPLL	Time required to reconfigure scan chains for PLLs	—	—	3.5 ³²	—	`SCANCLK` cycles
f_SCANCLK	`scanclk` frequency	—	—	—	100	MHz

Table 28. PLL Specifications for Intel^® MAX^® 10 Single Supply Devices. For V36 package, the PLL specification is based on single supply devices.
Symbol	Parameter	Condition	Max	Unit
t_{OUTJITTER_PERIOD_DEDCLK} ³¹	Dedicated clock output period jitter	F_OUT ≥ 100 MHz	660	ps
t_{OUTJITTER_PERIOD_DEDCLK} ³¹	Dedicated clock output period jitter	F_OUT < 100 MHz	66	mUI
t_{OUTJITTER_CCJ_DEDCLK} ³¹	Dedicated clock output cycle-to-cycle jitter	F_OUT ≥ 100 MHz	660	ps
t_{OUTJITTER_CCJ_DEDCLK} ³¹	Dedicated clock output cycle-to-cycle jitter	F_OUT < 100 MHz	66	mUI

Table 29. PLL Specifications for Intel^® MAX^® 10 Dual Supply Devices
Symbol	Parameter	Condition	Max	Unit
t_{OUTJITTER_PERIOD_DEDCLK} ³¹	Dedicated clock output period jitter	F_OUT ≥ 100 MHz	300	ps
t_{OUTJITTER_PERIOD_DEDCLK} ³¹	Dedicated clock output period jitter	F_OUT < 100 MHz	30	mUI
t_{OUTJITTER_CCJ_DEDCLK} ³¹	Dedicated clock output cycle-to-cycle jitter	F_OUT ≥ 100 MHz	300	ps
t_{OUTJITTER_CCJ_DEDCLK} ³¹	Dedicated clock output cycle-to-cycle jitter	F_OUT < 100 MHz	30	mUI

²⁸ This parameter is limited in the Intel^® Quartus^® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.

²⁹ The VCO frequency reported by the Intel^® Quartus^® Prime software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCO specification.

³⁰ A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.

³¹ Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.

³² With 100 MHz scanclk frequency.

Embedded Multiplier Specifications

Table 30. Embedded Multiplier Specifications for Intel^® MAX^® 10 Devices
Mode	Number of Multipliers	Power Supply Mode	Performance			Unit
Mode	Number of Multipliers	Power Supply Mode	–I6	–A6, –C7, –I7, –A7	–C8	Unit
9 × 9-bit multiplier	1	Single supply mode	198	183	160	MHz
9 × 9-bit multiplier	1	Dual supply mode	310	260	210	MHz
18 × 18-bit multiplier	1	Single supply mode	198	183	160	MHz
18 × 18-bit multiplier	1	Dual supply mode	265	240	190	MHz

Memory Block Performance Specifications

Table 31. Memory Block Performance Specifications for Intel^® MAX^® 10 Devices
Memory	Mode	Resources Used		Power Supply Mode	Performance			Unit
Memory	Mode	LEs	M9K Memory	Power Supply Mode	–I6	–A6, –C7, –I7, –A7	–C8	Unit
M9K Block	FIFO 256 × 36	47	1	Single supply mode	232	219	204	MHz
	FIFO 256 × 36	47	1	Dual supply mode	330	300	250	MHz
	Single-port 256 × 36	0	1	Single supply mode	232	219	204	MHz
	Single-port 256 × 36	0	1	Dual supply mode	330	300	250	MHz
	Simple dual-port 256 × 36 `CLK`	0	1	Single supply mode	232	219	204	MHz
	Simple dual-port 256 × 36 `CLK`	0	1	Dual supply mode	330	300	250	MHz
	True dual port 512 × 18 single `CLK`	0	1	Single supply mode	232	219	204	MHz
	True dual port 512 × 18 single `CLK`	0	1	Dual supply mode	330	300	250	MHz

Internal Oscillator Specifications

Table 32. Internal Oscillator Frequencies for Intel^® MAX^® 10 Devices. You can access to the internal oscillator frequencies in this table. The duty cycle of internal oscillator is approximately 45%–55%.
Device	Frequency			Unit
Device	Minimum	Typical	Maximum	Unit
10M02	55	82	116	MHz
10M04
10M08
10M16
10M25
10M40	35	52	77	MHz
10M50	35	52	77	MHz

UFM Performance Specifications

Table 33. UFM Performance Specifications for Intel^® MAX^® 10 Devices
Block	Mode	Interface	Device	Frequency		Unit
Block	Mode	Interface	Device	Minimum	Maximum	Unit
UFM	Avalon^® -MM slave	Parallel ³³	10M02 ³⁴	3.43	7.25	MHz
		Parallel ³³	10M04, 10M08, 10M16, 10M25, 10M40, 10M50	5	116	MHz
		Serial ³⁴	10M02, 10M04, 10M08, 10M16, 10M25	3.43	7.25	MHz
		Serial ³⁴	10M40, 10M50	2.18	4.81	MHz

³³ Clock source is derived from user, except for 10M02 device.

³⁴ Clock source is derived from 1/16 of the frequency of the internal oscillator.

ADC Performance Specifications

Single Supply Devices ADC Performance Specifications

Table 34. ADC Performance Specifications for Intel^® MAX^® 10 Single Supply Devices
Parameter		Symbol	Condition	Min	Typ	Max	Unit
ADC resolution		—	—	—	—	12	bits
ADC supply voltage		V_{CC_ONE}	—	2.85	3.0/3.3	3.465	V
External reference voltage		V_REF	—	V_{CC_ONE} – 0.5	—	V_{CC_ONE}	V
Sampling rate		F_S	Accumulative sampling rate	—	—	1	MSPS
Operating junction temperature range		T_J	—	–40	25	125	°C
Analog input voltage		V_IN	Prescalar disabled	0	—	V_REF	V
Analog input voltage		V_IN	Prescalar enabled ³⁵	0	—	3.6	V
Input resistance		R_IN	—	—	³⁶	—	—
Input capacitance		C_IN	—	—	³⁶	—	—
DC Accuracy	Offset error and drift	E_offset	Prescalar disabled	–0.2	—	0.2	%FS
	Offset error and drift	E_offset	Prescalar enabled	–0.5	—	0.5	%FS
	Gain error and drift	E_gain	Prescalar disabled	–0.5	—	0.5	%FS
	Gain error and drift	E_gain	Prescalar enabled	–0.75	—	0.75	%FS
	Differential non linearity	DNL	External V_REF, no missing code	–0.9	—	0.9	LSB
	Differential non linearity	DNL	Internal V_REF, no missing code	–1	—	1.7	LSB
	Integral non linearity	INL	—	–2	—	2	LSB
AC Accuracy	Total harmonic distortion	THD	F_IN = 50 kHz, F_S = 1 MHz, PLL	–65 ³⁷	—	—	dB
	Signal-to-noise ratio	SNR	F_IN = 50 kHz, F_S = 1 MHz, PLL	54 ³⁸	—	—	dB
	Signal-to-noise and distortion	SINAD	F_IN = 50 kHz, F_S = 1 MHz, PLL	53 ³⁹	—	—	dB
On-Chip Temperature Sensor	Temperature sampling rate	T_S	—	—	—	50	kSPS
On-Chip Temperature Sensor	Absolute accuracy	—	–40 to 125°C, with 64 samples averaging ⁴⁰	—	—	±10	°C
Conversion Rate ⁴¹	Conversion time	—	Single measurement	—	—	1	Cycle
			Continuous measurement	—	—	1	Cycle
			Temperature measurement	—	—	1	Cycle

³⁵ Prescalar function divides the analog input voltage by half. The analog input handles up to 3.6 V for the Intel^® MAX^® 10 single supply devices.

³⁶ Download the SPICE models for simulation.

³⁷ THD with prescalar enabled is 6dB less than the specification.

³⁸ SNR with prescalar enabled is 6dB less than the specification.

³⁹ SINAD with prescalar enabled is 6dB less than the specification.

⁴⁰ For the Intel^® Quartus^® Prime software version 15.0 and later, Modular ADC Core Intel^® FPGA IP and Modular Dual ADC Core Intel^® FPGA IP cores handle the 64 samples averaging. For the Intel^® Quartus^® Prime software versions prior to 14.1, you need to implement your own averaging calculation.

⁴¹ For more detailed description, refer to the Timing section in the Intel^® MAX^® 10 Analog-to-Digital Converter User Guide.

Dual Supply Devices ADC Performance Specifications

Table 35. ADC Performance Specifications for Intel^® MAX^® 10 Dual Supply Devices
Parameter		Symbol	Condition	Min	Typ	Max	Unit
ADC resolution		—	—	—	—	12	bits
Analog supply voltage		V_{CCA_ADC}	—	2.375	2.5	2.625	V
Digital supply voltage		V_CCINT	—	1.15	1.2	1.25	V
External reference voltage		V_REF	—	V_{CCA_ADC} – 0.5	—	V_{CCA_ADC}	V
Sampling rate		F_S	Accumulative sampling rate	—	—	1	MSPS
Operating junction temperature range		T_J	—	–40	25	125	°C
Analog input voltage		V_IN	Prescalar disabled	0	—	V_REF	V
Analog input voltage		V_IN	Prescalar enabled ⁴²	0	—	3	V
Analog supply current (DC)		I_{ACC_ADC}	Average current	—	275	450	µA
Digital supply current (DC)		I_CCINT	Average current	—	65	150	µA
Input resistance		R_IN	—	—	⁴³	—	—
Input capacitance		C_IN	—	—	⁴³	—	—
DC Accuracy	Offset error and drift	E_offset	Prescalar disabled	–0.2	—	0.2	%FS
	Offset error and drift	E_offset	Prescalar enabled	–0.5	—	0.5	%FS
	Gain error and drift	E_gain	Prescalar disabled	–0.5	—	0.5	%FS
	Gain error and drift	E_gain	Prescalar enabled	–0.75	—	0.75	%FS
	Differential non linearity	DNL	External V_REF, no missing code	–0.9	—	0.9	LSB
	Differential non linearity	DNL	Internal V_REF, no missing code	–1	—	1.7	LSB
	Integral non linearity	INL	—	–2	—	2	LSB
AC Accuracy	Total harmonic distortion	THD	F_IN = 50 kHz, F_S = 1 MHz, PLL	–70 ⁴⁴ ⁴⁵ ⁴⁶	—	—	dB
	Signal-to-noise ratio	SNR	F_IN = 50 kHz, F_S = 1 MHz, PLL	62 ⁴⁷ ⁴⁸ ⁴⁶	—	—	dB
	Signal-to-noise and distortion	SINAD	F_IN = 50 kHz, F_S = 1 MHz, PLL	61.5 ⁴⁹ ⁵⁰ ⁴⁶	—	—	dB
On-Chip Temperature Sensor	Temperature sampling rate	T_S	—	—	—	50	kSPS
On-Chip Temperature Sensor	Absolute accuracy	—	–40 to 125°C, with 64 samples averaging ⁵¹	—	—	±5	°C
Conversion Rate ⁵²	Conversion time	—	Single measurement	—	—	1	Cycle
			Continuous measurement	—	—	1	Cycle
			Temperature measurement	—	—	1	Cycle

⁴² Prescalar function divides the analog input voltage by half. The analog input handles up to 3 V input for the Intel^® MAX^® 10 dual supply devices.

⁴³ Download the SPICE models for simulation.

⁴⁴ Total harmonic distortion is –65 dB for dual function pin.

⁴⁵ THD with prescalar enabled is 6dB less than the specification.

⁴⁶ When using internal V_REF, THD = 66 dB, SNR = 58 dB and SINAD = 57.5 dB for dedicated ADC input channels.

⁴⁷ Signal-to-noise ratio is 54 dB for dual function pin.

⁴⁸ SNR with prescalar enabled is 6dB less than the specification.

⁴⁹ Signal-to-noise and distortion is 53 dB for dual function pin.

⁵⁰ SINAD with prescalar enabled is 6dB less than the specification.

⁵¹ For the Intel^® Quartus^® Prime software version 15.0 and later, Modular ADC Core and Modular Dual ADC Core IP cores handle the 64 samples averaging. For the Intel^® Quartus^® Prime software versions prior to 14.1, you need to implement your own averaging calculation.

⁵² For more detailed description, refer to the Timing section in the Intel^® MAX^® 10 Analog-to-Digital Converter User Guide.

Periphery Performance Specifications

This section describes the periphery performance, high-speed I/O, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

For more information about the high-speed and low-speed I/O performance pins, refer to the respective device pin-out files.

True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications

Table 36. True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel^® MAX^® 10 Dual Supply Devices. True **PPDS** transmitter is only supported at bottom I/O banks. Emulated **PPDS** transmitter is supported at the output pin of all I/O banks.
Symbol	Parameter	Mode	–I6, –A6, –C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	—	155	5	—	155	5	—	155	MHz
		×8	5	—	155	5	—	155	5	—	155	MHz
		×7	5	—	155	5	—	155	5	—	155	MHz
		×4	5	—	155	5	—	155	5	—	155	MHz
		×2	5	—	155	5	—	155	5	—	155	MHz
		×1	5	—	310	5	—	310	5	—	310	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	—	310	100	—	310	100	—	310	Mbps
		×8	80	—	310	80	—	310	80	—	310	Mbps
		×7	70	—	310	70	—	310	70	—	310	Mbps
		×4	40	—	310	40	—	310	40	—	310	Mbps
		×2	20	—	310	20	—	310	20	—	310	Mbps
		×1	10	—	310	10	—	310	10	—	310	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	—	150	5	—	150	5	—	150	MHz
		×8	5	—	150	5	—	150	5	—	150	MHz
		×7	5	—	150	5	—	150	5	—	150	MHz
		×4	5	—	150	5	—	150	5	—	150	MHz
		×2	5	—	150	5	—	150	5	—	150	MHz
		×1	5	—	300	5	—	300	5	—	300	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	—	300	100	—	300	100	—	300	Mbps
		×8	80	—	300	80	—	300	80	—	300	Mbps
		×7	70	—	300	70	—	300	70	—	300	Mbps
		×4	40	—	300	40	—	300	40	—	300	Mbps
		×2	20	—	300	20	—	300	20	—	300	Mbps
		×1	10	—	300	10	—	300	10	—	300	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁵³	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁵⁴	Output jitter (high-speed I/O performance pin)	—	—	—	425	—	—	425	—	—	425	ps
t_{x Jitter} ⁵⁴	Output jitter (low-speed I/O performance pin)	—	—	—	470	—	—	470	—	—	470	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

⁵³ TCCS specifications apply to I/O banks from the same side only.

⁵⁴ TX jitter is the jitter induced from core noise and I/O switching noise.

True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

Single Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

Table 37. True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel^® MAX^® 10 Single Supply Devices. True **RSDS** transmitter is only supported at bottom I/O banks. Emulated **RSDS** transmitter is supported at the output pin of all I/O banks.
Symbol	Parameter	Mode	–I6, –A6, –C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	—	50	5	—	50	5	—	50	MHz
		×8	5	—	50	5	—	50	5	—	50	MHz
		×7	5	—	50	5	—	50	5	—	50	MHz
		×4	5	—	50	5	—	50	5	—	50	MHz
		×2	5	—	50	5	—	50	5	—	50	MHz
		×1	5	—	100	5	—	100	5	—	100	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	—	100	100	—	100	100	—	100	Mbps
		×8	80	—	100	80	—	100	80	—	100	Mbps
		×7	70	—	100	70	—	100	70	—	100	Mbps
		×4	40	—	100	40	—	100	40	—	100	Mbps
		×2	20	—	100	20	—	100	20	—	100	Mbps
		×1	10	—	100	10	—	100	10	—	100	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	—	50	5	—	50	5	—	50	MHz
		×8	5	—	50	5	—	50	5	—	50	MHz
		×7	5	—	50	5	—	50	5	—	50	MHz
		×4	5	—	50	5	—	50	5	—	50	MHz
		×2	5	—	50	5	—	50	5	—	50	MHz
		×1	5	—	100	5	—	100	5	—	100	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	—	100	100	—	100	100	—	100	Mbps
		×8	80	—	100	80	—	100	80	—	100	Mbps
		×7	70	—	100	70	—	100	70	—	100	Mbps
		×4	40	—	100	40	—	100	40	—	100	Mbps
		×2	20	—	100	20	—	100	20	—	100	Mbps
		×1	10	—	100	10	—	100	10	—	100	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁵⁵	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁵⁶	Output jitter (high-speed I/O performance pin)	—	—	—	425	—	—	425	—	—	425	ps
t_{x Jitter} ⁵⁶	Output jitter (low-speed I/O performance pin)	—	—	—	470	—	—	470	—	—	470	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

Table 38. True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel^® MAX^® 10 Dual Supply Devices. True **RSDS** transmitter is only supported at bottom I/O banks. Emulated **RSDS** transmitter is supported at the output pin of all I/O banks.
Symbol	Parameter	Mode	–I6, –A6, –C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	—	155	5	—	155	5	—	155	MHz
		×8	5	—	155	5	—	155	5	—	155	MHz
		×7	5	—	155	5	—	155	5	—	155	MHz
		×4	5	—	155	5	—	155	5	—	155	MHz
		×2	5	—	155	5	—	155	5	—	155	MHz
		×1	5	—	310	5	—	310	5	—	310	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	—	310	100	—	310	100	—	310	Mbps
		×8	80	—	310	80	—	310	80	—	310	Mbps
		×7	70	—	310	70	—	310	70	—	310	Mbps
		×4	40	—	310	40	—	310	40	—	310	Mbps
		×2	20	—	310	20	—	310	20	—	310	Mbps
		×1	10	—	310	10	—	310	10	—	310	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	—	150	5	—	150	5	—	150	MHz
		×8	5	—	150	5	—	150	5	—	150	MHz
		×7	5	—	150	5	—	150	5	—	150	MHz
		×4	5	—	150	5	—	150	5	—	150	MHz
		×2	5	—	150	5	—	150	5	—	150	MHz
		×1	5	—	300	5	—	300	5	—	300	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	—	300	100	—	300	100	—	300	Mbps
		×8	80	—	300	80	—	300	80	—	300	Mbps
		×7	70	—	300	70	—	300	70	—	300	Mbps
		×4	40	—	300	40	—	300	40	—	300	Mbps
		×2	20	—	300	20	—	300	20	—	300	Mbps
		×1	10	—	300	10	—	300	10	—	300	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁵⁷	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁵⁸	Output jitter (high-speed I/O performance pin)	—	—	—	425	—	—	425	—	—	425	ps
t_{x Jitter} ⁵⁸	Output jitter (low-speed I/O performance pin)	—	—	—	470	—	—	470	—	—	470	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

⁵⁵ TCCS specifications apply to I/O banks from the same side only.

⁵⁶ TX jitter is the jitter induced from core noise and I/O switching noise.

⁵⁷ TCCS specifications apply to I/O banks from the same side only.

⁵⁸ TX jitter is the jitter induced from core noise and I/O switching noise.

Emulated RSDS_E_1R Transmitter Timing Specifications

Table 39. Emulated RSDS_E_1R Transmitter Timing Specifications for Intel^® MAX^® 10 Dual Supply Devices. Emulated **RSDS_E_1R** transmitter is supported at the output pin of all I/O banks.
Symbol	Parameter	Mode	–I6, –A6, –C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	—	85	5	—	85	5	—	85	MHz
		×8	5	—	85	5	—	85	5	—	85	MHz
		×7	5	—	85	5	—	85	5	—	85	MHz
		×4	5	—	85	5	—	85	5	—	85	MHz
		×2	5	—	85	5	—	85	5	—	85	MHz
		×1	5	—	170	5	—	170	5	—	170	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	—	170	100	—	170	100	—	170	Mbps
		×8	80	—	170	80	—	170	80	—	170	Mbps
		×7	70	—	170	70	—	170	70	—	170	Mbps
		×4	40	—	170	40	—	170	40	—	170	Mbps
		×2	20	—	170	20	—	170	20	—	170	Mbps
		×1	10	—	170	10	—	170	10	—	170	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	—	85	5	—	85	5	—	85	MHz
		×8	5	—	85	5	—	85	5	—	85	MHz
		×7	5	—	85	5	—	85	5	—	85	MHz
		×4	5	—	85	5	—	85	5	—	85	MHz
		×2	5	—	85	5	—	85	5	—	85	MHz
		×1	5	—	170	5	—	170	5	—	170	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	—	170	100	—	170	100	—	170	Mbps
		×8	80	—	170	80	—	170	80	—	170	Mbps
		×7	70	—	170	70	—	170	70	—	170	Mbps
		×4	40	—	170	40	—	170	40	—	170	Mbps
		×2	20	—	170	20	—	170	20	—	170	Mbps
		×1	10	—	170	10	—	170	10	—	170	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁵⁹	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁶⁰	Output jitter (high-speed I/O performance pin)	—	—	—	425	—	—	425	—	—	425	ps
t_{x Jitter} ⁶⁰	Output jitter (low-speed I/O performance pin)	—	—	—	470	—	—	470	—	—	470	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

⁵⁹ TCCS specifications apply to I/O banks from the same side only.

⁶⁰ TX jitter is the jitter induced from core noise and I/O switching noise.

True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications

Table 40. True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel^® MAX^® 10 Dual Supply Devices. True **mini-LVDS** transmitter is only supported at the bottom I/O banks. Emulated **mini-LVDS_E_3R** transmitter is supported at the output pin of all I/O banks.
Symbol	Parameter	Mode	–I6, –A6, –C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	—	155	5	—	155	5	—	155	MHz
		×8	5	—	155	5	—	155	5	—	155	MHz
		×7	5	—	155	5	—	155	5	—	155	MHz
		×4	5	—	155	5	—	155	5	—	155	MHz
		×2	5	—	155	5	—	155	5	—	155	MHz
		×1	5	—	310	5	—	310	5	—	310	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	—	310	100	—	310	100	—	310	Mbps
		×8	80	—	310	80	—	310	80	—	310	Mbps
		×7	70	—	310	70	—	310	70	—	310	Mbps
		×4	40	—	310	40	—	310	40	—	310	Mbps
		×2	20	—	310	20	—	310	20	—	310	Mbps
		×1	10	—	310	10	—	310	10	—	310	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	—	150	5	—	150	5	—	150	MHz
		×8	5	—	150	5	—	150	5	—	150	MHz
		×7	5	—	150	5	—	150	5	—	150	MHz
		×4	5	—	150	5	—	150	5	—	150	MHz
		×2	5	—	150	5	—	150	5	—	150	MHz
		×1	5	—	300	5	—	300	5	—	300	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	—	300	100	—	300	100	—	300	Mbps
		×8	80	—	300	80	—	300	80	—	300	Mbps
		×7	70	—	300	70	—	300	70	—	300	Mbps
		×4	40	—	300	40	—	300	40	—	300	Mbps
		×2	20	—	300	20	—	300	20	—	300	Mbps
		×1	10	—	300	10	—	300	10	—	300	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁶¹	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁶²	Output jitter (high-speed I/O performance pin)	—	—	—	425	—	—	425	—	—	425	ps
t_{x Jitter} ⁶²	Output jitter (low-speed I/O performance pin)	—	—	—	470	—	—	470	—	—	470	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

⁶¹ TCCS specifications apply to I/O banks from the same side only.

⁶² TX jitter is the jitter induced from core noise and I/O switching noise.

True LVDS Transmitter Timing

Single Supply Devices True LVDS Transmitter Timing Specifications

Table 41. True LVDS Transmitter Timing Specifications for Intel^® MAX^® 10 Single Supply Devices. True **LVDS** transmitter is only supported at the bottom I/O banks.
Symbol	Parameter	Mode	–C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency	×10	5	—	145	5	—	100	5	—	100	MHz
		×8	5	—	145	5	—	100	5	—	100	MHz
		×7	5	—	145	5	—	100	5	—	100	MHz
		×4	5	—	145	5	—	100	5	—	100	MHz
		×2	5	—	145	5	—	100	5	—	100	MHz
		×1	5	—	290	5	—	200	5	—	200	MHz
HSIODR	Data rate	×10	100	—	290	100	—	200	100	—	200	Mbps
		×8	80	—	290	80	—	200	80	—	200	Mbps
		×7	70	—	290	70	—	200	70	—	200	Mbps
		×4	40	—	290	40	—	200	40	—	200	Mbps
		×2	20	—	290	20	—	200	20	—	200	Mbps
		×1	10	—	290	10	—	200	10	—	200	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁶³	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁶⁴	Output jitter	—	—	—	1,000	—	—	1,000	—	—	1,000	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

Dual Supply Devices True LVDS Transmitter Timing Specifications

Table 42. True LVDS Transmitter Timing Specifications for Intel^® MAX^® 10 Dual Supply Devices. True **LVDS** transmitter is only supported at the bottom I/O banks.
Symbol	Parameter	Mode	–I6			–A6, –C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency	×10	5	—	360	5	—	340	5	—	310	5	—	300	MHz
		×8	5	—	360	5	—	360	5	—	320	5	—	320	MHz
		×7	5	—	360	5	—	340	5	—	310	5	—	300	MHz
		×4	5	—	360	5	—	350	5	—	320	5	—	320	MHz
		×2	5	—	360	5	—	350	5	—	320	5	—	320	MHz
		×1	5	—	360	5	—	350	5	—	320	5	—	320	MHz
HSIODR	Data rate	×10	100	—	720	100	—	680	100	—	620	100	—	600	Mbps
		×8	80	—	720	80	—	720	80	—	640	80	—	640	Mbps
		×7	70	—	720	70	—	680	70	—	620	70	—	600	Mbps
		×4	40	—	720	40	—	700	40	—	640	40	—	640	Mbps
		×2	20	—	720	20	—	700	20	—	640	20	—	640	Mbps
		×1	10	—	360	10	—	350	10	—	320	10	—	320	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	45	—	55	%
TCCS⁶⁵	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁶⁶	Output jitter	—	—	—	380	—	—	380	—	—	380	—	—	380	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	—	—	1	ms

⁶³ TCCS specifications apply to I/O banks from the same side only.

⁶⁴ TX jitter is the jitter induced from core noise and I/O switching noise.

⁶⁵ TCCS specifications apply to I/O banks from the same side only.

⁶⁶ TX jitter is the jitter induced from core noise and I/O switching noise.

Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications

Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications

Table 43. Emulated LVDS_E_3R Transmitter Timing Specifications for Intel^® MAX^® 10 Single Supply Devices. Emulated **LVDS_E_3R** transmitters are supported at the output pin of all I/O banks.
Symbol	Parameter	Mode	–C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	—	142.5	5	—	100	5	—	100	MHz
		×8	5	—	142.5	5	—	100	5	—	100	MHz
		×7	5	—	142.5	5	—	100	5	—	100	MHz
		×4	5	—	142.5	5	—	100	5	—	100	MHz
		×2	5	—	142.5	5	—	100	5	—	100	MHz
		×1	5	—	285	5	—	200	5	—	200	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	—	285	100	—	200	100	—	200	Mbps
		×8	80	—	285	80	—	200	80	—	200	Mbps
		×7	70	—	285	70	—	200	70	—	200	Mbps
		×4	40	—	285	40	—	200	40	—	200	Mbps
		×2	20	—	285	20	—	200	20	—	200	Mbps
		×1	10	—	285	10	—	200	10	—	200	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	—	100	5	—	100	5	—	100	MHz
		×8	5	—	100	5	—	100	5	—	100	MHz
		×7	5	—	100	5	—	100	5	—	100	MHz
		×4	5	—	100	5	—	100	5	—	100	MHz
		×2	5	—	100	5	—	100	5	—	100	MHz
		×1	5	—	200	5	—	200	5	—	200	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	—	200	100	—	200	100	—	200	Mbps
		×8	80	—	200	80	—	200	80	—	200	Mbps
		×7	70	—	200	70	—	200	70	—	200	Mbps
		×4	40	—	200	40	—	200	40	—	200	Mbps
		×2	20	—	200	20	—	200	20	—	200	Mbps
		×1	10	—	200	10	—	200	10	—	200	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁶⁷	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁶⁸	Output jitter	—	—	—	1,000	—	—	1,000	—	—	1,000	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications

Table 44. Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel^® MAX^® 10 Dual Supply Devices. Emulated **LVDS_E_3R**, **SLVS**, and **Sub-LVDS** transmitters are supported at the output pin of all I/O banks.
Symbol	Parameter	Mode	–I6, –A6, –C7, –I7			–A7			–C8			Unit
Symbol	Parameter	Mode	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	—	300	5	—	275	5	—	275	MHz
		×8	5	—	300	5	—	275	5	—	275	MHz
		×7	5	—	300	5	—	275	5	—	275	MHz
		×4	5	—	300	5	—	275	5	—	275	MHz
		×2	5	—	300	5	—	275	5	—	275	MHz
		×1	5	—	300	5	—	275	5	—	275	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	—	600	100	—	550	100	—	550	Mbps
		×8	80	—	600	80	—	550	80	—	550	Mbps
		×7	70	—	600	70	—	550	70	—	550	Mbps
		×4	40	—	600	40	—	550	40	—	550	Mbps
		×2	20	—	600	20	—	550	20	—	550	Mbps
		×1	10	—	300	10	—	275	10	—	275	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	—	150	5	—	150	5	—	150	MHz
		×8	5	—	150	5	—	150	5	—	150	MHz
		×7	5	—	150	5	—	150	5	—	150	MHz
		×4	5	—	150	5	—	150	5	—	150	MHz
		×2	5	—	150	5	—	150	5	—	150	MHz
		×1	5	—	300	5	—	300	5	—	300	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	—	300	100	—	300	100	—	300	Mbps
		×8	80	—	300	80	—	300	80	—	300	Mbps
		×7	70	—	300	70	—	300	70	—	300	Mbps
		×4	40	—	300	40	—	300	40	—	300	Mbps
		×2	20	—	300	20	—	300	20	—	300	Mbps
		×1	10	—	300	10	—	300	10	—	300	Mbps
t_DUTY	Duty cycle on transmitter output clock	—	45	—	55	45	—	55	45	—	55	%
TCCS⁶⁹	Transmitter channel-to-channel skew	—	—	—	300	—	—	300	—	—	300	ps
t_{x Jitter} ⁷⁰	Output jitter (high-speed I/O performance pin)	—	—	—	425	—	—	425	—	—	425	ps
t_{x Jitter} ⁷⁰	Output jitter (low-speed I/O performance pin)	—	—	—	470	—	—	470	—	—	470	ps
t_RISE	Rise time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_FALL	Fall time	20 – 80%, C_LOAD = 5 pF	—	500	—	—	500	—	—	500	—	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	—	1	—	—	1	—	—	1	ms

⁶⁷ TCCS specifications apply to I/O banks from the same side only.

⁶⁸ TX jitter is the jitter induced from core noise and I/O switching noise.

⁶⁹ TCCS specifications apply to I/O banks from the same side only.

⁷⁰ TX jitter is the jitter induced from core noise and I/O switching noise.

LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

Single Supply Devices LVDS Receiver Timing Specifications

Table 45. LVDS Receiver Timing Specifications for Intel^® MAX^® 10 Single Supply Devices. **LVDS** receivers are supported at all banks.
Symbol	Parameter	Mode	–C7, –I7		–A7		–C8		Unit
Symbol	Parameter	Mode	Min	Max	Min	Max	Min	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	145	5	100	5	100	MHz
		×8	5	145	5	100	5	100	MHz
		×7	5	145	5	100	5	100	MHz
		×4	5	145	5	100	5	100	MHz
		×2	5	145	5	100	5	100	MHz
		×1	5	290	5	200	5	200	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	290	100	200	100	200	Mbps
		×8	80	290	80	200	80	200	Mbps
		×7	70	290	70	200	70	200	Mbps
		×4	40	290	40	200	40	200	Mbps
		×2	20	290	20	200	20	200	Mbps
		×1	10	290	10	200	10	200	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	100	5	100	5	100	MHz
		×8	5	100	5	100	5	100	MHz
		×7	5	100	5	100	5	100	MHz
		×4	5	100	5	100	5	100	MHz
		×2	5	100	5	100	5	100	MHz
		×1	5	200	5	200	5	200	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	200	100	200	100	200	Mbps
		×8	80	200	80	200	80	200	Mbps
		×7	70	200	70	200	70	200	Mbps
		×4	40	200	40	200	40	200	Mbps
		×2	20	200	20	200	20	200	Mbps
		×1	10	200	10	200	10	200	Mbps
SW	Sampling window (high-speed I/O performance pin)	—	—	910	—	910	—	910	ps
SW	Sampling window (low-speed I/O performance pin)	—	—	1,110	—	1,110	—	1,110	ps
t_{x Jitter} ⁷¹	Input jitter	—	—	1,000	—	1,000	—	1,000	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	1	—	1	—	1	ms

Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

Table 46. LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel^® MAX^® 10 Dual Supply Devices. **LVDS**, **TMDS**, **HiSpi**, **SLVS**, and **Sub-LVDS** receivers are supported at all banks.
Symbol	Parameter	Mode	–I6, –A6, –C7, –I7		–A7		–C8		Unit
Symbol	Parameter	Mode	Min	Max	Min	Max	Min	Max	Unit
f_HSCLK	Input clock frequency (high-speed I/O performance pin)	×10	5	350	5	320	5	320	MHz
		×8	5	360	5	320	5	320	MHz
		×7	5	350	5	320	5	320	MHz
		×4	5	360	5	320	5	320	MHz
		×2	5	360	5	320	5	320	MHz
		×1	5	360	5	320	5	320	MHz
HSIODR	Data rate (high-speed I/O performance pin)	×10	100	700	100	640	100	640	Mbps
		×8	80	720	80	640	80	640	Mbps
		×7	70	700	70	640	70	640	Mbps
		×4	40	720	40	640	40	640	Mbps
		×2	20	720	20	640	20	640	Mbps
		×1	10	360	10	320	10	320	Mbps
f_HSCLK	Input clock frequency (low-speed I/O performance pin)	×10	5	150	5	150	5	150	MHz
		×8	5	150	5	150	5	150	MHz
		×7	5	150	5	150	5	150	MHz
		×4	5	150	5	150	5	150	MHz
		×2	5	150	5	150	5	150	MHz
		×1	5	300	5	300	5	300	MHz
HSIODR	Data rate (low-speed I/O performance pin)	×10	100	300	100	300	100	300	Mbps
		×8	80	300	80	300	80	300	Mbps
		×7	70	300	70	300	70	300	Mbps
		×4	40	300	40	300	40	300	Mbps
		×2	20	300	20	300	20	300	Mbps
		×1	10	300	10	300	10	300	Mbps
SW	Sampling window (high-speed I/O performance pin)	—	—	510	—	510	—	510	ps
SW	Sampling window (low-speed I/O performance pin)	—	—	910	—	910	—	910	ps
t_{x Jitter} ⁷²	Input jitter	—	—	500	—	500	—	500	ps
t_LOCK	Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration	—	—	1	—	1	—	1	ms

⁷¹ TX jitter is the jitter induced from core noise and I/O switching noise.

⁷² TX jitter is the jitter induced from core noise and I/O switching noise.

Memory Standards Supported by the Soft Memory Controller

Table 47. Memory Standards Supported by the Soft Memory Controller for Intel^® MAX^® 10 Devices. Contact your local sales representatives for access to the -I6 or -A6 speed grade devices in the Intel^® Quartus^® Prime software.
External Memory Interface Standard	Rate Support	Speed Grade	Voltage (V)	Max Frequency (MHz)
DDR3 SDRAM	Half	–I6	1.5	303
DDR3L SDRAM	Half	–I6	1.35	303
DDR2 SDRAM	Half	–I6	1.8	200
DDR2 SDRAM	Half	–I7 and –C7	1.8	167
LPDDR2 ⁷³	Half	–I6	1.2	200 ⁷⁴

⁷³ Intel^® MAX^® 10 devices support only single-die LPDDR2.

⁷⁴ To achieve the specified performance, constrain the memory device I/O and core power supply variation to within ±3%. By default, the frequency is 167 MHz.

Memory Output Clock Jitter Specifications

Intel^® MAX^® 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for Intel^® MAX^® 10 devices calibrate automatically.

The memory output clock jitter measurements are for 200 consecutive clock cycles.

The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a PHY clock network.

DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.

Table 48. Memory Output Clock Jitter Specifications for Intel^® MAX^® 10 Devices
Parameter	Symbol	–6 Speed Grade		–7 Speed Grade		Unit
Parameter	Symbol	Min	Max	Min	Max	Unit
Clock period jitter	t_JIT(per)	–127	127	–215	215	ps
Cycle-to-cycle period jitter	t_JIT(cc)	—	242	—	360	ps

Configuration Specifications

This section provides configuration specifications and timing for Intel^® MAX^® 10 devices.

JTAG Timing Parameters

Table 49. JTAG Timing Parameters for Intel^® MAX^® 10 Devices.
The values are based on C_L = 10 pF of `TDO`.

The affected Boundary Scan Test (BST) instructions are `SAMPLE`/`PRELOAD`, `EXTEST`, `INTEST`, and `CHECK_STATUS`.
Symbol	Parameter	Non-BST and non-CONFIG_IO Operation		BST and CONFIG_IO Operation		Unit
Symbol	Parameter	Minimum	Maximum	Minimum	Maximum	Unit
t_JCP	`TCK` clock period	40	—	50	—	ns
t_JCH	`TCK` clock high time	20	—	25	—	ns
t_JCL	`TCK` clock low time	20	—	25	—	ns
t_{JPSU_TDI}	JTAG port setup time	2	—	2	—	ns
t_{JPSU_TMS}	JTAG port setup time	3	—	3	—	ns
t_JPH	JTAG port hold time	10	—	10	—	ns
t_JPCO	JTAG port clock to output	—	15 (for V_CCIO = 3.3, 3.0, and 2.5 V) 17 (for V_CCIO = 1.8 and 1.5 V)	—	18 (for V_CCIO = 3.3, 3.0, and 2.5 V) 20 (for V_CCIO = 1.8 and 1.5 V)	ns
t_JPZX	JTAG port high impedance to valid output	—	15 (for V_CCIO = 3.3, 3.0, and 2.5 V) 17 (for V_CCIO = 1.8 and 1.5 V)	—	15 (for V_CCIO = 3.3, 3.0, and 2.5 V) 17 (for V_CCIO = 1.8 and 1.5 V)	ns
t_JPXZ	JTAG port valid output to high impedance	—	15 (for V_CCIO = 3.3, 3.0, and 2.5 V) 17 (for V_CCIO = 1.8 and 1.5 V)	—	15 (for V_CCIO = 3.3, 3.0, and 2.5 V) 17 (for V_CCIO = 1.8 and 1.5 V)	ns

Remote System Upgrade Circuitry Timing Specifications

Table 50. Remote System Upgrade Circuitry Timing Specifications for Intel^® MAX^® 10 Devices
Parameter	Device	Minimum	Maximum	Unit
t_{MAX_RU_CLK}	All	—	40	MHz
t_{RU_nCONFIG}	10M02, 10M04, 10M08, 10M16, 10M25	250	—	ns
t_{RU_nCONFIG}	10M40, 10M50	350	—	ns
t_{RU_nRSTIMER}	10M02, 10M04, 10M08, 10M16, 10M25	300	—	ns
t_{RU_nRSTIMER}	10M40, 10M50	500	—	ns

User Watchdog Internal Circuitry Timing Specifications

Table 51. User Watchdog Timer Specifications for Intel^® MAX^® 10 Devices. The specifications are subject to PVT changes.
Parameter	Device	Minimum	Typical	Maximum	Unit
User watchdog frequency	10M02, 10M04, 10M08, 10M16, 10M25	3.4	5.1	7.3	MHz
User watchdog frequency	10M40, 10M50	2.2	3.3	4.8	MHz

Uncompressed Raw Binary File (.rbf) Sizes

Table 52. Uncompressed .rbf Sizes for Intel^® MAX^® 10 Devices
Device	CFM Data Size (bits)
Device	Without Memory Initialization	With Memory Initialization
10M02	554,000	—
10M04	1,540,000	1,880,000
10M08	1,540,000	1,880,000
10M16	2,800,000	3,430,000
10M25	4,140,000	4,780,000
10M40	7,840,000	9,670,000
10M50	7,840,000	9,670,000

Internal Configuration Time

The internal configuration time measurement is from the rising edge of nSTATUS signal to the rising edge of CONF_DONE signal.

Table 53. Internal Configuration Time for Intel^® MAX^® 10 Devices (Uncompressed .rbf)
Device	Internal Configuration Time (ms)
	Unencrypted				Encrypted
	Without Memory Initialization		With Memory Initialization		Without Memory Initialization		With Memory Initialization
	Min	Max	Min	Max	Min	Max	Min	Max
10M02	0.3	1.7	—	—	1.7	5.4	—	—
10M04	0.6	2.7	1.0	3.4	5.0	15.0	6.8	19.6
10M08	0.6	2.7	1.0	3.4	5.0	15.0	6.8	19.6
10M16	1.1	3.7	1.4	4.5	9.3	25.3	11.7	31.5
10M25	1.0	3.7	1.3	4.4	14.0	38.1	16.9	45.7
10M40	2.6	6.9	3.2	9.8	41.5	112.1	51.7	139.6
10M50	2.6	6.9	3.2	9.8	41.5	112.1	51.7	139.6

Table 54. Internal Configuration Time for Intel^® MAX^® 10 Devices (Compressed .rbf). Compression ratio depends on design complexity. The minimum value is based on the best case (25% of original .rbf sizes) and the maximum value is based on the typical case (70% of original .rbf sizes).
Internal Configuration Time (ms)
Unencrypted/Encrypted
Without Memory Initialization		With Memory Initialization
Min	Max	Min	Max