AN 910: Intel Agilex Power Distribution Network Design Guidelines

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AN-910 | 2021.07.23

1. Intel Agilex Power Distribution Network Design Guidelines Overview

This application note provides information for the Intel^® Agilex™ device family power distribution network (PDN) design guidelines. A solid design guidelines for the Intel^® Agilex™ device family PDN including fixed decoupling capacitors on board and minimum simulation is proposed.

In the previous FPGA families (for example, the Intel^® Stratix^® 10 and Intel^® Arria^® 10 devices), the PDN tool was used along with power consumption data from the Early Power Estimator (EPE) and the pin connection guidelines to design and optimize board-level PDN. However, due to achieving non-feasible PDN design tool (decoupling capacitors) specifically for core, and with pessimistic results, the PDN tool is not used or supported for the Intel^® Agilex™ device family.

The information in this application note is intended to provide guidelines to allow you to successfully complete your PDN design, without requiring additional support.

2. Power Sequencing Guidelines

This section describes the recommended power sequencing guidelines of the Intel^® Agilex™ device family.

2.1. Power Rail Sequence Grouping in Power-Up Sequence (PUS)

In order to simplify the power sequencing of the FPGA, the voltage rails are divided into 3 groups as shown in the Table 1. The voltage rails of the lowest group comes up first in the PUS and go down last in the power-down sequence (PDS). Voltage rails in Group 1 comes up first, followed by Group 2, and then Group 3 in the PUS. Voltage rails in Group 3 comes down first, followed by Group 2, and then Group 1 in the PDS. All the voltage rails within each group are enabled and disabled at the same time.

Table 1 shows the Intel^® Agilex™ device family power rail grouping and the required PUS covering for both ES and production devices.

Table 1. Intel^® Agilex™ Device Power Rail Grouping for the PUS Purpose
Power Group	FPGA Core and Hard Processor System (HPS)	Additional Voltage Rails
Power Group	FPGA Core and Hard Processor System (HPS)	E-Tile	P-Tile	F-Tile	R-Tile
Group 1	V_CC V_CCP V_CCH V_{CCL_SDM} V_{CCH_SDM} V_{CCPLLDIG_SDM} V_{CCL_HPS} V_{CCPLLDIG_HPS}	V_{CCRT_GXE} V_{CC_HSSI_GXE} V_{CCRTPLL_GXE}	V_{CC_HSSI_GXP} V_{CCRT_GXP} V_{CCFUSE_GXP}	V_{CC_HSSI_GXF} V_{CCERT_FGT_GXF} V_{CCERT1_FHT_GXF} V_{CCERT2_FHT_GXF}	V_{CC_HSSI_GXR} V_{CCE_PLL_GXR} V_{CCRT_GXR} V_{CCE_DTS_GXR}
Group 2	V_CCPT V_{CCPLL_SDM} V_CCADC V_{CCPLL_HPS} V_{CCA_PLL} ¹	V_{CCH_GXE} V_{CCCLK_GXE}	V_{CCH_GXP} V_{CCCLK_GXP}	V_{CCFUSEWR_GXF} V_{CCCLK_GXF} V_{CCH_FGT_GXF} V_{CCEHT_FHT_GXF} V_{CCFUSECORE_GXF}	V_{CCED_GXR} V_{CCCLK_GXR} V_{CCHFUSE_GXR} V_{CCH_GXR}
Group 3	V_{CCA_PLL} ² V_{CCR_CORE} V_{CCIO_PIO_SDM} V_{CCIO_PIO} V_{CCFUSEWR_SDM} V_{CCIO_SDM} V_{CCIO_HPS}	—	—	—	—

The following lists the summary of the Intel^® Agilex™ device family required PUS:

PUS is a requirement, not a recommendation
PUS must be a controlled event (Group 1 > Group 2 > Group 3)
HBM PUS and PDS is defined by the JEDEC specification
VCCBAT can be powered up at any time
Configuration via Protocol (CvP) or autonomous hard IPs (HIPs) must be within 10 ms from the first power supply ramp up to the last power supply ramp up
All voltage rails must ramp up monotonically
All voltage rails must ramp up to the full t_RAMP specification (as stated in the device data sheet)
Do not drive I/O pins during a PUS

For more information, refer to the Power-Up Sequence Requirements section in the Intel^® Agilex™ Power Management User Guide.

¹ For AGF014 2486A Early Silicon.

² For AGF014 2486A production silicon.

2.2. Power-Down Sequencing (PDS)

Power-down sequencing (PDS) is the reverse of power-up sequencing (PUS). Power down has two cases—controlled power down (you do intend to perform power down, reset, or shutdown on the PCB) and uncontrolled power down (you do not intend to power down the PCB but because of malfunction or system failure, this happens).

PDS is always required and recommended in normal operation and controlled power down for the Intel^® Agilex™ device family. To perform the PDS in an controlled power-down event, you must follow the reverse for PUS. For more information, refer to the Intel^® Agilex™ Device Family Pin Connection Guidelines.

Intel^® Agilex™ device family has no uncontrolled PDS requirement for the core or fabric.

E-tile is not PDS-free. You must follow the recommended PDS. PDS is the reverse of PUS. Both VCCH_GXE and VCCCLK_GXE in Group 2 as shown in Figure 1 and Figure 2 must go down before VCC_HSSI_GXE in Group 1. For more information on the recommended power-down circuitry for E-tile in an uncontrolled power-down event, refer to AN 692: Power Sequencing Considerations for Intel^® Cyclone^® 10 GX, Intel^® Arria^® 10, Intel^® Stratix^® 10, and Intel^® Agilex™ Devices.

P-tile, R-tile, and F-tile are free of PDS in an uncontrolled power-down event.

The following lists the summary of the Intel^® Agilex™ recommended PDS:

PDS is required for a controlled power-down event. Follow the reverse of the PUS procedure.
PDS is not required but recommended for an uncontrolled power-down event unless it is stated.
- E-tile requires PDS for an uncontrolled power-down event.
All voltage rails must be <100 mV within 1 minute (this applies to a power loss condition as well).
If the above condition (<100 mV within 1 minute) is met, then the device reliability is guaranteed, and there will be no device damage or performance degradation.
Partial power down is not permitted.

3. Power Delivery Overview

This section covers the maximum power consumption budget specifically for the Intel^® Agilex™ device family. It also covers the recommended power tree or merged power rails on board to achieve minimum number of voltage regulators on board and reduce cost. The power rail names at the package-level along with their on-board (package pin) specification, rail tolerance, and the recommended step loads for the PDN time domain simulations are also covered in this section.

3.1. Power Architecture

3.1.1. Power Budget

Intel^® recommends you to use the Power Thermal Calculator (PTC) to determine the power for your applications. You must scale the recommended decoupling capacitors based on the scaling factor of the exact power consumption to the maximum power consumption.

The rule of thumb for scaling is to scale the number of suggested decoupling capacitors. For example, if your scale factor is 2, and you have 3 x 47µF capacitors as peripheral, the suggested decoupling capacitors on your board is 3/2 = (round it to 2) x 47µF.

Ensure that the recommended voltage regulator current in the board design must be larger than the total current for the merged power rails.

3.1.2. Power Tree

This section describes the recommended power tree for the Intel^® Agilex™ device family.

There are different types of Intel^® Agilex™ devices.

Intel^® Agilex™ (AGF) devices that cover only the E-tile and P-tile in the package (refer to Figure 1 and Figure 2).
Intel^® Agilex™ (AGF) devices that cover only the F-tile with only FGT (general-purpose transceivers) enabled (refer to Figure 3).
Intel^® Agilex™ (AGI) devices that cover the R-tile or F-tile, or both (F-tile has both FGT (general-purpose transceivers) enabled and FHT (high-speed transceivers) enabled (refer to Figure 3).
Intel^® Agilex™ (AGM) devices that cover the R-tile, F-tile, and HBM (the power tree will be provided in the future release).

3.1.2.1. Recommended Power Tree for the Intel Agilex Devices with only P-Tile and E-Tile in the Device Packages

The connection diagram in Figure 1 and Figure 2 show both recommended connections and required connections of the power rails on board. Required connections are mandatory for functionality. Not adhering to the required connection might produce unpredictable behavior. The recommended merged power rails and connections are aimed to reduce and optimize cost, area, and power in the platform design.

Figure 1 and Figure 2 show the recommended rail merger implemented in system with VCCIO of 1.2V. If a system is designed for VCCIO at 1.5V, a separate voltage regulator with a 1.5V output voltage within the same group must be assigned and designed for those I/O banks.

Figure 1. Recommended Intel^® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) SiliconThis power tree demonstrates the recommended FPGA PCB power rails grouping. You can use any recommended voltage regulators listed in FPGA Core Fabric VCC Voltage Regulator Selection as long as they meet the power rail specifications listed in Table 8.

Figure 2 is also valid for AGF012, AGF019, AGF022, AGF023, and AGF027 (with E-tile and P-tile) for production devices (unless it is mentioned in the power tree). Refer to Figure 1 for the recommended power of the AGF014 ES device.

Figure 2. Recommended Intel^® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production DevicesThis power tree demonstrates the recommended FPGA PCB power rails grouping. You can use any recommended voltage regulators listed in FPGA Core Fabric VCC Voltage Regulator Selection as long as they meet the power rail specifications listed in Table 8.

VREF_ADC

VREF_ADC (not mentioned in the power tree above) is treated as differential signal since it is input to the I/O buffer of ADC at FPGA. The in and out signals into FPGA is called VREF_ADCp and VREF_ADCn. The actual voltage of differential signal VREF_ADC is 1.25V. This voltage 1.25V comes from 1.8V in Group 2 with the use of a diode to convert 1.8V to 1.25V. This applies to both ES and production silicons. There is no restriction on VREF_ADC voltage level in the Intel^® Agilex™ device family compared to the Intel^® Stratix^® 10 device family that states VREF_ADC to be equal or lower voltage than VCCA_PLL.

VCCPT and VCCR_CORE: Differences between Intel^® Agilex™ AGF014 2486A ES and Production Silicons

To reduce power, there has been an effort to change the rail powering CRAM from 1.8V to 1.2V. Early silicon has 1.8V supply for VCCPT (VCCPT covers VCCR_CORE in package). However, in production silicon, this will change to separate VCCPT and VCCR_CORE power rails in package, with 1.2V power supply assigned for VCCR_CORE and 1.8V power supply assigned for VCCPT. There will also be a production package which is pin compatible to ES package and contains additional 1.2V balls to account for the additional supply. To avoid impact to boards which are already in PCB design phase, the ES package ballout already contains balls with VCCR_CORE of 1.2V in the Intel^® Agilex™ AGF014 ES packages. Therefore, ES to production silicon change should be transparent to board designers. The decoupling capacitor table provides decoupling capacitors specification separately for 1.2V VCCR_CORE supply. In production silicon, VCC_CORE is pin-out at package separately from VCCPT. However, in early silicon, both VCC_CORE and VCCPT power nets are combined at package and pin-out at package as VCCPT pins.

VCCA_PLL: Difference between Intel^® Agilex™ AGF014 2486A ES and Production Silicons

The power tree in Figure 1 stands for early silicon design where VCCA_PLL is 1.8V. For production silicon design, VCCA_PLL will drop to 1.2V (for lower power consumption), and a separate voltage regulator may be required for VCCA_PLL on board to support this power rail individually. This VCCA_PLL power rail which is in Group 3 for production silicon can be merged with 1.2V power rail in Group 3. The final voltage tolerance of the merged power rails must follow the most stringent power rail specification among all the power rails..

Power Tree Updates for Intel^® Agilex™ AGF014 2486A Production Silicon

To address the power rail changes in the production silicon, the power tree in Figure 1 will slightly change compared to the power tree in Figure 2. The changes are summarized below:

Separate VCCR_CORE from VCCPT.
Merge VCCR_CORE with VCCIO_PIO 1.2V power rail in Group 3 (P1V2_GR3).
Disconnect VCCA_PLL power rails from 1.8V power net in Group 2. The maximum supported current by voltage regulator for the updated power net 1.8V in Group 2 changes to 5A.
Add a new voltage regulator (maximum current 6A) into power tree in Group 2 to cover a 1.2V power net in Group 2. This new 1.2V power net in Group 2 is connected to VCCA_PLL (maximum current 5.68A).
VCCA_PLL shall be merged with VCCIO_1P2V power rail in Group 3, but an LC filter is added to isolate this power net from other power nets connected to the same rail. If you merge VCCA_PLL to VCCIO_1P2V in Group 3, the voltage noise tolerance for this VCCIO_1P2V power rail in Group 3 would change from ±5% to ±3% in Table 8.

3.1.2.2. Recommended Power Tree for the Intel Agilex AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Device Packages

Figure 3. Recommended Intel^® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon

This block diagram is also applicable for the Intel^® Agilex™ AGF devices with only F-tile (Only FGT transceivers enabled) in the package. However, you need to remove or disable all power rails in the power tree with power rails ending with _GXR and _FHT_GXF to exclude the R-tile and F-tile (FHT) from the power tree.
All power rails with naming _GXR refers to the R-tile power rails and all power rails with naming _GXF refers to the F-tile power rails.

3.2. Rail Merger Requirements

IP voltage rails of same nominal values within the same sequencing group can be merged assuming that the power delivery network to each package balls for each IP is designed with care to meet the tolerance specifications of that IP. Therefore, proper analysis and/or simulations should be done to ensure voltage drop and cross regulations are under control.

Other connections not mentioned in the Table 2 are recommended (not mandatory to follow) to optimize design cost and size.

Table 2. Required Rail Connections
	Rail 1	Rail 2	Notes
1	VCCH	VCC_HSSI_GXE	—
2	VCCH	VCCRT_GXE	Required to eliminate the need of PDS pull-down circuits. Connect via an LC filter. Use an inductor instead of ferrite bead to reduce voltage drop.
3	VCCH	VCCRTPLL_GXE	Required to eliminate the PDS circuits. Connect via a ferrite bead LC filter.
4	VCCH	VCC_HSSI_GXP	—
5	VCCH	VCCRT_GXP	VCC_HSSI_GXP and VCCRT_GXP should be connected to the same voltage regulator. Connect via an LC filter.
6	VCCH	VCC_HSSI_GXF/ VCCL_SDM	VCCH is 0.8V for AGI027-R29A (PKG: 2957A).
6	VCCH	VCC_HSSI_GXR/ VCCH_SDM	—
7	VCCH_SDM	VCCPLLDIG_HPS	Connect VCCPLLDIG_HPS to VCCH_SDM via a ferrite bead (BLM15AX300SN1 60mohm DCR 0402).
8	VCCH_SDM	VCC_HSSI_GXR	VCC_HSSI_GXR is 0.95V for AGI027-R29A (PKG: 2957A) ES version (require separate power rail, not merged with VCCH_SDM).
8	VCCH_SDM	VCC_HSSI_GXR	VCC_HSSI_GXR is 0.9V for AGI027-R29A (PKG: 2957A) production version and can be merged with VCCH_SDM without filter.
9	P1V8_GR2	VCCH_GXR	Each power in Rail 2 column is connected to power in Rail 1 column via a filter.
		VCCH_FGT_GXF
		VCCCLK_GXF
		VCCH_GXP
		VCCCLK_GXP
10	P1V8_GR2	VCCADC	Each power in Rail 2 column is connected to power in Rail 1 column via a filter.
		VCCPLL_SDM
		VCCPLL_HPS

As many power rails are merged on the motherboard, the requirement for an LC filter is necessary to ensure systems functionality especially for rail connections to sensitive circuits such as the phase-locked loop (PLL) and clock. Intel^® recommends you to follow the LC filter requirements.

VCCH for the E-tile and P-tile are not connected on package. You can separate them if they stay in the same power sequence group. However, VCCH_SDM should be connected to both to provide proper functionality.

3.3. Power Rails Specification

3.3.1. Power Nets

This section describes the Intel^® Agilex™ device family power nets and their subsystem details along with their board-level connection based on the recommended power trees described in the Power Tree.

3.3.1.1. Intel Agilex Package Power Nets and Subsystems Details

Table 3 shows the Intel^® Agilex™ FPGA Core/Fabric power nets and their subsystem details based on the recommended power tree in Figure 1 and Figure 2.

Table 3. Intel^® Agilex™ AGF (with only E-Tile and P-Tile), Intel^® Agilex™ AGF (with only F-Tile), and Intel^® Agilex™ AGI (with only F-Tile, R-Tile, or both) FPGA Package Power Rail Nets and Subsystem Details
System	Power Thermal Calculator (PTC) Rail Name	Board Connections	System Connections
FPGA	VCC	VCC 0.8V	Fabric core
FPGA/HPS AGF packages with E-tile and P-tile	VCCL_HPS		HPS core for –2 and –3 devices. Refer to the notes in Figure 1 and Figure 2.
FPGA/HPS AGF packages with E-tile and P-tile	VCCPLLDIG_HPS		HPS digital PLL for –2 and –3 devices. Refer to the notes in Figure 1 and Figure 2.
FPGA/PIO	VCCP		I/O 96 PHY
FPGA AGF packages with E-tile and P-tile	VCCH	VCCH 0.9V/P0V9_GR1	Rail for AIB-Bridge for FPGA AGF packages with E-tile and P-tile.
FPGA/SDM	VCCH_SDM	VCCH 0.9V/P0V9_GR1	SDM POR monitoring ball for VCCH
FPGA AGI packages (with F-tile or R-tile) or AGF packages (with F-tile)	VCCH	P0V8_GR1	Rail for AIB-Bridge for AGI packages with F-tile or R-tile or AGF packages with F-tile
FPGA/SDM	VCCL_SDM		SDM core
FPGA/SDM	VCCPLLDIG_SDM		SDM digital PLL
FPGA	VCCPT	P1V8_GR2	CRAM
FPGA/SDM	VCCADC		ADC
FPGA/SDM	VCCPLL_SDM		SDM analog PLL
FPGA/HPS	VCCPLL_HPS		HPS analog PLL
FPGA/SDM	VCCIO_PIO_SDM	P1V2_GR3	SDM POR monitor for VCCIO_PIO_SDM
FPGA/PIO	VCCIO_PIO		I/O 96 I/O buffer
FPGA	VCCR_CORE		Share with VCCIO only when I/O is DDR4/1.2V
FPGA	VCCA_PLL³		Main DDR PLL
FPGA/SDM	VCCIO_SDM	P1V8_GR3	SDM 1.8V I/O supply
FPGA/HPS	VCCIO_HPS		HPS I/O supply
FPGA/SDM	VCCBAT		—
FPGA/SDM	VCCFUSEWR_SDM	VCCFUSEWR_SDM	SDM fuse

Table 4. Intel^® Agilex™ E-Tile Power Rail Nets and Subsystem Details
PTC Rail Name	Board Connections	System Connections
VCCRT_GXE	VCCH 0.9V	E-Tile TX/RX transceiver analog
VCCRTPLL_GXE		E-Tile TX/RX transceiver analog
VCC_HSSI_GXE		E-Tile TX/RX transceiver analog
VCCH_GXE	VCCH_GXE	E-Tile TX/RX transceiver analog
VCCCLK_GXE	VCCCLK_GXE	E-Tile 2.5V I/O supply

Table 5. Intel^® Agilex™ P-Tile Power Rail Nets and Subsystem Details
PTC Rail Name	Board Connections	System Connections
VCC_HSSI_GXP	VCCH 0.9V	P-tile TX/RX transceiver digital
VCCFUSE_GXP		P-tile fuse
VCCRT_GXP		P-tile TX/RX transceiver analog
VCCH_GXP	P1V8_GR2	P-tile TX/RX analog
VCCCLK_GXP	P1V8_GR2	1.8 GPIO in P-tile

Table 6. Intel^® Agilex™ R-Tile Power Rail Nets and Subsystem Details
PTC Rail Name	Board Connections	System Connections
VCC_HSSI_GXR	P0V9_GR1	R-tile TX/RX transceiver digital For AGI027-R29A (PKG: 2957A) ES device, VCC_HSSI_GXR is 0.95V, hence requires a separate power rail For AGI027-R29A (PKG: 2957A) production device, VCC_HSSI_GXR is 0.9V, can be merged with VCCH
VCCED_GXR	P0V9_GR1	—
VCCE_PLL_GXR	VCCE_PLL_GXR	R-tile PLL reference signal power
VCCCLK_GXR	P1V0_GR2	R-tile DFE
VCCHFUSE_GXR	P1V0_GR2	R-tile fuse sense
VCCRT_GXR	VCCRT_GXR	R-tile TX/RX transceiver analog supply
VCCE_DTS_GXR	VCCE_PLL_GXR	—
VCCH_GXR	P1V8_GR2	R-tile high voltage (1.8V), connect to P1V8_GR2 via a filter

Table 7. Intel^® Agilex™ F-Tile Power Rail Nets and Subsystem Details
PTC Rail Name	Board Connections	System Connections
VCC_HSSI_GXF	P0V8_GR1	F-tile digital power supply, connect to P0V8_GR1 without filter
VCCERT_FGT_GXF	P1V0_GR1	F-tile general purpose analog supply
VCCERT1_FHT_GXF		F-tile high speed (HS) analog supply
VCCERT2_FHT_GXF		F-tile HS analog supply
VCCFUSECORE_GXF	P1V0_GR2	F-tile fuse supply
VCCFUSEWR_GXF	P1V0_GR2	F-tile fuse sense WR
VCCEHT_FHT_GXF	VCCEHT_FHT_GXF	F-tile HS high voltage supply
VCCH_FGT_GXF	P1V8_GR2	F-tile general purpose high voltage supply, connect to P1V8_GR2 via a filter
VCCLK_GXF	P1V8_GR2	F-tile DFT supply, connect to P1V8_GR2 via a filter

³ For AGF012 and AGF014 (with E-tile and P-tile) ES devices, this power rail is 1.8V (merged with P1V8_GR2). For production silicon, this power rail is 1.2V.

3.3.2. Power Rails Tolerance

This section describes the power rails tolerance and budget (AC + DC) on board at package level for the Intel^® Agilex™ device family. The rail tolerance must be met at the FPGA package ball. You must consider the following instructions to measure the rail tolerance:

VCC (core power net) measurement is taken at the FPGA remote differential sense lines (there is assigned differential sense pins at FPGA package) with the scope set to bandwidth limited at 20MHz.
VCCERT1_FHT_GXF has dedicated differential sense line at package level to compensate the IR drop at die level.
Other power rails (except for VCC (core power)), the rail tolerance must be met at the board vias on the bottom layer directly connected to the package power balls.
For other rails, place the voltage regulator sense point (if it has) in the FPGA pin field (in the package shadow), as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location.

Table 8. Intel^® Agilex™ Device PCB Power Rail Tolerance
Power Tree Rail Name	Vnom (Required) (V)	Recommended DC Setpoint (% of Vnom)	Recommended VR Ripple (% of Vnom)	Recommended AC Transient (% of Vnom)	Maximum DC + AC (% of Vnom) ⁴
VCC	VID (0.68, 0.8, 0.85)	±0.5%	±2.5%		±3%
VCCH 0.9V/ P0V9_GR1	0.9	±0.5%	±2.5%		±3%
P0V8_GR1	0.8	±0.5%	±2.5%		±3%
VCCH_GXE	1.1	±0.5%	±0.5%	±2%	±3%
VCCCLK_GXE	2.5	±0.5%	±0.5%	±3.5%	±5%
P1V8_GR2	1.8	±0.5%	±0.5%	±2%	3%
P1V2_GR3	1.2	±0.5%	±1%	±3.5%	5%
P1V8_GR3	1.8	±0.5%	±1%	±3.5%	5%
VCCFUSEWR_SDM	1.5 – 2.4	±0.5%	±1%	±3.5%	5%
VCCED_GXR	0.9	±0.5%	±2.5%		±3%
VCCE_PLL_GXR	1.0	±0.5%	±1.5%		±2%
P1V0_GR1: VCCERT_FGT_GXF VCCERT1_FHT_GXF VCCERT2_FHT_GXF ⁵ ⁶	1.0	±0.5%	±2%		±2.5%
P1V0_GR2: VCCCLK_GXR VCCH_FUSE_GXR VCCFUSECORE_GXF⁷/ VCCFUSEWR_GXF	1.0	±0.5%	±2.5%		±3%
VCCRT_GXR	1.0	±1%	±1.5%		±2.5%
VCCEHT_FHT_GXF	1.5	±0.5%	±2%		±2.5%
VCCFUSECORE_GXF/ VCCFUSEWR_GXF (standalone rail)	1.0	±0.5%	±4.5%	—	±5%
VCCH_FGT_GXF⁸	1.8	±0.5%	±2%		±2.5%
VCCH_GXR	1.8	±0.5%	±2%		±2.5%
VCCH_FUSE_GXR (standalone rail)	1.0	±0.5%	±1%	±3.5%	±5%

The actual specification for each power rail at package level is listed in the Intel^® Agilex™ Device Data Sheet. To reduce the PCB cost, some power rails are merged by using only a single voltage regulator to feed the power rails. The AC + DC specification in this design guideline is based on this design. However, you have the option to not combine the power rails on the PCB in your design.

You can combine the analog power rails on the PCB (provided that the nominal voltages are the same) by using a single voltage regulator on the PCB to feed the power rails to achieve the minimum cost. If you implement this design, you have to ensure the power rail specifications of the combined power rails on the PCB and voltage regulator must follow the most stringent specification of those package power rails.

Table 8 shows the power rail tolerance (AC + DC) based on the recommended power grouping in Table 1 and power tree in Figure 1 and Figure 2.

If a different power tree in Figure 1 and Figure 2 is used, the rail tolerance of each power net must fall into their recommended grouping category in Table 8.

⁴ The specification stands for DC + AC rail tolerance and must be measured and met at package pin/ball.

⁵ The VCCERT_FGT_GXF specification for this individual specific power rail is ±3% (AC + DC) at package pin. The VCCERT_FGT_GXF power rail is slightly more relaxed than the VCCERT_FHT_GXF power rail. This specification is also up to 1 MHz. The voltage regulator ripple specification is 5 mV p-p maximum. The AC noise specification above 1 MHz at package pin is ±15mV (30 mV p-p). This can be measured by a high pass filter probe above 1 MHz.

⁶ The VCCERT_FGT_GXF, VCCERT1_FHT_GXF, and VCCERT2_FHT_GXF each has its own separate power rail in the recommended power tree. However, you can merge these power rails (P1V0_GR1). The final specification of the merged power rail is the most stringent among those power rails. Intel^® recommends you to add filters to VCCERT_FGT_GXF and VCCERT1_FHT_GXF power rails.

⁷ This specification is when VCCFUSECORE_GXF is merged to other rails in P1V0_GR2.

⁸ The VCCH_FGT_GXF specification for this individual power rail per Intel^® Agilex™ Device Data Sheet is ±2.5% (DC + AC). This applies up to 1 MHz (use of probe with low pass filter at 1 MHz at package pin, the voltage regulator ripple specification is 5 mV p-p maximum). The AC noise specification above 1 MHz at package pin is ±15 mV (30 mV p-p). This can be measured by a high pass filter probe above 1 MHz.

3.3.3. Power Nets and Transient Specifications

Rail transient provided in the Table 9 is used to design and simulate the board level. Choose the recommended load slew rates and step load at FPGA package ball below for PCB-level PDN system simulations and design. Table 9 shows the maximum tolerable step load at FPGA package pin. The recommended step load in Table 9 is connected to FPGA package ball along with the PCB post-layout model (with decoupling capacitors and voltage regulator model excluding package and silicon/die model) in an EDA tool for time domain simulation to meet rail tolerance of respective power net in Table 8 at FPGA package ball.

Table 9 shows for the recommended step load at package ball and step load’s slew rate.

Note: The step load suggested in Table 9 is for a normal application and worst case operation in FPGA and tiles. Step load can also be scaled if the dynamic current of the target power rail in PTC is smaller than the step load in Table 9.

To address the worst step load for other packages, you can also use the recommended AGF012/AGF014 step load in Table 9 for AGF006/AGF008 device packages. The AGF006/AGF008 device packages have the smallest fabric/core in the Intel^® Agilex™ device family compared to the AGF012/AGF014 devices with the medium core/fabric size. For that reason, Intel^® recommends you to adopt the AGF012/AGF014 step load for the AGF006/AGF008 devices (although it might be slightly non-realistic), but more details will be listed for these packages in Table 9 in the future. For the same reason, you can also use the AGF027/AGF023/AGF022/AGI027/AGI023/AGI022 step load (addressing the large core/fabric packages) in Table 9 for AGF019/AGI019 device packages.

Table 9. Intel^® Agilex™ Device Family Transient and Step Load Specifications at Package Pin
Package Power Rails	At Package Balls (Step Load)	DI/dt at Package Balls (for Board Design)-Slew Rate	Notes
Package Power Rails	DI (A)-Step Load	DI/dt (A/µs)-Slew Rate	Notes
VCC Core: AGF012/AGF014	17	200	This is the most stringent based on simulation models.
VCC Core: AGF027/AGF023/AGF022 and AGI027/AGI023/AGI022	32.5	325	This is the most stringent based on simulation models.
VCCP	1.56	6.8	Step current is for 4x I/O banks together at each side of package (if the device has 8x I/O banks—4x I/O banks at each side of package—you should use 2x step current to cover all I/O banks).
VCCPT	2.4	12	—
VCCIO_PIO	0.645	10.8	Current specification is per I/O bank. Each I/O bank consists of 96 x I/Os. More I/O banks can join the same voltage regulator but current specification stays per I/O bank.
VCCA_PLL	0.25	5	Per each I/O bank.
VCCH	1.12	4.8	Step current at package ball per each AIB Bridge. The number of AIB Bridge is calculated based on number of tiles in package.
VCCRT_GXE	0.88	35.2	Per E-tile
VCCRTPLL_GXE	0.3	6	Per E-tile
VCC_HSSI_GXP	1.6	20	Per P-tile
VCCRT_GXP	1.56	15	Slowest step load but largest current amplitude. Per P-tile.
VCCRT_GXP	0.5	10	Fastest step load but slowest current amplitude. Per P-tile.
VCCH_GXP	0.37	7.4	Per P-tile
VCC_HSSI_GXF	0.825	30.55	Per F-tile
VCCERT_FGT_GXF	0.228	22.8	Per single FGT—F-tile channel
	0.935	1.33	For 8 x FGT—F-tile channels
	1.87	1.24	For 16 x FGT—F-tile channels
VCCH_FGT_GXF	0.031	31	Per single FGT—F-tile channel
	0.18	0.26	For 8 x FGT—F-tile channels
	0.37	0.25	For 16 x FGT—F-tile channels
VCCERT2_FHT_GXF	0.072	0.36	Per single FHT—F-tile channel
VCCERT2_FHT_GXF	0.216	0.72	For 4 x FHT—F-tile channels
VCCERT1_FHT_GXF	0.480	7.5	Per single FHT—F-tile channel
VCCERT1_FHT_GXF	1.44	4.8	For 4 x FHT—F-tile channels
VCCEHT_FHT_GXF	0.36	5	Per single FHT—F-tile channel
VCCEHT_FHT_GXF	1.1	3.7	For 4 x FHT—F-tile channels
VCC_HSSI_GXR	1.585	52.83	Per R-tile
VCCRT_GXR	2.47	6.58
VCCH_GXR	0.026	12.56

You must also notice the following:

Step current at package pin is only provided for critical power rails due to either having high current/power profile at die or being highly sensitive. Intel^® recommends you to do transient/time domain PDN simulation by using this step load for these critical power rails in Table 9 to ensure you will meet the voltage specification at package pin. If the voltage specification is not met at package pin, decoupling capacitors must be adjusted.
Intel^® do not provide step current for other power rails not mentioned in Table 9. Those power rails are called non-critical power rail due to having less sensitivity or low current profile/power consumption at silicon. Intel^® do not recommend time domain PDN analysis for non-critical power rails. Non-critical power rails PDN design suggested in this application note is guaranteed.
Intel^® recommends you to perform DC IR drop analysis for all power rails.

3.4. Decoupling Capacitors Recommendation

Solid and recommended FPGA decoupling capacitors requirement on board-level PCB are listed in this section in the table format for all power nets and based on the maximum FPGA power consumption and the recommended power trees. The table does not include recommended decoupling/bulk capacitors at voltage regulators. You must select the voltage regulator capacitors (bulk decoupling capacitors) based on the data sheet specification from the voltage regulator supplier and required specifications by Intel^® such as the maximum voltage regulator ripple and maximum total current support for that specific power rail or combined power rails. You must perform the PDN transient simulation if your design is not following the recommendation.

You must follow the recommended decoupling capacitors along with the power rail grouping and recommended voltage regulator on the PCB to ensure your are meeting the power rail tolerance and specification at package ball. For boards/PCBs that consume less power than the maximum power consumption, you must scale the decoupling capacitors by ratio of the board power consumption to the maximum power consumption per power rail. However, transient PDN simulation must be performed to ensure meeting the power rail tolerance at package ball.

3.4.1. Intel Agilex AGF012/AGF014, Intel Agilex AGI027/AGI023/AGI022, and Intel Agilex AGF027/AGF023/AGF022 FPGA Packages Board-Level Decoupling Capacitors Summary

Table 10 shows the PCB recommended FPGA decoupling capacitor requirement for the Intel^® Agilex™ AGF012/AGF014 (medium package size), Intel^® Agilex™ AGI027/AGI023/AGI022, and Intel^® Agilex™ AGF027/AGF023/AGF022 large device packages.

Fabric or core decoupling capacitors are highly dependent on the size of the core or fabric (LE and number of GPIO pins) in the package. Intel^® plans to add more packages to Table 10 in the future release to address decoupling capacitors solutions for other Intel^® Agilex™ devices.

To address PCB decoupling capacitors for other packages, you can also use the recommended AGF012/AGF014 decoupling capacitors in Table 10 for the AGF006/AGF008 device packages. The AGF006/AGF008 device packages have the smallest fabric/core in the Intel^® Agilex™ device family compared to the AGF012/AGF014 devices with medium core/fabric size. For that reason, adopting the AGF012/AGF014 decoupling capacitors for the AGF006/AGF008 devices might be slightly over designing, but highly recommended until we address more packages in Table 10 in the future release. For the same reason, you can also implement the AGF027/AGF023/AGF022/AGI027/AGI023/AGI022 decoupling capacitors (addressing the large core/fabric packages) in Table 10 for the AGF019/AGI019 device packages.

Decoupling capacitor recommendations for each tile is valid for any size of packages.

Table 10. Intel^® Agilex™ AGF012/AGF014, Intel^® Agilex™ AGI027/AGI023/AGI022, and Intel^® Agilex™ AGF027/AGF023/AGF022 FPGA Decoupling Capacitors Summary
System	Intel^® Agilex™ Power and Thermal Calculator (PTC) Rail Name	Bottom-side Capacitors		FPGA Periphery Capacitors		Notes
System		Thick PCB (>65 mil thickness)	Thin PCB (≤65 mil thickness)	Thick PCB (>65 mil thickness)	Thin PCB (≤65 mil thickness)	Notes
FPGA/PIO AGF012/AGF014	VCC	9x 47uF 0805	5x 47uF 0805	6x 47uF 0805	3x 47uF 0805	Place thick 0805 (47uF) capacitors inside bottom-side cavity. Use 47uF 0805 periphery capacitors on top-layer near FPGA.
FPGA/PIO AGF012/AGF014	VCCP	9x 47uF 0805	5x 47uF 0805	6x 47uF 0805	3x 47uF 0805
FPGA/PIO AGF012/AGF014	VCCR_CORE	1x 1uF 0201	1x 1uF 0201	N/A	N/A	—
FPGA/HPS	VCCPLLDIG_HPS	1x 1uF 0201	1x 1uF 0201	N/A	N/A	—
FPGA/HPS	VCCL_HPS	2x 10uF 0402 or 3x 4.7uF 0201	2x 10uF 0402 or 3x 4.7uF 0201	1x 22uF 0603	1x 22uF 0603	For SoC-centric designs.
FPGA	VCCH	4x 22uF (0603 or 0402) or 9x 10uF 0402	4x 22uF (0603 or 0402) or 9x 10uF 0402	2x 47uF 0805	2x 47uF 0805	Place thick 0603 (22uF) capacitors inside bottom-side cavity.
FPGA/SDM	VCCH_SDM	1x 1uF 0201	1x 1uF 0201	Same as VCCH	Same as VCCH	—
FPGA/SDM	VCCL_SDM	2x 1uF 0201	2x 1uF 0201	N/A	N/A	—
FPGA/SDM	VCCPLLDIG_SDM	1x 1uF 0201	1x 1uF 0201	LC filter capacitors	LC filter capacitors	—
FPGA	VCCPT	2x 4.7uF 0201	2x 4.7uF 0201	LC filter capacitors	LC filter capacitors	—
FPGA/PIO	VCCA_PLL	2x 10uF 0402	2x 10uF 0402	LC filter capacitors	LC filter capacitors	—
FPGA/SDM	VCCADC	1x 4.7uF 0402 or 0201	1x 4.7uF 0402 or 0201	LC filter capacitors	LC filter capacitors	—
FPGA/SDM	VCCPLL_SDM	2x 4.7uF 0402 or 0201	2x 4.7uF 0402 or 0201	LC filter capacitors	LC filter capacitors	—
FPGA/HPS	VCCPLL_HPS	2x 4.7uF 0402 or 0201	2x 4.7uF 0402 or 0201	LC filter capacitors	LC filter capacitors	—
FPGA/SDM	VCCIO_PIO_SDM	N/A	N/A	N/A	N/A	—
FPGA/PIO	VCCIO_PIO	2x 4.7uF 0402	2x 4.7uF 0402	1x 10uF 0402	1x 10uF 0402	Per channel
FPGA/SDM	VCCIO_SDM	1x 1uF 0201	1x 1uF 0201	N/A	N/A	—
FPGA/HPS	VCCIO_HPS	1x 1uF 0201	1x 1uF 0201	N/A	N/A	—
FPGA/SDM	VCCFUSEWR_SDM	1x 1uF 0201	1x 1uF 0201	N/A	N/A	—
FPGA/PIO AGI027/AGI023/AGI022 and AGF027/AGF023/AGF022	VCC	8x 100 uF 0805 + 4x 47uF 0805	6x 100uF 0805 + 4x 47uF 0805	12x 100uF 0805 + 10x 47uF 0805	10x 100uF 0805 + 8x 47uF 0805	Place 0805 capacitors inside the bottom-side cavity. Place 0402 in the FPGA pin field.
FPGA/PIO AGI027/AGI023/AGI022 and AGF027/AGF023/AGF022	VCCP	8x 100 uF 0805 + 4x 47uF 0805	6x 100uF 0805 + 4x 47uF 0805	12x 100uF 0805 + 10x 47uF 0805	10x 100uF 0805 + 8x 47uF 0805
FPGA/PIO AGI027/AGI023/AGI022 and AGF027/AGF023/AGF022	VCCR_CORE	2x 4.7uF 0201		1x 10uF 0402		—

3.4.2. Intel Agilex E-Tile Board-Level Decoupling Capacitors Summary

Table 11. Intel^® Agilex™ E-Tile Decoupling Capacitors Summary per Tile
Intel^® Agilex™ PTC Rail Name	Bottom-side Capacitors		FPGA Periphery Capacitors		Notes
Intel^® Agilex™ PTC Rail Name	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Notes
VCCRT_GXE	6x 4.7uF 0201	6x 4.7uF 0201	LC filter capacitors	LC filter capacitors	—
VCCRTPLL_GXE	2x 0201 1uF	2x 0201 1uF	LC filter capacitors	LC filter capacitors	—
VCC_HSSI_GXE	3x 10uF 0402 or 10x 4.7uF 0201	3x 10uF 0402 or 10x 4.7uF 0201	N/A	N/A	—
VCCH_GXE	2x 4.7uF 0201	2x 4.7uF 0201	5x 100uF 0805 + 1x 22uF 0603	5x 100uF 0805 + 1x 22uF 0603	—
VCCCLK_GXE	1x 1uF 0201	1x 1uF 0201	N/A	N/A	—

Although it is not required to use the recommended decoupling capacitors and LC filters for unused E-tile, Intel^® recommends you to use at least one of each suggested decoupling capacitors for the bottom-side capacitors if the E-tile is not used.

If you plan to run the E-Tile based on OTN protocol standards, please contact the Intel^® Premier Support and quote ID #"1509475736" (which is the HSDES case that contains the Intel^® contact who can provide more information). A step-by-step guideline will be submitted to you to update/adjust the PCB decoupling capacitors for E-tile (only for VCCRT_GXE and VCCRTPLL_GXE power rails) to support the OTN application.

3.4.3. Intel Agilex P-Tile Board-Level Decoupling Capacitors Summary

Table 12. Intel^® Agilex™ P-Tile Decoupling Capacitors Summary per Tile
Intel^® Agilex™ PTC Rail Name	Bottom-side Capacitors		FPGA Periphery Capacitors		Notes
Intel^® Agilex™ PTC Rail Name	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Notes
VCC_HSSI_GXP	1x 10uF 0402	1x 10uF 0402	N/A	N/A	—
VCCFUSE_GXP	1x 1uF 0201	1x 1uF 0201	N/A	N/A	For multiple P-tiles in the device package, use 1x 0402 4.7uF per 2 P-tile.
VCCRT_GXP	6x 4.7uF 0201	6x 4.7uF 0201	LC filter capacitors	LC filter capacitors	Can also use 11x 1uF 0201 instead for bottom-side capacitors.
VCCH_GXP	1x 1uF 0201	1x 1uF 0201	LC filter capacitors	LC filter capacitors	—
VCCCLK_GXP	1x 1uF 0201	1x 1uF 0201	LC filter capacitors	LC filter capacitors	—

Although it is not required to use the recommended decoupling capacitors and LC filters for unused P-tile, Intel^® recommends you to use at least one of each suggested decoupling capacitors for the bottom-side capacitors if the P-tile is not used.

3.4.4. Intel Agilex F-Tile Board-Level Decoupling Capacitors Summary

Table 13. Intel^® Agilex™ F-Tile Decoupling Capacitors Summary per Tile
Intel^® Agilex™ PTC Rail Name	Bottom-side Capacitors		FPGA Periphery Capacitors		Notes
Intel^® Agilex™ PTC Rail Name	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Notes
VCC_HSSI_GXF	2x 10uF 0402		2x 47uF 0805		Per each F-tile
VCCERT_FGT_GXF	2x 10uF 0402		4x 47uF 0805		Per each F-tile
VCCERT2_FHT_GXF	1x 10uF 0402		N/A		Per each F-tile
VCCERT1_FHT_GXF	2x 10uF 0402		2x 47uF 0805		Per each F-tile
VCCH_FGT_GXF	2x 10uF 0402		N/A		Per each F-tile
VCCEHT_FHT_GXF	2x 10uF 0402		N/A		Per each F-tile
VCCCLK_GXF	2x 10uF 0402		N/A		Per each F-tile
VCCFUSEWR_GXF	1x 1uF 0201		N/A		Per each F-tile
VCCFUSECORE_GXF	1x 4.7uF 0201		N/A		Per each F-tile

3.4.5. Intel Agilex R-Tile Board-Level Decoupling Capacitors Summary

Table 14. Intel^® Agilex™ R-Tile Decoupling Capacitors Summary per Tile
Intel^® Agilex™ PTC Rail Name	Bottom-side Capacitors		FPGA Periphery Capacitors		Notes
Intel^® Agilex™ PTC Rail Name	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Thick PCB (≥65 mil thickness)	Thin PCB (≤65 mil thickness)	Notes
VCC_HSSI_GXR	2x 10uF 0402		2x 47uF 0805		Per each R-tile
VCCE_PLL_GXR	1x 4.7uF 0201		N/A		Per each R-tile
VCCE_DTS_GXR	1x 4.7uF 0201		N/A		Per each R-tile
VCCRT_GXR	4x 10uF 0402		2x 47uF 0805		Per each R-tile.
VCCRT_GXR	4x 10uF 0402		2x 220uF 1206 + 3x 100uF 0805		Per each R-tile: If LDO voltage regulator is used for this power rail.
VCCH_GXR	1x 10uF 0402		1x 47uF 0805		Per each R-tile.
VCCED_GXR	1x 10uF 0402		1x 47uF 0805		Per each R-tile
VCCCLK_GXR	2x 10uF 0402		N/A		Per each R-tile
VCCHFUSE_GXR	2x 10uF 0402		N/A		Per each R-tile

This recommended decoupling capacitors solution has been verified along with the use of the recommended switching voltage regulator or LDO in the Figure 3 power tree. You can use other switching voltage regulators or LDOs as long as you meet the PCB power rail tolerance specification in Table 8. Intel^® recommends performing the PCB time domain simulation by using the step load in Table 9 for critical power rails. Intel^® do not support customers' PCB PDN time domain simulation. It is your responsibility to use the data and specifications in this document along with the simulation guidance in the Board Power Delivery Network Simulations chapter to perform the PDN time domain simulation.

4. Board Power Delivery Network Recommendations

This section describes other recommended power delivery network designs including the voltage regulator selection and filtering circuitry for power rails that are fed by a common voltage regulator. The design example in this section shows the development kits designed in-house.

This section also describes board decoupling capacitor placement example on board.

4.1. Board Decoupling Capacitors Guide

In addition to OPD (as LSC and DSC), the Intel^® Agilex™ device family also offers a cavity site or state to place large size back side capacitors as close as possible to the die or package to improve transient voltage droop response and reduce second or third voltage droop. A total of 15 decoupling capacitors (refer to Table 10, the bottom side capacitors for VCC core and VCCH) can be added into the Intel^® Agilex™ AGF014 Development Kit Board cavity including 9x 0805 47uF (for VCC core) and 6x 0603 22uF (for VCCH) as shown in Figure 4.

Figure 4 is an example of a decoupling capacitor placement scheme or connection within cavity on the top-layer for a PCB designed for the Intel^® Agilex™ AGF014 PCIe* Development Kit without socket and the use of micro via. The top layer in Figure 4 is assigned for VCC core power and the GND pins on top layer within the decoupling capacitor mounting are connected to the second layer (ground) through a micro via.

Figure 4. Back-side Board Cavity with Large Size Decoupling Capacitors for PCB without Socket, Thin Stackup, and the Use of Micro Via ( Intel^® Agilex™ AGF014 PCIe* Development Kit)

Because of the location of the cavity capacitors on the bottom side, several GND balls can’t have vias in pad, for stackup without the use of micro via. To ensure that we do not reduce the package current capability, and that we have a low-return inductance path, add a ground island on the top layer connecting those floating balls to adjacent GND vias, as illustrated in Figure 5.

Figure 5 is an example of decoupling capacitors scheme or connection within the cavity on the top layer for a PCB designed of Intel^® Agilex™ AGF014 Signal Integrity Development Kit without socket and the use of only through via for GND pins.

Figure 5. Back-side Board Cavity with Large Size Decoupling Capacitors, Thick Stackup, and the Use of Through Via ( Intel^® Agilex™ AGF014 Signal Integrity Development Kit)

In addition, other recommended 0201 and 0402 decoupling capacitors can be placed in the via field (FPGA pin field) on bottom layer inside the package shadow. The board side decoupling capacitors (FPGA periphery) recommendation for all rails can be placed either on top layer or bottom layer close to the edge of FPGA device.

This is a summary of the recommended decoupling capacitors placement within cavity for the Intel^® Agilex™ AGF012 and AGF014 device family:

VCC core cavity decoupling capacitors on bottom side:
- Thick PCB: 9x 0805 47µF
- Thin PCB: 5x 0805 47µF
VCCH cavity decoupling capacitors on bottom side: 4x 0603 22µF
- Option for VCCH: Some 0603 capacitors can be allocated to VCC or VCCIO_PIO/VCCPT depending on power consumption.
Note: The power tree and number of decoupling capacitors within the cavity on the Intel^® Agilex™ development kit boards may be slightly different than what has been recommended in this application note due to early release of silicon and guideline. The recommended power tree, guideline, and decoupling capacitors in this application note has been well established and validated by measurement for the final device production.

It is due to reliability to have the cavity area on top layer to be free of components due to OPD in package. However, pads or other coppers are allowed in this area on top layer. This means you can place as much capacitors if they fit into the cavity area on the bottom layer connecting capacitors to top layer through via.

4.2. FPGA Core Fabric VCC Voltage Regulator Selection

Intel^® recommends you to use the industry standard common footprints for power stages. This provides you the flexibility to choose between six different vendors during the validation phases. This also allows you to choose the vendor that best fit your PCB performance and cost targets without impacting the program schedule. The vendors that offer power stages for core in the industry standard common footprints are:

Intel^® Enpirion^®
MPS
Infineon
Fairchild
TI
Intersil
ADI
LTC

The following controllers have been validated for operation and communication with the Intel^® Agilex™ Power Management Controller Tool and added to the existing list of supported controllers and power stages.

The recommended VCC core voltage regulators in Table 15 are available in the Intel^® Quartus^® Prime software for your selection. Intel^® has already qualified these voltage regulators for the VID application. The PMBus communication is already validated by Intel^® .

Table 15. List of Supported Controllers and Power Stages
Vendor	Controller	Power Stage	Number of Phase
Intel^® Enpirion^® / Intel^®	ED8401	ET6160 (60A)	4
MPS	MPS2975/2972	MP86956A (60A)	5
Intersil/Renesas	ISL68236	ISL99227 (60A)	5
ADI	LTC3888-1	LTC7051 (60A)	4

Validated VR controllers from the Intel^® Stratix^® 10 device are still supported too.

The following power tree is being tested on internal boards (development kits). Hence, Intel^® recommends you to follow this VCC core voltage regulator diagram.

Figure 6. VCC/VCCP Core Voltage Regulator Design Implemented on the Intel^® Agilex™ AGF014 2486A FPGA Development Kits

4.3. Remote Sense Connections

Die sense pins are provided for the core fabric voltage regulator. The voltage regulator sense line for VCC core must be connected to the differential pair sense lines or pins provided on the package. The voltage regulator feedback inputs shall be connected to this FPGA die remote sense lines.

For all other voltage regulators related to other power rails or groups, the remote sense shall be placed inside the via or pin field under the die shadow as close as physically possible to the geometrical center of the corresponding power balls. Note that the voltage rail specification provided in Table 8 are valid only when sensing at this remote sense location, for example, on the board back side, on the vias connected to the package power balls.

You are required to use sense lines for Intel^® Agilex™ core, including the VID and multi-voltage designs. You are also required to add sense line to the F-tile transceivers power rail design because of tight specifications. VCCERT1_FHT_GXF power rails have dedicated sense pins at package level.

Note: For those power rails which do not have dedicated sense pins at package level, the IR drop can still be compensated by using a voltage regulator with the sense feedback pin. To find the sense pins, you must do the IR drop analysis along with plotting power/current distribution of that specific power rail at package level to find the pins which are located further from the voltage regulator and have the maximum IR drop.

Note: Any sense line used on the board for that specific power rail must be placed before LC filter. If a sense line is placed after LC filter, it will result in oscillation to the rails and an unstable voltage that is an input to the voltage regulator feedback pin function. If the power rail is using LDO, LC filter is not required.

4.4. Load Line Requirements

Load line is optional for Intel^® Agilex™ device family packages. The load line requirements will be updated for future Intel^® Agilex™ device family.

4.5. VCC Core Board Current Slew Rate

The VCC core fabric has a very high current slew rate. But some of that is filtered out by the metal-insulator-metal (MIM) capacitors as they provide the lowest impedance to the load because of their proximity. With addition of OPDs, most of the remaining fast edges are filtered out, leaving the board cavity capacitors and voltage regulator capacitors to handle only a fraction of the die level current.

You must ensure the PDN can deliver the current specified at the package balls. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails describes the recommended PCB system-level simulation to ensure the voltage tolerance or specification at package balls are met through the design.

5. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails

The part number selected for ferrite bead (FB) and inductance (L) in this chapter are the parts which are recommended by Intel^® . However, you can select different part numbers as long as the inductance/impedance at certain frequency, resistance, and other parameters of the new part is similar to recommended FB/L part (similar inductance/impedance and similar to lower resistance within frequency range mentioned in the data sheet of recommended part).

P1V8_GR2 Filters Recommendation for Device Fabric

The connections below are recommended for the P1V8_GR2_FLTR voltage rails for noise filtering. P1V8_GR2_FLTR consists of VCCADC, VCCPLL_SDM, and VCCPLL_HPS.

Figure 7. VCCADC, VCCPLL_SDM, and VCCPLL_HPS Filter Recommendation

Figure 8. VCCPT LC Filter Recommendation

The following figure shows the filter recommendation for VCCA_PLL in 1.2V VCCIO power rail.

Figure 9. VCCA_PLL Filter Recommendation

5.1. P-Tile Rail LC Filter Board Scheme and Connection

The filtering topology in Figure 10, Figure 11, and Figure 12 are recommended for the P-tile voltage rails (VCCCLK_GXP, VCCH_GXP, VCCRT_GXP) in the Power Tree for noise filtering purpose. The filter can be placed as close to FPGA as periphery capacitors in the recommended decoupling capacitors table in the Decoupling Capacitors Recommendation. In addition to the LC filter, you must also add the bottom or backside capacitors recommended in the decoupling capacitors table in the Decoupling Capacitors Recommendation within pin or via field on the bottom layer.

Figure 10. Filter Recommendation for VCCCLK_GXP

Figure 11. Filter Recommendation for VCCH_GXP

Figure 12. Filter Recommendation for VCCRT_GXP

5.2. E-Tile Rail LC Filter Board Scheme and Connection

The E-tile has a strict connection requirement to eliminate the need for power-down sequencing (PDS) control circuits. With the connections in Figure 13 and Figure 14, the E-tile eliminates the PDS requirement existing in the Intel^® Stratix^® 10 device family—no pull-down discharge FETs or resistors on voltage rails are required. The filter can be placed as close to FPGA as periphery capacitors in Table 10.

Figure 13. Connection Requirement and Filter Recommendation for VCCRT_GXE

Figure 14. Connection Requirement and Filter Recommendation for VCCRTPLL_GXE

5.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator

The LC filter recommendation in this chapter is not required for the F-tile power rails if you meet the voltage regulator (VR) ripple requirement in Table 16. Intel^® recommends using the LTC7151S voltage regulator to meet very tight noise specifications for VCCERT1_FHT_GXF and VCCERT2_FHT_GXF. You can use any other voltage regulators for the F-tile power rails as long as you meet the voltage regulator ripple specifications by selecting a proper voltage regulator. If you do not meet the VR ripple specification in Table 16 by using a noisy voltage regulator, Intel^® recommends using the LC filters in this chapter to block the high noise.

Table 16. Maximum Ripple Requirements for the F-Tile Analog Power Rails
Power Rail	Maximum Ripple (mVp-p)
VCCERT_FGT_GXF	5
VCCERT1_FHT_GXF	5
VCCERT2_FHT_GXF	5
VCCH_FGT_GXF	7
VCCEHT_FHT_GXF	7

Figure 15. Filter Recommendation for VCCH_FGT_GXFUnder the condition of using the noisy switching voltage regulator.

Figure 16. Filter Recommendation for VCCERT_FGT_GXFInductor MPN: SL1616A-R10MHF, under the condition of using noisy switching voltage regulator.

Figure 17. Filter Recommendation for VCCERT1_FHT_GXFInductor MPN: SL1616A-R10MHF, under the condition of using noisy switching voltage regulator.

Figure 18. Filter Recommendation for VCCERT2_FHT_GXFUnder the condition of using noisy switching voltage regulator.

Figure 19. Filter Recommendation for VCCEHT_FHT_GXFUnder the condition of using noisy switching voltage regulator.

5.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator

The R-tile requires a strict connection requirement to eliminate the need for power-down sequencing (PDS) control circuits. Using the board connections shown below, the R-tile removes the PDS requirement (such as the PDS requirement in the Intel^® Stratix^® 10 device family)—no pull-down discharge FETs or resistors on voltage rails is required. Therefore, the Intel^® Agilex™ device is a PDS-free FPGA.

For the VCCRT_GXR rail that is designed with the recommended LTC7151S voltage regulator (500 KHZ switching frequency is recommended), with a very tight noise specification, you do not need to add filter to this power rail (refer to the recommended power tree). However, if noisy switching voltage regulator is used, an elaborate filter design is required to dampen the noise in the power rail. Perform the PDN transient simulation to validate this power rail design against the specifications. Intel^® recommends you to follow the power tree and voltage regulators in Figure 3.

If you are using the LDO voltage regulator to meet the tight noise specification for this power rail, the recommended LDO is 2x ADP1765 and it is not needed to add LC filter when using LDO.

The maximum voltage regulator (VR) voltage ripple allowed for the VCCRT_GXR is 5mV and for VCCH_GXR is 7mV. If you do not meet this VR ripple specification for the R-tile power rails by selecting a noisy VR, Intel^® recommends using the recommended LC filters to block the noise.

Figure 20. Connection Requirement and Filter Recommendation for VCCH_GXR

6. PCB PDN Design Guideline for Unused Tiles

This chapter describes the PDN design guidelines for unused tiles on PCB design. For more information, refer to the Intel^® Agilex™ Device Family Pin Connection Guidelines.

6.1. PDN Design Guideline for Unused E-Tile

All E-tile power rails (ending with _GXE) must be powered on PCB even if the E-tile is not used in your board design. However, due to only small static/bypass current usage, the recommended decoupling capacitors in Table 11 for E-tile power rails in this document are not required on PCB. You must still meet the voltage specification at package pin for the E-tile power rails by selecting a proper voltage regulator (such as low ripple, DC setpoint, recommended VR bulk capacitors, etc) and considering the static/bypass current.

6.2. PDN Design Guideline for Unused P-Tile

All P-tile power rails (ending with _GXP) must be powered on PCB even if the P-tile is not used in your board design. However, due to only small static/bypass current usage, the recommended decoupling capacitors in Table 12 for the P-tile power rails in this document are not required on PCB. You must still meet the voltage specification at package pin for the P-tile power rails by selecting a proper voltage regulator (such as low ripple, DC setpoint, recommended VR bulk capacitors, etc) and considering the static/bypass current.

6.3. PDN Design Guideline for Unused R-Tile

If R-tile is not used on your PCB design, all the R-tile power rails (ending with _GXR: VCC_HSSI_GXR, VCCH_GXR, VCCED_GXR, VCCRT_GXR, VCCE_DTS_GXR, VCCE_PLL_GXR, VCCHFUSE_GXR, and VCCCLK_GXR) can be connected to GND. You must disconnect them from the power tree. VCCH in the power tree must still be powered on using the recommended decoupling capacitors listed in this document.

6.4. PDN Design Guideline for Unused F-Tile

If the entire F-tile is not used on your PCB design, all F-tile power rails (ending with _GXF) can be connected to GND. You must disconnect them from the power tree. VCCH in the power tree must still be powered on with the recommended decoupling capacitors listed in this document.

If only the high-speed 116G FHT transceivers/channels are not used in the F-tile, the F-tile power rails (ending with _FHT_GXF) in the power tree can be connected to GND. All other power rails remaining in F-tile must be powered on according to the specification by using the recommended decoupling capacitors listed in this document.

7. PCB Voltage Regulator Recommendation for PCB Power Rails

Intel^® recommends the Intel^® Agilex™ PCB-based designs to use the Intel^® Enpirion^® voltage regulators because of its capability, efficiency, and performance which have been validated on various Intel^® Agilex™ device family boards. Although you can use other voltage regulators, you are advised to use tested and trusted power solutions to remove the burden of validating other vendor solutions. This is to ensure that you can focus your bandwidth on validating and optimizing the FPGA intrinsic performances.

The following shows the recommended voltage regulators for some of the PCB power rails (refer to the power trees in Figure 1, Figure 2, and Figure 3). However, you are not limited to only use them. You can use any other voltage regulators as long as you meet the PCB power rail tolerance and specification in Table 8 measured at package pin. Intel^® does not support customers' PCB PDN time domain simulations. It is your responsibility to use the data and specifications in this document along with the guidance in Board Power Delivery Network Simulations chapter to perform PDN time domain simulation.

P1V2_GR3

The recommended voltage regulator solution for P1V2_GR3 is the Intel^® Enpirion^® Power Solutions EM2140P01Q1 40A PowerSoC.

VCCH 0.9V/P0V9_GR1

The recommended voltage regulator solution for 0.9V power rail is the Intel^® Enpirion^® Power SolutionsEM2260P01QI 60A PowerSoC.

VCCH_GXE

The recommended voltage regulator solution for VCCH_GXE is the Intel^® Enpirion^® EN29A0QI 10A PowerSoC.

VCCCLK_GXE

The recommended voltage regulator solution for VCCCLK_GXE is the Intel^® Enpirion^® EN5311QI 1A.

P0V8_GR1

The recommended voltage regulator solution for 0.8V power rail in Group 1 is the Intel^® Enpirion^® EN5311QI 1A or EM2130L02 QI 30A, depending on the device and the recommended power tree.

P1V8_GR2

The recommended voltage regulator solution for P1V8_GR2 is the Intel^® Enpirion^® EM2120H01QI 20A PowerSoC.

P1V8_GR3

The recommended voltage regulator solution for P1V8_GR3 is the Intel^® Enpirion^® EN5311QI 1A or EN6363QI.

VCCFUSEWR_SDM

The recommended voltage regulator solution for VCCFUSEWR_SDM is the Intel^® Enpirion^® EP5348UI 400mA.

8. Board Power Delivery Network Simulations

In this section, the PDN post-layout simulation is shown in Figure 21 for any Intel^® Agilex™ device family board design and system-level PDN simulation.

Figure 21. Methodology for Device PDN and Transient Noise AnalysisStep load at the package pin is injected to the PCB model to meet voltage droop (DC + AC) at the package pin.

Intel^® recommends you to follow the above-mentioned guidelines to design all power rails on the PCB with the recommended decoupling capacitors, voltage regulators, and LC filtering. In the post-layout phase, it is recommended to do the IR drop and transient (time domain) PDN analysis for PCB only. This means, unconventionally, we do not recommend impedance target and frequency target analysis (frequency domain simulation) for the Intel^® Agilex™ device.

To ensure the PDN design performance is within the required tolerance or specification in Table 8, time domain post-layout PDN simulation for some critical power nets such as VCC core, VCCP, VCCPT, VCCIO_PIO, VCCH, and power rails for E-tile, P-tile, F-tile, and R-tile must be performed.

PDN time domain simulation is only performed on PCB from voltage regulator to package ball. Therefore, package, OPDs, and on-chip models are not required for the PDN time domain simulation.

The following steps show the time domain PDN simulation (as shown in Figure 22):

Obtain the implemented VRM SPICE model for the target power rail.
Extract post-layout PCB model (HSPICE or scattering parameters by using tools such as PowerSI) of the PCB with decoupling capacitors and LC filtering from the voltage regulator (including VRM recommended bulk decoupling capacitors by vendor) to package pin (if use of scattering parameters, the PCB model shall be extracted from DC up to 1GHz). Intel recommends you to convert scattering parameters to circuit model by use of any broadband Spice or IDEM tool to avoid problematic simulation. To avoid simulation divergence, you shall include the small to medium decoupling capacitors on PCB extraction and define ports for the large and bulk capacitors on the PCB when extracting its model. Then, you add the large/bulk capacitors (in the format of spice models) externally in the schematic (as explained in step 3).
Build a schematic in any possible EDA tool (Keysight ADS or Cadence or LTspice or Simplix) with the voltage regulator model (possible HSPICE model) and PCB model extracted from previous step.
- This schematic represents the voltage regulator plus the PCB or decoupling capacitors model up to package pins.
- Package, OPDs, or die model are not built into this schematic (Step load at package pin covers frequencies for only PCB, which means high frequency current components are eliminated through package and on-die).
- Connect the sense pins from the package pin feedback to the voltage regulator sense pins.
Connect the maximum step load current at the package pins shown in Table 9 (for example, for for Intel^® Agilex™ AGF014 core, 200A/µs slew rate and step load of 17A).
Probe voltage drop at the package pin to see if the power rail specification in Table 8 is met (for example, for VCC core, the DC+AC voltage tolerance is ±3%).
- If not meeting the package power rail tolerance or specification in Table 8, you must check the PCB and adjust the decoupling capacitors or locations.

Figure 22. Time Domain PDN Test Bench Example for Intel^® Agilex™ AGF014 VCC Core"A" is the VCC node at the package ball (all VCC pins at the package are connected to A). Voltage at "A" must be evaluated based on the voltage tolerance.

You must notice that Figure 22 shows a simplified schematic for the PDN transient simulation. In order to avoid non-convergence condition in TD simulation, Intel^® recommends you to only include small decoupling capacitors in the PCB model extraction and define ports for large/bulk decoupling capacitors at PCB level and add them to the schematic in Figure 22 manually.

Some of the PCB power rails in the recommended power tree in Figure 1, Figure 2, and Figure 3 is built by merging various power rails (with or without filter). You must define ports in the PCB modeling for each power rail to be able to inject the respective step load for that power rail in the PDN simulation schematic.

The recommended step load along with the static current (obtained from PTC) in a format of a pulse for each power rail is added to power rail ports in the PDN simulation schematic (e.g. Figure 22) and the voltage droop and overshoot are measured against the specification listed in Table 8.

The PDN IR drop analysis is a DC simulation and must be performed on all power rails on the PCB up to package pins to meet the electrical specifications listed in the Intel^® Agilex™ Device Data Sheet.

Figure 23 shows the reference stackup used in the PDN design guideline and FPGA decoupling capacitors extraction. However, the FPGA PDN performance is also validated with a thicker PCB such the DK-SI-AGF014E3ES board designed in-house.

Figure 23. Reference Stackup

9. Intel Agilex Device Family PDN Design Summary

The summary of the Intel^® Agilex™ device family PDN design guidelines are as follow:

Current PDN design guidelines stand for the maximum power consumption—the worst use case.
- If for any reason (various applications, configurations, or the PTC) power data is lower than the maximum power used for the PDN design guideline, you must scale the recommended decoupling capacitors based on the ratio of design current to the maximum current. Use of ratio is an estimate and time domain simulation are mandatory to ensure meeting package ball voltage specification.
Apply the recommended power-up or power-down sequence grouping on the PCB. For more information, refer to AN 692: Intel^® Cyclone^® 10 GX, Intel^® Arria^® 10, Intel^® Stratix^® 10, and Intel^® Agilex™ Devices and Intel^® Agilex™ Power Management User Guide.
Use the recommended power tree presented in the Power Tree for each Intel^® Agilex™ device with the suggested merged power nets.
- For example, minimum 9 x voltage regulator is required on the PCB for the Intel^® Agilex™ AGF014 2486A Package Early Silicon and minimum 10 x voltage regulator is required on the PCB for Intel^® Agilex™ AGF014 production silicon. The recommended voltage regulators are only for FPGA and do not cover other devices on the board.
- The minimum recommended number of voltage regulators on PCB is due to cost, area, and power-effective solution strategies. However, you can separate all power rails by the use of separate voltage regulators.
Use the recommended voltage regulators in the power tree or design your own voltage regulator based on the required maximum ripple or total current support per power rail on the PCB-VRM inductors or bulk capacitors must be designed separately. Tables in the Decoupling Capacitors Recommendation show the FPGA decoupling capacitors and do not include the voltage regulator bulk capacitors.
Use the recommended bottom-side or FPGA periphery decoupling capacitors for each power net.
Use the recommended LC filters for power nets.
Use of sense line for IR drop compensation.
Configure the FPGA to follow the maximum recommended step load allowed at the package pin.
Do post-layout simulation for the IR drop analysis to see if this is within the DC specification at the package pin in Table 8.
Do post-layout time domain PCB simulation up to the package pin for critical power nets such as the VCC core to meet the AC voltage tolerance or specification at the package pin in Table 8.
If not meeting the voltage tolerance (DC or AC) at the FPGA package pin, you must check the PCB and update the decoupling capacitors and redo the simulations.

10. Document Revision History for AN 910: Intel Agilex Power Distribution Network Design Guidelines

Document Version	Changes
2021.07.23	Added the PCB PDN Design Guideline for Unused Tiles section. Added Figure: VCCPT LC Filter Recommendation. Updated the Power Tree section. Updated the Power Tree Updates for Intel^® Agilex™ AGF014 2486A Production Silicon section. Updated the Power Nets and Transient Specifications section. Updated the Intel^® Agilex™ AGF012/AGF014, Intel^® Agilex™ AGI027/AGI023/AGI022, and Intel^® Agilex™ AGF027/AGF023/AGF022 FPGA Packages Board-Level Decoupling Capacitors Summary section. Updated the Board Decoupling Capacitors Guide section. Updated the FPGA Core Fabric VCC Voltage Regulator Selection section. Updated the Remote Sense Connections section. Updated the VCC Core Board Current Slew Rate section. Updated the Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails section. Updated the P-Tile Rail LC Filter Board Scheme and Connection section. Updated the PCB Voltage Regulator Recommendation for Other Power Rails section. Updated the Board Power Delivery Network Simulations section. Updated the Intel^® Agilex™ Device Family PDN Design Summary section. Updated Table: Intel^® Agilex™ Device Power Rail Grouping for the PUS Purpose. Updated Table: Required Rail Connections. Updated Table: Intel^® Agilex™ AGF (with only E-Tile and P-Tile), Intel^® Agilex™ AGF (with only F-Tile), and Intel^® Agilex™ AGI (with only F-Tile, R-Tile, or both tiles) FPGA Package Power Rail Nets and Subsystem Details. Updated Table: Intel^® Agilex™ E-Tile Power Rail Nets and Subsystem Details. Updated Table: Intel^® Agilex™ P-Tile Power Rail Nets and Subsystem Details. Updated Table: Intel^® Agilex™ R-Tile Power Rail Nets and Subsystem Details. Updated Table: Intel^® Agilex™ F-Tile Power Rail Nets and Subsystem Details. Updated Table: Intel^® Agilex™ Device PCB Power Rail Tolerance. Updated Table: Intel^® Agilex™ Device Family Transient and Step Load Specifications at Package Pin. Updated Table: Intel^® Agilex™ AGF012/AGF014, Intel^® Agilex™ AGI027/AGI023/AGI022, and Intel^® Agilex™ AGF027/AGF023/AGF022 Decoupling Capacitors Summary. Updated Table: Intel^® Agilex™ E-Tile Decoupling Capacitors Summary per Tile. Updated Table: Intel^® Agilex™ P-Tile Decoupling Capacitors Summary per Tile. Updated Table: Intel^® Agilex™ F-Tile Decoupling Capacitors Summary per Tile. Updated Table: Intel^® Agilex™ R-Tile Decoupling Capacitors Summary per Tile. Updated Figure: Recommended Intel^® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon. Updated Figure: Recommended Intel^® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices. Updated Figure: Recommended Intel^® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon. Updated Figure: Filter Recommendation for VCCH_GXP. Updated Figure: Filter Recommendation for VCCRT_GXP. Updated Figure: Connection Requirement and Filter Recommendation for VCCRT_GXE. Updated Figure: Connection Requirement and Filter Recommendation for VCCRTPLL_GXE. Updated Figure: Filter Recommendation for VCCH_FGT_GXF. Updated Figure: Connection Requirement and Filter Recommendation for VCCH_GXR. Updated Figure: Time Domain PDN Test Bench Example for Intel^® Agilex™ AGF014 VCC Core. Edited all "caps" and "decaps" to "capacitors" and "decoupling capacitors".
2021.06.02	Added VCCH_GXP and VCCCLK_GXP rails to Group 9 Rail 2 column in Table: Required Rail Connections. Updated VCCBAT_SDM power rail name to VCCBAT. Updated Figure: Filter Recommendation for VCCRT_GXP. Removed VCCBAT from Table: Intel^® Agilex™ Device Power Rail Grouping for the PUS Purpose. Removed F-series and I-series references.
2021.03.12	Added the F-tile and R-tile power rails in the following tables: Table: Required Rail Connections Table: Intel^® Agilex™ F-Series 2486A and 2581A FPGA Package Power Rail Nets and Subsystem Details Table: Intel^® Agilex™ Device Rail Tolerance Table: Intel^® Agilex™ Device Family Transient and Step Load Specifications at Package Pin Table: Intel^® Agilex™ F-Series 2486A and 2581A FPGA Decoupling Capacitors Summary Added Table: Intel^® Agilex™ F-Tile Decoupling Capacitors Summary. Added Table: Intel^® Agilex™ R-Tile Decoupling Capacitors Summary. Added Table: Intel^® Agilex™ R-Tile Power Rail Nets and Subsystem Details. Added Table: Intel^® Agilex™ F-Tile Power Rail Nets and Subsystem Details. Added the Recommended Power Tree for the Intel^® Agilex™ I-Series (2957A: R-Tile and F-Tile) Device Packages section. Added the P1V8_GR2 Filters Recommendation for Device Fabric section. Added the F-Tile Rail LC Filter Board Scheme and Connection section. Added the R-Tile Rail LC Filter Board Scheme and Connection section. Added Figure: VCCADC, VCCPLL_SDM, and VCCPLL_HPS Filter Recommendation. Added Figure: VCCA_PLL Filter Recommendation. Updated Table: Intel^® Agilex™ Device Power Rail Grouping for the PUS Purpose. Updated Figure:VCC/VCCP Core Voltage Regulator Design Implemented on the Intel^® Agilex™ AGF014 2486A FPGA Development Kits. Updated Figure: Filter Recommendation for VCCRT_GXP. Updated the Power-Down Sequencing (PDS) section. Updated the Power Budget section. Updated the Power Rails Tolerance section. Updated the Decoupling Capacitors Recommendation section. Updated the Board Decoupling Capacitors Guide section. Updated the Remote Sense Connections section. Updated the section title FPGA Core Fabric VCCL Voltage Regulator Selection to FPGA Core Fabric VCC Voltage Regulator Selection.
2020.12.18	Updated Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon to correct VCCCLX_GXP to VCCCLK_GXP.
2020.12.16	Updated Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon to correct the power group for VCCA_PLL from 2 to 3.
2020.12.05	Updated references to "ES silicon" to "early silicon" throughout the document. Updated Figure: Recommended F-Series 2486A Power Tree for Early Silicon. Updated Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon. Updated the Board Decoupling Capacitors Guide topic: Updated the VCCH cavity decapacitors on bottom side from 6x 0603 22µ to 4x 0603 22µ. Added a note to clarify that the power tree and number of decoupling capacitors within cavity on Intel^® Agilex™ development kit boards may be slightly different than what has been recommended due to early release of silicon and guideline. Updated Table: Intel^® Agilex™ F-Series 2486A and 2581A FPGA Decoupling Capacitors Summary. Updated Table: Required Rail Connections.
2020.08.25	Updated Figure: Recommended F-Series 2486A Power Tree for ES Silicon. Updated note (1) in Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon.
2020.08.19	Initial release.