Intel Stratix 10 Device Family Pin Connection Guidelines
Intel Stratix 10 Device Family Pin Connection Guidelines
Intel Stratix 10 Core Pins
Clock and PLL Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]p CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]p |
CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]p CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]p |
I/O, Clock Input |
Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT Rd, single-ended input OCT Rt, and single-ended output OCT Rs are supported on these pins. When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins. |
Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND. |
CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]n CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]n |
CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]n CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]n |
I/O, Clock Input | ||
PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FB[0] PLL_[3][A,B,C,F,G,H,I,J,K,L]_FB[0] |
PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_FB[0,1] PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_FB[0,1] |
I/O, Clock |
Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins. For more information about the supported pins, refer to the device pin-out file. |
Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND. |
PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBp PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBp |
— | I/O, Clock |
Dual-purpose I/O pins that can be used as differential I/Os, or external feedback input pins. For more information about the supported pins, refer to the device pin-out file. |
Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. |
PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBn PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBn |
— | I/O, Clock | ||
PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1] PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1] PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]p PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]p |
PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1] PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_CLKOUT[0:1] PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]p PLL_[2] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_CLKOUT[0:1]p |
I/O, Clock |
I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. For more information about the supported pins, refer to the device pin-out file. |
Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND. |
PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]n PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]n |
PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]n PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_CLKOUT[0:1]n |
I/O, Clock |
Dedicated Configuration/JTAG Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
TCK | F[1,2]_TCK | Input |
Dedicated JTAG test clock input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins. |
Connect this pin through a 1-kΩ pull-down resistor to GND. This pin has an internal 25-kΩ pull-down. Do not drive voltage higher than the VCCIO_SDM supply for the TCK pin. The TCK input pin is powered by the VCCIO_SDM supply. |
TMS | F[1,2]_TMS | Input |
Dedicated JTAG test mode select input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins. |
Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TMS pin to the VCCIO_SDM supply using a 1-kΩ resistor. This pin has an internal 25-kΩ pull-up. Do not drive voltage higher than the VCCIO_SDM supply for the TMS pin. The TMS input pin is powered by the VCCIO_SDM supply. |
TDO | F[1,2]_TDO | Output |
Dedicated JTAG test data output pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins. |
If the JTAG interface is not used, leave the TDO pin unconnected. |
TDI | F[1,2]_TDI | Input |
Dedicated JTAG test data input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins. |
Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TDI pin to the VCCIO_SDM supply using a 1-kΩ resistor. This pin has an internal 25-kΩ pull-up. Do not drive voltage higher than the VCCIO_SDM supply for the TDI pin. The TDI input pin is powered by the VCCIO_SDM supply. |
nSTATUS | F[1,2]_nSTATUS | Output | This pin is used for synchronization with the configuration host driving nCONFIG and to report errors. |
When you are using the Avalon-ST configuration scheme, connect this pin to the configuration host. For other configuration schemes, you can use this pin to monitor the configuration status. This pin must be pulled up through a 10-kΩ resistor to VCCIO_SDM for all configuration schemes. This pin has an internal 25-kΩ pull-up. |
nCONFIG | F[1,2]_nCONFIG | Input | The nCONFIG pin is used to clear the device and prepare for reconfiguration. |
When you use the Avalon-ST configuration scheme, connect this pin to the configuration host. When you use other configuration schemes, pull this pin to VCCIO_SDM through an external 10-KΩ pull-up resistor. This pin can be used to restart configuration by driving it low and then high again. Ensure that you follow all the requirements for the nCONFIG operation as specified in the Intel® Stratix® 10 Configuration User Guide and Intel® Stratix® 10 Device Design Guidelines. |
OSC_CLK_1 | F[1,2]_OSC_CLK_1 | Input | This pin is used as the clock for device configuration and transceiver calibration. |
You must provide an external clock source to this pin if you are using transceivers. If you choose to use the external clock source for configuration and/or instantiate any transceivers in your design, you must provide a 25-MHz, 100-MHz, or 125-MHz free-running clock source to this pin and enable it in the Intel® Quartus® Prime software when you compile your design. If you are using the internal oscillator for configuration and do not instantiate any transceivers in your design, leave this pin unconnected. |
Optional/Dual-Purpose Configuration Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
AVST_DATA[31:0] | — | I/O, Input |
Dual-purpose configuration data input pins. Use DATA [15:0] pins for Avalon Streaming Interface (Avalon-ST) x16 mode, DATA [31:0] pins for Avalon-ST x32 mode, or as regular I/O pins. Avalon-ST x8 mode uses the SDM_IO pins. These pins can also be used as user I/O pins after configuration. |
If these pins are not used as the dual-purpose pins and they are not used as I/O pins, leave these pins unconnected. |
AVST_CLK | — | I/O, Input |
Dual-purpose Avalon-ST interface clock input pin. This pin is used for Avalon-ST x16 and x32 configuration schemes. This pin can also be used as a user I/O pin after configuration. |
Connect this pin to the clock signal of an external configuration controller when configuring using the Avalon-ST x16 or x32 interface. |
AVST_VALID | — | I/O, Input |
Dual-purpose Avalon-ST interface data valid input pin. This pin is used for Avalon-ST x16 and x32 configuration schemes. This pin can also be used as a user I/O pin after configuration. |
Connect this pin to the data valid signal of an external configuration controller when configuring using the Avalon-ST x16 or x32 interface. |
nPERST[L,R][0:2] | nPERST[L,R][0:2] | I/O, Input |
Dual-purpose fundamental reset pin that is only available when you use together with PCI Express® (PCIe®) hard IP (HIP). When the PCIe HIP on a side (left or right) is enabled, the nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe nPERST signal to ensure that both ends of the link start link-training at the same time. The nPERST pins on a side are available as GPIOs only when the PCIe HIP on that side is not enabled. When the pin is low, the transceivers are in reset. When the pin is high, the transceivers are out of reset. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin. |
Connect this pin as defined in the Intel® Quartus® Prime software. This pin is powered by the VCCIO3V supply. When VCCIO3V is connected to a 3.0-V supply, you must use a diode to clamp the 3.3V LVTTL PCIe input signal to the VCCIO3V power of the device. When VCCIO3V is connected to any voltage other than 3.0V, you must use a level translator to shift down the voltage from 3.3V LVTTL to the corresponding voltage level powering the VCCIO3V pin. Only one nPERST pin is used per PCIe HIP. The
Intel®
Stratix® 10 components may have all six pins listed even when the specific component might only have 1 or 2 PCIe HIPs.
For maximum compatibility, always use the bottom left PCIe HIP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe link. |
3V Compatible I/O Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] | T[1,2,3,4]_IO3V[0,1,2,3,4,5,6,7] | I/O |
These are the 3.0V I/O pins. Each H- or L- transceiver tile supports eight 3.0V I/O pins. These pins support 1.2V, 1.25V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.0V I/O standards. For details about the supported I/O standards, refer to the Intel® Stratix® 10 Device Datasheet. |
Connect these pins according to the I/O interface standard you are using. You must provide power to the VCCR_GXB, VCCT_GXB, and VCCH_GXB pins of a transceiver tile to enable the 3.0V I/O pins within that tile. For any transceiver tiles that have their VCCR_GXB, VCCT_GXB, and VCCH_GXB unpowered, the corresponding 3.0V I/O pins within that tile is disabled. Using 3V I/O pins from an unpowered tile can potentially result in configuration failures. Connect unused pins as defined in the Intel® Quartus® Prime software. |
3.3V I/O Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
IO33_[5:0]_[7:0] |
— | I/O |
These are 3.3V I/O pins. The I/O bank is known as the 3.3V I/O bank and it is only available in the HF35 package of the GX400 (1SG040) and SX400 (1SX040) devices. These pins support 3.0V and 3.3V I/O. The index of [5:0] represents the grouping of the I/O pins and the index of [7:0] represents the pin numbering within the same group. The I/O pin can be configured as an input or output within the same grouping index. When any of the pin within the same group is configured as an input or output, the remaining pins will be configured to the same I/O direction. The same I/O buffer setting such as the slew rate and weak pull-up functions will be applied for pins within the same grouping. Intel® recommends you to plan the I/O resources before implementing your design. For more details about the supported I/O standards and features, refer to the Intel® Stratix® 10 General Purpose I/O User Guide. Fore more details about the I/O electrical specification, refer to the Intel® Stratix® 10 Device Datasheet. |
Connect these pins according to the I/O interface standard used in your design. To enable the 3.3V I/O bank, you must provide 3.0V or 3.3V power to VCCIO3C and 1.8V power to VCCIO3D. For unused I/O pins, leave the pins as NC. Tie VREFB3CN0 to GND. |
Differential I/O Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
LVDS[2][A,B,C,D,E, F,G,H,I,J,K,L,M,N]_[1:24][p,n] LVDS[3][A,B,C,D,E,F,G,H,I,J,K,L,M,N]_[1:24][p,n] |
LVDS[2][A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[1:24][p,n] LVDS[3][A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[1:24][p,n] | I/O, RX/TX channel | These are true LVDS receiver and transmitter channels on column I/O banks. Each I/O pair can be configured as a LVDS receiver or a LVDS transmitter. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If these pins are not used for differential signaling, these pins are available as user I/O pins. | Connect unused pins as defined in the Intel® Quartus® Prime software. |
DIFF_3[A,D]_[1:24][p,n] |
— | I/O |
These I/O banks are only available in the HF35 package of the GX 400 (1SG040), SX 400 (1ST040), and TX 400 (1SX040) devices. These pins support 1.2V, 1.25V, 1.35V, 1.5V, and 1.8V I/O standard. The LVDS, RSDS, and mini-LVDS I/O standards are only supported in the dedicated clock pin. The LVDS SERDES and EMIF functions are not supported in these I/O banks. Bank 3D of the GX 400 (1SG040) and SX 400 (1SX040) devices in the HF35 package has a maximum of 30 I/O pins only. |
Connect unused pins as defined in the Intel® Quartus® Prime software. |
External Memory Interface Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
DQS[0:47] DQS[48:95] |
DQS[0:47] DQS[48:95] |
I/O, bi-directional | Optional data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry. | Connect unused pins as defined in the Intel® Quartus® Prime software. |
DQSn[0:47] DQSn[48:95] |
DQSn[0:47] DQSn[48:95] |
I/O, bi-directional | Optional complementary data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry. | Connect unused pins as defined in the Intel® Quartus® Prime software. |
DQ[0:47] DQ[48:95] |
DQ[0:47] DQ[48:95] |
I/O, bi-directional | Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the device pin-out file. | Connect unused pins as defined in the Intel® Quartus® Prime software. |
Voltage Sensor Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
VSIGP_[0,1] | F[1,2]_VSIGP_[0,1] | Input | 2 pairs (for all Intel® Stratix® 10 FPGAs except Intel® Stratix® 10 GX 10M devices) or 4 pairs (for Intel® Stratix® 10 GX 10M device) of analog differential inputs pins used with the voltage sensor inside the FPGA to monitor external analog voltages. |
Tie these pins to GND if you do not use the voltage sensor feature. For details on the usage of these pins, refer to the Intel® Stratix® 10 Analog to Digital Converter User Guide. Do not drive VSIGP and VSIGN pins until the VCCADC power rail has reached 1.62V to prevent damage. |
VSIGN_[0,1] | F[1,2]_VSIGN_[0,1] | Input |
Temperature Sensor Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
TEMPDIODEp[0..6] |
F[1,2]_TEMPDIODE0p T[1,3]_TEMPDIODE1p T[2,4]_TEMPDIODE4p |
Input | These pins connect to the internal temperature sensing diodes in the FPGA core and in the transceiver tiles (bias-high input). |
Connect this pin to an external temperature sensing device to allow sensing of the FPGA's temperature. If you do not use the temperature sensing diode with an external temperature sensing device, leave this pin unconnected. For more information about the locations and channel numbers of the temperature sensors, refer to the Intel® Stratix® 10 Analog to Digital Converter User Guide. |
TEMPDIODEn[0..6] |
F[1,2]_TEMPDIODE0n T[1,3]_TEMPDIODE1n T[2,4]_TEMPDIODE4n |
Input | These pins connect to the internal temperature sensing diodes in the FPGA core and in the transceiver tiles (bias-low input). |
Connect this pin to an external temperature sensing device to allow sensing of the FPGA's temperature. If you do not use the temperature sensing diode with an external temperature sensing device, leave this pin unconnected. For more information about the locations and channel numbers of the temperature sensors, refer to the Intel® Stratix® 10 Analog to Digital Converter User Guide. |
Reference Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
RZQ_[2][A,B,C,F,G,H,I,J,K,L,M,N] RZQ_[3][A,B,C,D,E,F,G,H,I,J,K,L] |
RZQ_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2] RZQ_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2] |
I/O, bi-directional |
Reference pins for I/O banks. The RZQ pins share the same VCCIO with the I/O bank where they are located. Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin. |
When using OCT, tie these pins to GND through either a 240-Ω or 100-Ω resistor, depending on the desired OCT impedance. For more information about the OCT schemes, refer to the Intel® Stratix® 10 General Purpose I/O User Guide. When you do not use these pins as dedicated input for the external precision resistor or as I/O pins, leave these pins unconnected. |
No Connect and DNU Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
DNU | DNU | Do Not Use | Do Not Use (DNU). | Do not connect to power, GND, or any other signal. These pins must be left floating. |
NC | NC | No Connect | Do not drive signals into these pins. |
When designing for device migration, you have the option to connect these pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern, leave these pins floating. The following guidelines are for the HF35 package of the Intel® Stratix® 10 GX 400 or Intel® Stratix® 10 SX 400 to Intel® Stratix® 10 GX 650 or Intel® Stratix® 10 SX 650 device migration:
For more information, refer to AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package. |
Power Supply Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
VCCP | VCCP | Power | VCCP supplies power to the periphery. |
VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. For details about the recommended operating conditions, refer to the Electrical Characteristics in the Intel® Stratix® 10 Device Datasheet. Use the Intel® Stratix® 10 Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. See Notes 2, 3, 4, 6, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCC | VCC | Power | VCC supplies power to the core. |
VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. For details about the recommended operating conditions, refer to the Electrical Characteristics in the Intel® Stratix® 10 Device Datasheet. Use the Intel® Stratix® 10 Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. See Notes 2, 3, 4, 6, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCPT | VCCPT | Power | Power supply for the programmable power technology and I/O pre-drivers. |
Connect VCCPT to a 1.8V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:
Provide a minimum decoupling of 1uF for the VCCPT power rail near the VCCPT pin. A floating voltage may be observed on VCCPT during device power-up and power-down sequencing due to VCCERAM, with the magnitude of the floating voltage being lower than VCCPT. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices. See Notes 2, 3, 4, 7, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCA_PLL | VCCA_PLL_F[1,2] | Power | PLL Analog power. |
Connect VCCA_PLL to a 1.8V low noise switching regulator. With proper isolation filtering, you have the option to source VCCA_PLL from the same regulator as VCCPT. See Notes 2, 3, 4, 7, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCIO([2][A,B,C,F,L,M,N], [3][A,B,C,I,J,K,L]) |
VCCIO2[A,B,C,F,G,H,I, J,K,L,M,N]_F[1,2] VCCIO3[A,B,C,D,E,F,G,H,I,J,K,L]_F[1,2] |
Power |
These are the supply voltage pins for the I/O banks. Each bank can support a different voltage level. Supported VCCIO standards include the following:
|
These VCCIO guidelines only apply to non-HF35 package. If you are using the HF35 package of the GX 400 (1SG040), SX 400 (1SX040), and TX 400 (1ST040) devices, refer to the 3.3V I/O Pins table in this document for the VCCIO3C and VCCIO3D connection guidelines. Connect these pins to 1.2V, 1.25V, 1.35V, 1.5V, or 1.8V supplies, depending on the I/O standard required by the specific bank. You have the option to power down unused I/O banks by connecting their VCCIO pin to GND. During the power-up sequence only, a transient current whose magnitude is less than the VCCIO operating static current may be observed as the VCCIO transistors become operational. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed. When I/O bank 3A is used for AVST x16 or AVST x32 configuration mode, you must connect the VCCIO3A power supply to the VCCIO_SDM power supply for proper device functionality. For more details, refer to the Intel® Stratix® 10 General Purpose I/O User Guide. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices. See Notes 2, 3, 4, 8, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCIO3V | VCCIO3V_T[1,2,3,4] | Power | Power supply of the 3V I/O bank. |
Connect these pins to 1.2V, 1.5V, 1.8V, 2.5V, or 3.0V supplies, depending on the I/O standard required by the specified bank. VCCIO3V must be powered on for proper device operation even if the VCCIO3V banks are unused. VCCR_GXB, VCCT_GXB, and VCCH_GXB must be powered up to operate the VCCIO3V bank. For more details, refer to the Intel® Stratix® 10 General Purpose I/O User Guide. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices. See Notes 2, 3, 4, 8, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCIO_SDM | VCCIO_SDM_F[1,2] | Power | Configuration pins power supply. |
Connect these pins to a 1.8V power supply. When dual-purpose configuration pins are used for configuration, tie VCCIO of the bank where the dual-purpose configuration pins reside to the same regulator as VCCIO_SDM. When these pins require the same voltage level as VCCIO, you have the option to tie them to the same regulator as VCCIO. Provide a minimum decoupling of 47nF for the VCCIO_SDM power rail near the VCCIO_SDM pin. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices. See Notes 2, 3, 4, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCERAM | VCCERAM | Power | Embedded memory and digital transceiver power supply. |
Connect all VCCERAM pins to a 0.9V low noise switching power supply. VCCPLLDIG_SDM must be sourced from the same regulator as VCCERAM with proper isolation filtering. For more details, refer to the Intel® Stratix® 10 Device Datasheet. See Notes 2, 3, 7, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCPLLDIG_SDM | VCCPLLDIG_SDM_F[1,2] | Power | SDM block PLL power pins. | VCCPLLDIG_SDM must be sourced from the same regulator as VCCERAM with proper isolation filtering. |
VCCBAT | VCCBAT_F[1,2] | Power | Battery back-up power supply for design security volatile key register. |
When using the design security volatile key, connect this pin to a non-volatile battery power source in the range of 1.2V - 1.8V. When not using the volatile key, tie this pin to the 1.8-V VCCPT. This pin must be properly powered as per the recommended voltage range as the power-on reset (POR) circuitry of the Intel® Stratix® 10 devices monitors VCCBAT. Provide a minimum decoupling of 47nF for the VCCBAT power rail near the VCCBAT pin. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices. |
VCCPLL_SDM | VCCPLL_SDM_F[1,2] | Power | VCCPLL_SDM supplies analog power to the SDM block PLLs. |
Connect these pins to a 1.8V low noise power supply through a proper isolation filter. With proper isolation filtering, you have the option to source VCCPLL_SDM from the same regulator as VCCPT when all power rails require 1.8V. Decoupling for these pins depends on the design decoupling requirements of the specific board. See Notes 2, 3, 4, and 7 in Notes to Intel® Stratix® 10 Core Pins. |
GND | — | Ground | Device ground pins. | Connect all GND pins to the board ground plane. |
VREFB[[2][A,B,C,F,G,H,I,J,K,L,M,N], [3][A,B,C,D,E,F,G,H,I,J,K,L]]N0 |
VREFB2[A,B,C,F,G,H,I,J,K,L,M,N]N0_F[1,2] VREFB3[A,B,C,D,E,F,G,H,I,J,K,L]N0_F[1,2] |
Power | Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then use these pins as voltage-reference pins for the bank. |
If VREF pins are not used, connect them to either the VCCIO in the bank in which the pins reside or GND. See Notes 2, 8, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCLSENSE | VCCLSENSE_F[1,2] | Power | Differential sense line to external regulator. |
VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulators’ differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source. You must connect the VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs. |
GNDSENSE | GNDSENSE_F[1,2] | Power | ||
VCCADC | VCCADC_F[1,2] | Power | ADC power pin for the voltage sensors. |
You must supply a low noise 1.8V power supply to this pin if you are using the internal voltage sensors of the Intel® Stratix® 10 device. When you are using the voltage sensors, tie this pin to VCCA_PLL with proper isolation filtering. If you are not using the voltage sensors, tie this pin to VCCA_PLL. |
VCCFUSEWR_SDM | VCCFUSEWR_SDM_F[1,2] | Power | The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Intel® Stratix® 10 security architecture. For more information, refer to the Intel® Stratix® 10 Device Security User Guide. |
2.4V power supply is required on this pin if field-programming of the eFuses is required. If field-programming of the eFuses is not required, tie this pin to VCCPT or leave it unconnected (floating). Do not tie this pin to GND. If field-programming of the eFuses is required, Intel® recommends you to use an adjustable regulator that is set to 2.4V output when programming the eFuses and 1.8V output at all other times. A floating voltage may be observed on the VCCFUSEWR_SDM power during power-up and power-down sequencing due to VCCPT and/or VCCERAM, with the total magnitude of the floating voltage being lower than VCCFUSEWR_SDM. During the power-up sequence only, a transient current whose magnitude is less than the VCCFUSEWR_SDM operating transient current may be observed. The floating voltage and transient current are expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed. |
Secure Device Manager (SDM) Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Description | MSEL[2:0] | Pin Functions | Connection Guidelines |
---|---|---|---|---|---|
RREF_SDM |
F1_RREF_SDM F2_RREF_SDM |
Reference resistor input for the PLLs of the SDM interface. |
— | Input |
Connect a 2kΩ +/-1% resistor to GND. |
SDM_IO0 | F[1,2]_SDM_IO0 |
This pin is pulled low internally by a 25-kΩ resistor when the device is powered up. |
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. |
SDM_IO1 | F[1,2]_SDM_IO1 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA2 | Connect this pin to the data2 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
3'b001 or 3'b011 | AS_DATA1 | Connect this pin to the data1 pin of the QSPI flash device when configuring from the QSPI flash device. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO2 | F[1,2]_SDM_IO2 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA0 | Connect this pin to the data0 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
3'b001 or 3'b011 | AS_CLK | Connect this pin to the clock input of the QSPI flash device when configuring from the QSPI flash device. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO3 | F[1,2]_SDM_IO3 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA3 | Connect this pin to the data3 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
3'b001 or 3'b011 | AS_DATA2 | Connect this pin to the data2 pin of the QSPI flash device when configuring from the QSPI flash device. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO4 | F[1,2]_SDM_IO4 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA1 | Connect this pin to the data1 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
3'b001 or 3'b011 | AS_DATA0 | Connect this pin to the data0 pin of the QSPI flash device when configuring from the QSPI flash device. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO5 | F[1,2]_SDM_IO5 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin will function as MSEL[0] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected. For more information, refer to the Intel® Stratix® 10 Configuration User Guide. |
— | MSEL[0] | This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme. |
3'b001 or 3'b011 | AS_nCSO0 | Connect this pin to the nCS input of the first QSPI flash device when configuring from QSPI flash devices. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO6 | F[1,2]_SDM_IO6 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA4 | Connect this pin to the data4 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
3'b001 or 3'b011 | AS_DATA3 | Connect this pin to the data3 pin of the QSPI flash device when configuring from the QSPI flash device. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO7 | F[1,2]_SDM_IO7 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin will function as MSEL[1] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected. For more information, refer to the Intel® Stratix® 10 Configuration User Guide. |
— | MSEL[1] | This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme. |
3'b001 or 3'b011 | AS_nCSO2 | Connect this pin to the nCS input of the third QSPI flash device when you use cascaded QSPI flash devices for HPS application. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO8 | F[1,2]_SDM_IO8 |
This pin is pulled low internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_READY | Connect this pin to the ready signal output of the external configuration controller when configuring using the Avalon-ST x8, x16, or x32 interface. |
3'b001 or 3'b011 | AS_nCSO3 | Connect this pin to the nCS input of the fourth QSPI flash device when you use cascaded QSPI flash devices for HPS application. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO9 | F[1,2]_SDM_IO9 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin will function as MSEL[2] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected. For more information, refer to the Intel® Stratix® 10 Configuration User Guide. |
— | MSEL[2] | This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme. |
3'b001 or 3'b011 | AS_nCSO1 | Connect this pin to the nCS input of the second QSPI flash device when you use cascaded QSPI flash devices for HPS application. | |||
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO10 | F[1,2]_SDM_IO10 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA7 | Connect this pin to the data7 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO11 | F[1,2]_SDM_IO11 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_VALID | Connect this pin to the data valid pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO12 | F[1,2]_SDM_IO12 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. |
— | Any MSEL setting | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. |
SDM_IO13 | F[1,2]_SDM_IO13 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA5 | Connect this pin to the data5 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO14 | F[1,2]_SDM_IO14 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_CLK | Connect this pin to the clock output of an external configuration controller when configuring using the Avalon-ST x8 interface. |
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO15 | F[1,2]_SDM_IO15 |
This pin is pulled high internally by a 25-kΩ resistor when the device is powered up. This pin functions differently depending on the configuration scheme used by setting the MSEL pins. |
3'b110 | AVSTx8_DATA6 | Connect this pin to the data6 pin of an external configuration controller when configuring using the Avalon-ST x8 interface. |
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. | |||
SDM_IO16 | F[1,2]_SDM_IO16 |
This pin is pulled low internally by a 25-kΩ resistor when the device is powered up. |
Any valid MSEL setting | Optional signals | The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins. |
Secure Device Manager (SDM) Optional Signal Pins
Signal Name ( Intel® Stratix® 10 Devices) | Signal Name ( Intel® Stratix® 10 GX 10M Device) | Signal Description | Connection Guidelines | Configuration Schemes | |||
---|---|---|---|---|---|---|---|
ASx4 | AVSTx8 | AVSTx16 | AVSTx32 | ||||
PWRMGT_SCL | F[1,2]_PWRMGT_SCL |
PMBus Power Management Clock. This pin is used as the clock pin for the PMBus interface. |
This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V. Connect this pin to the PMBus clock pin of your regulator. When a –V device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode. When the PWRMGT_SCL pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain. |
SDM_IO0 SDM_IO14 |
SDM_IO0 |
SDM_IO0 SDM_IO14 |
SDM_IO0 SDM_IO14 |
PWRMGT_SDA | F[1,2]_PWRMGT_SDA |
PMBus Power Management Serial Data. This pin is used as the data pin for the PMBus interface. |
This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V. Connect this pin to the PMBus data pin of your regulator. When a –V device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode. When the PWRMGT_SDA pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain. |
SDM_IO11 SDM_IO12 SDM_IO16 |
SDM_IO12 SDM_IO16 |
SDM_IO11 SDM_IO12 SDM_IO16 |
SDM_IO11 SDM_IO12 SDM_IO16 |
PWRMGT_ALERT | — |
PMBus Power Management Alert. This pin is used as the ALERT function for the PMBus interface when the Intel® Stratix® 10 –V is the PMBus slave. |
This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V. Connect this pin to the PMBus ALERT pin of the external master controller. When using the SmartVID feature with the Intel® Stratix® 10 –V device as a PMBus slave, you must connect the PWRMGT_ALERT signal along with the PWRMGT_SCL and PWRMGT_SDA signals to the PMBus master device to complete the SmartVID power management interface. The PMBus master device reads the VID codes from the Intel® Stratix® 10 slave and programs the voltage regulator to output the correct VID voltage. When the PWRMGT_ALERT pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain. |
SDM_IO0 SDM_IO12 |
SDM_IO0 SDM_IO9 SDM_IO12 |
SDM_IO0 SDM_IO9 SDM_IO12 |
SDM_IO0 SDM_IO12 |
CONF_DONE | F[1,2]_CONF_DONE |
The CONF_DONE pin indicates all configuration data has been received. For the Intel® Stratix® 10 GX 10M device, both F1_CONF_DONE and F2_CONF_DONE pins must be active before use mode can be initiated. |
By default, Intel® recommends using the SDM_IO16 pin to implement the CONF_DONE function. If SDM_IO16 is unavailable, the CONF_DONE function can also be implemented using any unused SDM_IO pins. Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are required to connect to an external 4.7-kΩ pull-down resistor for the CONF_DONE signal. Connect the CONF_DONE pin to the external configuration controller when configuring using the Avalon® -ST (AVST) interface. You have an option to monitor this signal with an external component if you are using the active serial (AS) x4 configuration scheme. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO6 SDM_IO7 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
INIT_DONE | F[1,2]_INIT_DONE |
The INIT_DONE pin indicates the device has enter user mode upon completion of configuration. When used for this purpose, this pin must be enabled by the Intel® Quartus® Prime software. When the INIT_DONE function is enabled, this pin will drive high when configuration is completed and the device goes into user mode. |
Intel® recommends you to use SDM_IO0 or SDM_IO16 to implement the INIT_DONE function when available as it has an internal weak pull-down for the correct function of INIT_DONE during power up. If SDM_IO0 and SDM_IO16 are unavailable, SDM_IO5 can also be used for the INIT_DONE function when the configuration mode is set to Avalon® –ST x8 or Avalon® –ST x32 (AVST x8 or AVST x32) as these modes require an external 4.7–kΩ pull-down resistor. If SDM_IO0, SDM_IO5, and SDM_IO16 are unavailable, the INIT_DONE function can also be implemented using any unused SDM_IO pins provided that an external 4.7–kΩ pull-down resistor is provided for the INIT_DONE signal. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO6 SDM_IO7 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
CvP_CONFDONE | — |
The CvP_CONFDONE pin indicates the device has received the complete bitstream during configuration via protocol (CvP) core image configuration. When used for this purpose, enable this pin using the Intel® Quartus® Prime software. |
Connect this output pin to an external logic that monitors the CvP operation. The VCCIO_SDM power supply must meet the input voltage specification of the receiving side. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 |
— | — |
SEU_ERROR | — |
The SEU_ERROR pin drives high to indicate there is an SEU error message inside the SEU error queue. This pin stays high whenever the error message queue contains one or more error messages. The SEU_ERROR signal goes low only when the SEU error message queue is empty. When used for this purpose, enable this pin using the Intel® Quartus® Prime software. |
Connect this output pin to an external logic that monitors the SEU event. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
HPS_COLD_nRESET | — |
This is an active low, bidirectional pin. By default, this pin acts as an input pin to the SDM. When asserted externally for at least 5ms, this pin will generate interrupt to the SDM. The SDM will then initiate a cold reset procedure to the HPS and its peripherals. If the cold reset is generated from internal sources (for example, the HPS EL3 software), the SDM will switch this pin to output and drive a pulse to indicate reset. Once the cold reset procedure is complete, this pin will be switched back to input. |
Connect this pin through a 1–10-kΩ pull up to the VCCIO_SDM supply. Do not connect this pin to the reset input of any connected quad serial peripheral interface (quad SPI) devices. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
Direct to Factory Image | — |
Direct to factory input pin. When using the remote system upgrade feature, this optional pin allows you to choose between factory or application image. Driving logic high into this pin will instruct the device to load factory image, while driving logic low into this pin will instruct the device to load the application image. |
Connect this input pin to an external logic that manages the remote system upgrade of the device. By default, the external logic should provide logic low to this pin so that the application image will be the default image of the device, and only switch to factory image if required. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
— | — | — |
Notes to Intel Stratix 10 Core Pins
Intel provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.
- These pin connection guidelines are created based on the Intel® Stratix® 10 GX device variant.
- Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
- Use the Intel® Stratix® 10 Early Power Estimator (EPE) to determine the preliminary current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
- These supplies may share power planes across multiple Intel® Stratix® 10 devices.
- Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
- Example 1 and Example 2 illustrate the power supply sharing guidelines for the Intel® Stratix® 10 GX devices.
- Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching frequency range is not an Intel requirement.
- The number of modular I/O banks on Intel® Stratix® 10 devices depends on the device density. For the indexes available for a specific device, please refer to the I/O Bank section in the Intel® Stratix® 10 General Purpose I/O User Guide.
- PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
- Decoupling for these pins depends on the design decoupling requirements of the specific board.
- There are no dedicated PR_REQUEST, PR_ERROR, and PR_DONE pins. If required, you can use user I/O pins for these functions.
- The device orientation is die view (bottom of chip view).
Intel Stratix 10 High Bandwidth Memory (HBM) Pins
UIB and eSRAM Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
CLK_ESRAM_[0,1]p | Embedded SRAM (eSRAM) Clock Input | Dedicated positive high speed differential reference clock pin for eSRAM PLL. |
Connect this pin to the positive terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime ESRAM PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:
Connect directly to GND if unused. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. |
CLK_ESRAM_[0,1]n | eSRAM Clock Input | Dedicated complement high speed differential reference clock pin for eSRAM PLL. |
Connect this pin to the negative terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime ESRAM PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:
Connect directly to GND if unused. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. |
UIB_PLL_REF_CLK_[00,01]p | UIB Clock Input | Dedicated positive high speed differential reference clock pin for UIB PLL. |
Connect this pin to the positive terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime HBM2 interface PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:
You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2) IP is included in your design. Connect directly to GND if unused. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. |
UIB_PLL_REF_CLK_[00,01]n | UIB Clock Input | Dedicated complement high speed differential reference clock pin for UIB PLL. |
Connect this pin to the negative terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel® Quartus® Prime HBM2 interface PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:
You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2) IP is included in your design. Connect directly to GND if unused. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. |
RREF_ESRAM_[0,1] | eSRAM RREF Input | Reference resistor pin for UIB PLL and eSRAM PLL, specific to top (T) and bottom (B) of device. | If any UIB PLL or eSRAM PLL on the top or bottom side of the device is used, the corresponding RREF pin on that side of the device (top or bottom) must connect to its own individual 2K Ω +/-1% resistor to GND. The PCB trace between this pin and the reference resistor needs to be carefully routed to avoid any aggressor signals. |
UIB_RREF_[00,01] | UIB RREF Input | Reference resistor pin for UIB IO ZQ calibration. | Connect each pin through an individual 240Ω +/- 1% resistor to GND. No resistor sharing between pins is allowed. Leave this pin floating if unused. |
Intel Stratix 10 HBM Power Supply Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
VCCM_WORD_[BL,TL] | Power | Power supply for the embedded HBM2 memory. | Connect these pins to a 2.5V power supply. |
VCCIO_UIB_[BL,TL] | Power | Power supply for the Universal Interface Bus between the core and embedded HBM2 memory. | Connect these pins to a 1.2V power supply. |
Notes to Intel Stratix 10 HBM Pins
Intel provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.
- These pin connection guidelines are created based on the Intel® Stratix® 10 MX device variant.
- Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
- Use the Intel® Stratix® 10 Early Power Estimator (EPE) to determine the preliminary current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
- These supplies may share power planes across multiple Intel® Stratix® 10 devices.
- Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
- Example 7 and Example 8 illustrate the power supply sharing guidelines for the Intel® Stratix® 10 MX devices.
- Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching frequency range is not an Intel requirement.
- The number of modular I/O banks on Intel® Stratix® 10 devices depends on the device density. For the indexes available for a specific device, please refer to the I/O Bank section in the Intel® Stratix® 10 General Purpose I/O User Guide.
- For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
- Decoupling for these pins depends on the design decoupling requirements of the specific board.
H-Tile and L-Tile Pins
H-Tile and L-Tile Pins
Pin Name ( Intel® Stratix® 10 Devices) | Pin Name ( Intel® Stratix® 10 GX 10M Device) | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|---|
VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] |
VCCR_GXBL1[C,D,E]_T[1,3] VCCR_GXBL1[K,L,M]_T[2,4] |
Power |
Analog power, receiver, specific to each transceiver bank of the left (L) side or right (R) side of the device. |
Connect VCCR_GXB pins to a 1.03-V or 1.12-V low noise switching regulator depending on the transceiver data rate. VCCR_GXB and VCCT_GXB pins of each bank within a transceiver tile (L-tile or H-tile) must have the same voltage (either 1.03 V or 1.12 V). However, VCCR_GXB and VCCT_GXB of different banks within the same transceiver tile can have different voltages based on the configured transceiver data rates to further reduce power consumption of the transceiver tile. When the banks within a transceiver tile are powered at different voltages (for example, some banks operating at 1.03 V while other banks operating at 1.12 V), the xN clock lines are only allowed to transverse between contiguous banks operating at the same VCCR_GXB or VCCT_GXB voltages. The xN clock lines crossing boundaries of banks operating at different voltages is not allowed. For any input reference clock coming into a transceiver tile, that clock can be distributed to any bank within the tile even if the VCCR_GXB and VCCT_GXB operating voltages of the banks are different. When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND. Place a 22-nF decoupling capacitor between each VCCR_GXB power pin and GND pin on the back side of the BGA pin field. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. See Notes 2, 3, 4, 7, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] |
VCCT_GXBL1[C,D,E]_T[1,3] VCCT_GXBL1[K,LM]_T[2,4] |
Power | Analog power, transmitter, specific to each transceiver bank of the left (L) side or right (R) side of the device. |
Connect VCCT_GXB pins to a 1.03-V or 1.12-V low noise switching regulator depending on the transceiver data rate. VCCR_GXB and VCCT_GXB pins of each bank within a transceiver tile (L-tile or H-tile) must have the same voltage (either 1.03 V or 1.12 V). However, VCCR_GXB and VCCT_GXB of different banks within the same transceiver tile can have different voltages based on the configured transceiver data rates to further reduce power consumption of the transceiver tile. When the banks within a transceiver tile are powered at different voltages (for example, some banks operating at 1.03 V while other banks operating at 1.12 V), the xN clock lines are only allowed to transverse between contiguous banks operating at the same VCCR_GXB or VCCT_GXB voltages. The xN clock lines crossing boundaries of banks operating at different voltages is not allowed. For any input reference clock coming into a transceiver tile, that clock can be distributed to any bank within the tile even if the VCCR_GXB and VCCT_GXB operating voltages of the banks are different. When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND. Place a 22-nF decoupling capacitor between each VCCT_GXB power pin and GND pin on the back side of the BGA pin field. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. See Notes 2, 3, 4, 7, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
VCCH_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N] |
VCCH_GXBL1_T[1,3] VCCH_GXBR1_T[2,4] |
Power | Analog power, block level transmitter buffers, specific to the left (L) side or right (R) side of the device. |
Connect VCCH_GXB to 1.8-V low noise switching regulator. With a proper isolation filtering, you have the option to source VCCH_GXB from the same regulator as VCCPT. To minimize the regulator switching noise impact on channel jitter performance, keep the switching frequency for VCCH_GXB regulator below 2 MHz. For OTN applications, the switching frequency for VCCH_GXB is recommended to be below 500 KHz. Place a 22-nF decoupling capacitor between each VCCH_GXB power pin and GND pin on the back side of the BGA pin field. A leakage voltage may be observed on the VCCH_GXB power rail before the VCCH_GXB is powered on due to leakage inside the device during the power-up and power-down sequencing. The total magnitude of this leakage voltage is lower than VCCH_GXB and this is an expected behavior. During the power-up sequence only, a transient current whose magnitude is less than the VCCH_GXB static operating current may be observed. The floating voltage and transient current are expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed. When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND. See Notes 2, 3, 4, 7, and 10 in Notes to Intel® Stratix® 10 Core Pins. |
GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]p GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]p |
T1_GXBL1[C,D,E,F]_RX_CH[0:5]P T1_GXBL1[C,D,E,F]_REFCLK[0:5]p T2_GXBL1[N,M,L,K]_RX_CH[0:5]P T2_GXBL1[N,M,L,K]_REFCLK[0:5]p T3_GXBL1[C,D,E,F]_RX_CH[0:5]P T3_GXBL1[C,D,E,F]_REFCLK[0:5]p T4_GXBL1[N,M,L,K]_RX_CH[0:5]P T4_GXBL1[N,M,L,K]_REFCLK[0:5]p |
Input | High speed positive differential receiver channels or REFCLK inputs. Specific to each transceiver bank of the left (L) side or right (R) side of the device. |
These pins can be AC-coupled or DC-coupled when used. For more information, refer to the transceiver specifications in the Intel® Stratix® 10 Device Data Sheet. Connect all unused GXB_RXp pins directly to GND. |
GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]n GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]n |
T1_GXBL1[C,D,E,F]_RX_CH[0:5]n T1_GXBL1[C,D,E,F]_REFCLK[0:5]n T2_GXBL1[N,M,L,K]_RX_CH[0:5]n T2_GXBL1[N,M,L,K]_REFCLK[0:5]n T3_GXBL1[C,D,E,F]_RX_CH[0:5]n T3_GXBL1[C,D,E,F]_REFCLK[0:5]n T4_GXBL1[N,M,L,K]_RX_CH[0:5]n T4_GXBL1[N,M,L,K]_REFCLK[0:5]n |
Input | High speed negative differential receiver channels or REFCLK inputs. Specific to each transceiver bank of the left (L) side or right (R) side of the device. |
These pins can be AC-coupled or DC-coupled when used. For more information, refer to the transceiver specifications in the Intel® Stratix® 10 Device Data Sheet. Connect all unused GXB_RXn pins directly to GND. |
GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_TX_CH[0:5]p |
T1_GXBL1[C,D,E,F]_TX_CH[0:5]p T2_GXBL1[N,M,L,K]_TX_CH[0:5]p T3_GXBL1[C,D,E,F]_TX_CH[0:5]p T4_GXBL1[N,M,L,K]_TX_CH[0:5]p |
Output | High speed positive differential transmitter channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. | Leave all unused GXB_TXp pins floating. |
GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_TX_CH[0:5]n |
T1_GXBL1[C,D,E,F]_TX_CH[0:5]n T2_GXBL1[N,M,L,K]_TX_CH[0:5]n T3_GXBL1[C,D,E,F]_TX_CH[0:5]n T4_GXBL1[N,M,L,K]_TX_CH[0:5]n |
Output | High speed negative differential transmitter channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. | Leave all unused GXB_TXn pins floating. |
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]p |
T1_REFCLK_GXBL1[C,D,E,F]_CH[B,T]p T2_REFCLK_GXBL1[N,M,L,K]_CH[B,T]p T3_REFCLK_GXBL1[C,D,E,F]_CH[B,T]p T4_REFCLK_GXBL1[N,M,L,K]_CH[B,T]p |
Input |
High speed differential reference clock positive receiver channels, specific to each transceiver bank of the left (L) side or right (R) side of the device. REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not used. |
These pins should be AC-coupled when connected to any I/O standard other than the HCSL I/O standard. For the HCSL I/O standard, these pins must be DC-coupled. For example, PCIe* reference clocks should be DC-coupled if it uses the HCSL I/O standard. Connect all unused pins individually to GND. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. For PCIe* , you must follow this clock requirement. See Note 9 in Notes to Intel® Stratix® 10 Core Pins. |
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]n |
T1_REFCLK_GXBL1[C,D,E,F]_CH[B,T]n T2_REFCLK_GXBL1[N,M,L,K]_CH[B,T]n T3_REFCLK_GXBL1[C,D,E,F]_CH[B,T]n T4_REFCLK_GXBL1[N,M,L,K]_CH[B,T]n |
Input |
High speed differential reference clock complement, complementary receiver channel, specific to each transceiver bank of the left (L) side or right (R) side of the device. REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not used. |
These pins should be AC-coupled when connected to any I/O standard other than the HCSL I/O standard. For the HCSL I/O standard, these pins must be DC-coupled. For example, PCIe* reference clocks should be DC-coupled if it uses the HCSL I/O standard. Connect all unused pins individually to GND. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. For PCIe* , you must follow this clock requirement. See Note 9 in Notes to Intel® Stratix® 10 Core Pins. |
RREF_[T,M,B][L,R] |
T1_RREF_BL T2_RREF_BR T3_RREF_BL T4_RREF_BR |
Input | Reference resistor for fPLL, IOPLL, and transceiver, specific to the top (T), middle (M), and bottom (B) of the left (L) side or right (R) side of the device. |
If any REFCLK pin or transceiver channel on one side (left or right) of the device, IOPLL, or fPLL is used, you must connect each RREF pin on that side of the device to its own individual 2 kΩ ±1% resistor to GND. Otherwise, you can connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. |
RREF_SIPAUX0 | — | Input | Reference resistor pin for UIB PLL. |
You must connect the RREF_SIPAUX0 pin to a 2 kΩ ±1% resistor to GND. In the PCB layout, the trace from this pin to the resistor must be routed so that it avoids any aggressor signals. |
H-Tile/L-Tile | Bank | |||
---|---|---|---|---|
1C, 1D, 1E, 1F | 1K, 1L, 1M, 1N | 4C, 4D, 4E, 4F | 4K, 4L, 4M, 4N | |
3VIO pins | IO3V[0..7]_10 | IO3V[0..7]_12 | IO3V[0..7]_20 | IO3V[0..7]_22 |
Intel Stratix 10 E-Tile Pins
Intel Stratix 10 E-Tile Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
VCCH_GXE(L2, L3, R1, R2, R3) | Power | Analog power, block level transmitter buffers for E-tile, specific to the left (L) side or right (R) side of the device. |
Connect VCCH_GXE to a 1.1V low noise switching regulator. VCCH_GXE must be powered up even when the E-tile transceivers are not used. |
VCCRT_GXE(L2, L3, R1, R2, R3) | Power | Analog power, used for the high-speed circuitry for the E-tile blocks, specific to the left (L) side or right (R) side of the device. |
Connect VCCRT_GXE to VCCERAM through an LC filter. For more information about the LC filter design, refer to the Intel® Stratix® 10 Power Management User Guide. VCCRT_GXE must be powered up even when the E-tile transceivers are not used. |
VCCRTPLL_GXE(L2, L3, R1, R2, R3) | Power | Analog power, used for the high-speed circuitry for the E-tile blocks, specific to the left (L) side or right (R) side of the device. |
You must source the VCCRTPLL_GXE from the VCCRT_GXE with proper isolation filtering. Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel® Stratix® 10 Power Management User Guide. VCCRTPLL_GXE must be powered up even when the E-tile transceivers are not used. |
VCCCLK_GXE(L2, L3, R1, R2, R3) | Power | I/O power, specific to the E-tile reference clock buffers. |
Connect VCCCLK_GXE to a 2.5V low noise switching regulator. VCCCLK_GXE must be powered up even when the E-tile transceivers are not used. |
GXE(L8, R9)(A, B, C)_RX_CH[0:23][p,n] |
Input | High speed differential serial inputs to the receiver circuitry. Specific to the E-tile transceiver blocks on the left (L) side or right (R) side of the device. |
For PAM4, no off-chip AC-coupling capacitor is required provided that the RX input common mode voltage is between (GND + 300mV) and (VCCH_GXE-300mV), and the RX input amplitude differential voltage is less than 1200mVp-p. For PAM4, the absolute maximum positive voltage at the RX input of the SerDes is VCCH_GXE to maintain linearity. For NRZ, no off-chip AC-coupling capacitor is required provided that the RX input common mode voltage is between GND and VCCH_GXE, and the RX input amplitude differential voltage is less than 1200mVp-p. For NRZ, the absolute maximum positive voltage at the RX input to the SerDes is (VCCH_GXE + 300mV) to prevent forward-biasing of the ESD diodes. For more information, refer to the Electrical Characteristics section in the Intel® Stratix® 10 Device Datasheet. When the RX input common mode voltage is outside its required range (PAM4 or NRZ), external AC-coupling capacitors must be used. When using external AC-coupling capacitors, the RX termination is to the VCCH_GXE supply. A typical value of 100nF can be used as the external AC-coupling capacitor. Select a capacitor package (SMD) similar to that of the trace width to reduce in-line parasitics, and a material of X7R quality or higher. For high speed SerDes, mounting launch pad must be carefully designed. For more information about the external AC-coupling, refer to the Intel® Stratix® 10 E-Tile Transceiver PHY User Guide. Leave unused pins floating. |
GXE(L8, R9)(A, B, C)_TX_CH[0:23][p,n] | Output | High speed differential serial outputs from the transmitter circuitry. Specific to the E-tile transceiver blocks on the left (L) side or right (R) side of the device. | Leave all unused GXE_TX[p,n] pins floating. |
REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8][p,n] | Input |
High speed differential reference clock connects to the E-tile transceiver of the left (L) side or right (R) side of the device. REFCLK_GXE is supplied to both RX and TX independently. REFCLK_GXE can be used as dedicated clock input pins for core clock generation by configuring transceiver channel (Native PHY IP core) in the PLL mode. Supported I/O standard:
|
No off-chip AC-coupling capacitor is required. The default internal REFCLK inputs are 2.5-V LVPECL with a 50-Ω termination. Optional external termination is 2.5-V LVPECL or 3.3-V LVPECL. For more information about the external termination, refer to section 4.1 in the E-Tile Transceiver PHY User Guide. Tie each unused REFCLK pin to GND through a 1-kΩ resistor. REFCLK[1] must always be bonded out on board and connected to a clock source in case dynamic reconfiguration of REFCLK is planned. For more details on how to use it, refer to section 7.12 in the E-tile Transceiver PHY User Guide. Preservation of unused transceiver channels may need extra REFCLK_GXE to be bonded out on board based on use cases. For more details, refer to section 3.1.10 Unused Transceiver Channel in the E-tile Transceiver PHY User Guide. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. |
IO_AUX_RREF(11, 12, 20, 21, 22) | Input | Reference resistor for the AIB auxiliary channel. | Connect to a 2-kΩ resistor (±1%) to GND. |
Notes to Intel Stratix 10 E-Tile Pins
Intel provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.
- These pin connection guidelines are created based on the Intel® Stratix® 10 TX device variant.
- Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
- Use the Intel® Stratix® 10 Early Power Estimator (EPE) to determine the preliminary current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
- These supplies may share power planes across multiple Intel® Stratix® 10 devices.
- Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
- Example 9 and example 10 illustrate the power supply sharing guidelines for the Intel® Stratix® 10 TX devices.
- Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching frequency range is not an Intel requirement.
- The number of modular I/O banks on Intel® Stratix® 10 devices depends on the device density. For the indexes available for a specific device, please refer to the I/O Bank section in the Intel® Stratix® 10 General Purpose I/O User Guide.
- For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
- Decoupling for these pins depends on the design decoupling requirements of the specific board.
Intel Stratix 10 P-Tile Pins
Intel Stratix 10 P-Tile Power Supply Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
VCCH_GXP[L, R][1, 2, 3] | Power | Secondary high-voltage analog supply for transceivers and on-die PLL specific to P-tile. |
Connect VCCH_GXP to a 1.8V low-noise switching regulator. To minimize the regulator switching noise impact on channel jitter performance, keep the regulator switching frequency below 1 MHz. Place a 22–nF decoupling capacitor between each VCCH_GXP power pin and GND pin on the back side of the BGA pin field. VCCH_GXP must be filtered through the ferrite bead. VCCH_GXP must be powered up even when the P-tile transceivers are not used. |
VCCRT_GXP[L, R][1, 2, 3] | Power | Primary analog supply for the TX and RX channels, specific to P-tile. |
Connect VCCRT_GXP to a 0.9V low-noise switching regulator. With a proper isolation filtering, you have the option to source VCCRT_GXP from the same regulator as VCCERAM. VCCRT_GXP must be powered up even when the P-tile transceivers are not used. |
VCCCLK_GXP[L, R][1, 2, 3] | Power | LVCMOS I/O buffer supply rail, specific to P-tile. |
Connect VCCCLK_GXP to a 1.8V low-noise switching regulator. With a proper isolation filtering, you have the option to source VCCCLK_GXP from the same regulator as VCCPT. VCCCLK_GXP must be powered up even when the P-tile transceivers are not used. |
VCCFUSE_GXP | Power | Required power supply for the firmware to read internal settings for the one-time programmable eFuses. |
Connect the VCCFUSE_GXP pin to the 0.9V VCCERAM power. Connecting to the VCCERAM power rail adheres to the power-down sequencing requirement for the VCCFUSE_GXP supply. Do not leave this pin floating or tie it to GND. VCCFUSE_GXP must be powered up even when the P-tile transceivers are not used. |
Intel Stratix 10 P-Tile Transceiver Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
IO_AUX_RREF[10, 11, 12, 20, 21, 22]_P | Input | Reference resistor for P-tile transceivers. |
Connect each IO_AUX_RREF pin to a 2.8KΩ resistor (±1%) to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals. If this tile is unused, you must connect the 2.8KΩ resistor between this pin and GND. |
U[10, 11, 12, 20, 21, 22]_P_IO_RESREF_0 | Input | Transceiver reference resistor connection for PMA circuitry to provide termination for calibration. |
Connect each pin to 169Ω (±1%, 100 ppm/C) precision resistor to GND if the UltraPath Interconnect (UPI)/ PCIe* is 85Ω impedance. Place this resistor very close to the IO_RESREF pin. Avoid routing any noisy signals next to this reference resistor or its traces. Tie resistor to GND plane through a via placed very close to the reference resistor. External reference resistor parasitic capacitance load must be less than 6.5pF. |
I_PIN_PERST_N[10, 11, 12, 20, 21, 22]_P | Input | PCI Express* ( PCIe* ) Platform reset pin. |
In a PCI Express* ( PCIe* ) adapter card implementation, connect the PCIe* nPERST signal from the PCIe* edge connector to each P-tile transceiver bank I_PIN_PERST_N input. Use a level translator to fan out and change the 3.3V open-drain nPERST signal from the PCIe* connector to the 1.8V I_PIN_PERST_N input of each P-tile transceiver that is used on the board. Provide a 1.8V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3V PCIe* nPERST signal on the adapter card. For the UltraPath Interconnect (UPI) mode, contact Intel® for guidance. If the tile is unused, tie to GND. |
GXP[L, R][10, 11, 12][A, B, C]_TX_CH[0:19][p,n] | Output |
Differential-based transmitter pins, specific to P-tile transceivers on the left (L) side and right (R) side of the device. These pins support NRZ encoding up to 16Gbps. |
Connection guidelines for the PCIe* and UltraPath Interconnect (UPI) modes are as follow:
When these pins are not used, they can be floating. |
GXP[L, R][10, 11, 12][A, B, C]_RX_CH[0:19][p,n] | Input |
Differential-based receiver pins, specific to P-tile transceivers on the left (L) side and right (R) side of the device. These pins support NRZ encoding up to 16Gbps. |
When these pins are not used, they can be left floating. |
REFCLK_GXP[L, R][10, 11, 12][A, B, C]_CH[0, 2][p,n] | Input | Standard PCIe* HCSL reference clock input pins, specific to P-tile transceivers on the left (L) side and right (R) side of the device. |
For the HCSL I/O standard, it only supports DC coupling. In the PCIe* configuration, DC-coupling is allowed on the REFCLK if the selected REFCLK I/O standard is the HCSL I/O standard. Connect all unused pins individually to GND. You must connect a 100MHz reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ±300ppm requirement. For 2x8 modes, you can connect both reference clock inputs to the same clock source or connect to two independent clock sources. If the P-tile is completely unused but still has power applied, tie both REFCLK inputs to GND. |
S_STRAP[10,11,12,20,21,22]_P | Input | Internal strap pins. |
For PCIe* only system, connect to GND. For UltraPath Interconnect (UPI) applications, connect the strap pins as follows:
For the UltraPath Interconnect (UPI) mode, contact Intel® for guidance. |
NODE_ID[0,1][10,11,12,20,21,22]_P | Input | Internal node ID pins. |
For PCIe* only system, connect both ID pins to GND. For UltraPath Interconnect (UPI) applications, connect these ID pins to the corresponding CPU ID of the UPI interface.
If the tile is unused, tie to GND. For the UltraPath Interconnect (UPI) mode, contact Intel® for guidance. |
Intel Stratix 10 Hard Processor System (HPS) Pins
HPS Supply Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
VCCL_HPS | Power | VCCL_HPS supplies power to the HPS core. |
The VCCL_HPS power supply voltage could vary from 0.8V to 0.94V for –1V, –2V, or –3V devices with the SmartVID feature depending on the SmartVID setting in the device. When using –2L or –3X devices, you must connect to either 0.9V or 0.94V supply. If you are using 0.9V supply, VCCL_HPS can be connected to VCCERAM. VCCL_HPS can be shared with VCC and VCCP if they are at the same voltage level only when using –1V, –2V, or –3V devices (with the SmartVID feature). VCCL_HPS cannot be shared with VCC and VCCP when using –2L or –3X devices. VCCL_HPS always needs to be equal to VCCPLLDIG_HPS. Use the Intel® Stratix® 10 Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer to determine the current requirements for VCCL_HPS and other power supplies. Decoupling for these pins depends on the design decoupling requirements of the specific board. See Notes 2, 3, 4, and 6 in Notes to Intel® Stratix® 10 HPS Pins. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCL_HPS floating or connected to GND. |
VCCIO_HPS | Power | The HPS dedicated I/Os support 1.8V voltage level. |
Connect these pins to 1.8V power supply. If these pins have the same voltage requirement as VCCIO and VCCIO_SDM, you have the option to source VCCIO_HPS pins from the same regulator as VCCIO and VCCIO_SDM. Decoupling for these pins depends on the design decoupling requirements of the specific board. See Notes 2, 3, 4, and 8 in Notes to Intel® Stratix® 10 HPS Pins. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCIO_HPS floating or connected to GND. |
VCCPLL_HPS | Power | VCCPLL_HPS supplies analog power to the HPS PLLs. |
Connect these pins to a 1.8V low noise power supply through a proper isolation filter. You have the option to share VCCPLL_HPS with the same regulator as VCCPT when all power rails require 1.8V but only with a proper isolation filter. Decoupling for these pins depends on the design decoupling requirements of the specific board. See Notes 2, 3, 4, and 7 in Notes to Intel® Stratix® 10 HPS Pins. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCPLL_HPS floating or connected to GND. |
VCCPLLDIG_HPS | Power | Digital power supply of the PLL in HPS. |
Connect this to the VCCL_HPS with proper isolation filtering. For more information about isolation filters, refer to AN583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCPLLDIG_HPS floating or connected to GND. |
You can use the HPS Component in the Platform Designer to assign the HPS Dedicated I/Os to various HPS Peripherals and one hps_osc_clk input. The handoff files generated by the Platform Designer during the Intel® Quartus® Prime compilation will set the pin mux registers (pin0sel through pin47sel) and the HPS Oscillator Clock register (hps_osc_clk) to their respective HPS pin functions.
For more information about the valid combinations of the HPS I/O assignments, refer to the Hard Processor System Pin Information for Intel® Stratix® 10 Devices.
HPS Oscillator Clock Input Pin
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
HPS_OSC_CLK |
Clock input pin that drives the main PLL. Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS. For more information, refer to the valid frequency range of the clock source in the Intel® Stratix® 10 Device Datasheet. |
Input | Select one of the 48 HPS dedicated I/O in Platform Designer HPS Component. |
HPS JTAG Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
JTAG_TCK |
HPS JTAG test clock input pin. Connect this pin through a 1-kΩ – 10-kΩ pull-down resistor to GND. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. The option to access the HPS JTAG interface through the FPGA JTAG pins is available in the Intel® Quartus® Prime Pro Edition. For more details, refer to AN 802: Intel® Stratix® 10 SoC Device Design Guidelines. |
Input | HPS_IOB_9 |
JTAG_TMS |
HPS JTAG test mode select input pin. Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. |
Input | HPS_IOB_10 |
JTAG_TDO |
HPS JTAG test data output pin. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. |
Output | HPS_IOB_11 |
JTAG_TDI |
HPS JTAG test data input pin. Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. |
Input | HPS_IOB_12 |
HPS GPIO Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
GPIO0_IO[0..23] |
General purpose input output. Ensure that the I/O standard used is compatible with VCCIO_HPS. |
I/O |
HPS_IOA_[1..24] HPS_IOB_[1..24] |
GPIO1_IO[0..23] |
HPS SDMMC Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | |
---|---|---|---|---|
Group 1 | Group 2 | |||
SDMMC_CCLK | SDMMC clock out | Output | HPS_IOA_1 | HPS_IOB_15 |
SDMMC_CMD |
SDMMC command line Pull this pin high on the board with a weak pull-up resistor. For example, a 10-kΩ to VCCIO_HPS. |
I/O | HPS_IOA_2 | HPS_IOB_14 |
SDMMC_DATA0 | SDMMC Data 0 | I/O | HPS_IOA_3 | HPS_IOB_13 |
SDMMC_DATA1 | SDMMC Data 1 | I/O | HPS_IOA_4 | HPS_IOB_16 |
SDMMC_DATA2 | SDMMC Data 2 | I/O | HPS_IOA_5 | HPS_IOB_17 |
SDMMC_DATA3 |
SDMMC Data 3 When using SD card, there is an existing 50-kΩ pull-up on SDMMC Data Bit 3 which can be disabled in the HPS software by using the SET_CLR_CARD_DETECT (ACMD42) command. This is not applicable to the eMMC flash. |
I/O | HPS_IOA_6 | HPS_IOB_18 |
SDMMC_DATA4 | SDMMC Data 4 | I/O | HPS_IOA_7 | HPS_IOB_19 |
SDMMC_DATA5 | SDMMC Data 5 | I/O | HPS_IOA_8 | HPS_IOB_20 |
SDMMC_DATA6 | SDMMC Data 6 | I/O | HPS_IOA_9 | HPS_IOB_21 |
SDMMC_DATA7 | SDMMC Data 7 | I/O | HPS_IOA_10 | HPS_IOB_22 |
SDMMC_PWR_EN | SDMMC Power Enable | Output | HPS_IOA_11 | HPS_IOB_23 |
HPS NAND Pins
HPS Pin Functions | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | |
---|---|---|---|---|
Group 1 | Group 2 | |||
NAND_ADQ0 | NAND Data Bit 0 | I/O | HPS_IOA_1 | HPS_IOB_1 |
NAND_ADQ1 | NAND Data Bit 1 | I/O | HPS_IOA_2 | HPS_IOB_2 |
NAND_WE_N |
NAND Write Enable See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_3 | HPS_IOB_3 |
NAND_RE_N |
NAND Read Enable See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_4 | HPS_IOB_4 |
NAND_WP_N | NAND Write Protect | Output | HPS_IOA_5 | HPS_IOB_5 |
NAND_ADQ2 | NAND Data Bit 2 | I/O | HPS_IOA_6 | HPS_IOB_6 |
NAND_ADQ3 | NAND Data Bit 3 | I/O | HPS_IOA_7 | HPS_IOB_7 |
NAND_CLE | NAND Command Latch Enable | Output | HPS_IOA_8 | HPS_IOB_8 |
NAND_ADQ4 | NAND Data Bit 4 | I/O | HPS_IOA_9 | HPS_IOB_9 |
NAND_ADQ5 | NAND Data Bit 5 | I/O | HPS_IOA_10 | HPS_IOB_10 |
NAND_ADQ6 | NAND Data Bit 6 | I/O | HPS_IOA_11 | HPS_IOB_11 |
NAND_ADQ7 | NAND Data Bit 7 | I/O | HPS_IOA_12 | HPS_IOB_12 |
NAND_ALE | NAND Address Latch Enable | Output | HPS_IOA_13 | HPS_IOB_13 |
NAND_RB |
NAND Ready/Busy Connect this pin through a 1-kΩ to 10-kΩ pull-up resistor to VCCIO_HPS. |
Input | HPS_IOA_14 | HPS_IOB_14 |
NAND_CE_N |
NAND Chip Enable See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_15 | HPS_IOB_15 |
NAND_ADQ8 | NAND Data Bit 8 | I/O | HPS_IOA_17 | HPS_IOB_17 |
NAND_ADQ9 | NAND Data Bit 9 | I/O | HPS_IOA_18 | HPS_IOB_18 |
NAND_ADQ10 | NAND Data Bit 10 | I/O | HPS_IOA_19 | HPS_IOB_19 |
NAND_ADQ11 | NAND Data Bit 11 | I/O | HPS_IOA_20 | HPS_IOB_20 |
NAND_ADQ12 | NAND Data Bit 12 | I/O | HPS_IOA_21 | HPS_IOB_21 |
NAND_ADQ13 | NAND Data Bit 13 | I/O | HPS_IOA_22 | HPS_IOB_22 |
NAND_ADQ14 | NAND Data Bit 14 | I/O | HPS_IOA_23 | HPS_IOB_23 |
NAND_ADQ15 | NAND Data Bit 15 | I/O | HPS_IOA_24 | HPS_IOB_24 |
HPS USB Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
USB0_CLK | USB0 Clock | Input | HPS_IOA_1 |
USB0_STP | USB0 Stop Data | Output | HPS_IOA_2 |
USB0_DIR | USB0 Direction | Input | HPS_IOA_3 |
USB0_DATA0 | USB0 Data Bit 0 | I/O | HPS_IOA_4 |
USB0_DATA1 | USB0 Data Bit 1 | I/O | HPS_IOA_5 |
USB0_NXT | USB0 Next Data | Input | HPS_IOA_6 |
USB0_DATA2 | USB0 Data Bit 2 | I/O | HPS_IOA_7 |
USB0_DATA3 | USB0 Data Bit 3 | I/O | HPS_IOA_8 |
USB0_DATA4 | USB0 Data Bit 4 | I/O | HPS_IOA_9 |
USB0_DATA5 | USB0 Data Bit 5 | I/O | HPS_IOA_10 |
USB0_DATA6 | USB0 Data Bit 6 | I/O | HPS_IOA_11 |
USB0_DATA7 | USB0 Data Bit 7 | I/O | HPS_IOA_12 |
USB1_CLK | USB1 Clock | Input | HPS_IOA_13 |
USB1_STP | USB1 Stop Data | Output | HPS_IOA_14 |
USB1_DIR | USB1 Direction | Input | HPS_IOA_15 |
USB1_DATA0 | USB1 Data Bit 0 | I/O | HPS_IOA_16 |
USB1_DATA1 | USB1 Data Bit 1 | I/O | HPS_IOA_17 |
USB1_NXT | USB1 Next Data | Input | HPS_IOA_18 |
USB1_DATA2 | USB1 Data Bit 2 | I/O | HPS_IOA_19 |
USB1_DATA3 | USB1 Data Bit 3 | I/O | HPS_IOA_20 |
USB1_DATA4 | USB1 Data Bit 4 | I/O | HPS_IOA_21 |
USB1_DATA5 | USB1 Data Bit 5 | I/O | HPS_IOA_22 |
USB1_DATA6 | USB1 Data Bit 6 | I/O | HPS_IOA_23 |
USB1_DATA7 | USB1 Data Bit 7 | I/O | HPS_IOA_24 |
HPS EMAC Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
EMAC0_TX_CLK | EMAC0 Transmit Clock | Output | HPS_IOA_13 |
EMAC0_TX_CTL | EMAC0 Transmit Control | Output | HPS_IOA_14 |
EMAC0_RX_CLK | EMAC0 Receive Clock | Input | HPS_IOA_15 |
EMAC0_RX_CTL | EMAC0 Receive Control | Input | HPS_IOA_16 |
EMAC0_TXD0 | EMAC0 Transmit Data Bit 0 | Output | HPS_IOA_17 |
EMAC0_TXD1 | EMAC0 Transmit Data Bit 1 | Output | HPS_IOA_18 |
EMAC0_RXD0 | EMAC0 Receive Data Bit 0 | Input | HPS_IOA_19 |
EMAC0_RXD1 | EMAC0 Receive Data Bit 1 | Input | HPS_IOA_20 |
EMAC0_TXD2 | EMAC0 Transmit Data Bit 2 | Output | HPS_IOA_21 |
EMAC0_TXD3 | EMAC0 Transmit Data Bit 3 | Output | HPS_IOA_22 |
EMAC0_RXD2 | EMAC0 Receive Data Bit 2 | Input | HPS_IOA_23 |
EMAC0_RXD3 | EMAC0 Receive Data Bit 3 | Input | HPS_IOA_24 |
EMAC1_TX_CLK | EMAC1 Transmit Clock | Output | HPS_IOB_1 |
EMAC1_TX_CTL | EMAC1 Transmit Control | Output | HPS_IOB_2 |
EMAC1_RX_CLK | EMAC1 Receive Clock | Input | HPS_IOB_3 |
EMAC1_RX_CTL | EMAC1 Receive Control. | Input | HPS_IOB_4 |
EMAC1_TXD0 | EMAC1 Transmit Data Bit 0 | Output | HPS_IOB_5 |
EMAC1_TXD1 | EMAC1 Transmit Data Bit 1 | Output | HPS_IOB_6 |
EMAC1_RXD0 | EMAC1 Receive Data Bit 0 | Input | HPS_IOB_7 |
EMAC1_RXD1 | EMAC1 Receive Data Bit 1 | Input | HPS_IOB_8 |
EMAC1_TXD2 | EMAC1 Transmit Data Bit 2 | Output | HPS_IOB_9 |
EMAC1_TXD3 | EMAC1 Transmit Data Bit 3 | Output | HPS_IOB_10 |
EMAC1_RXD2 | EMAC1 Receive Data Bit 2 | Input | HPS_IOB_11 |
EMAC1_RXD3 | EMAC1 Receive Data Bit 3 | Input | HPS_IOB_12 |
EMAC2_TX_CLK | EMAC2 Transmit Clock | Output | HPS_IOB_13 |
EMAC2_TX_CTL | EMAC2 Transmit Control | Output | HPS_IOB_14 |
EMAC2_RX_CLK | EMAC2 Receive Clock | Input | HPS_IOB_15 |
EMAC2_RX_CTL | EMAC2 Receive Control | Input | HPS_IOB_16 |
EMAC2_TXD0 | EMAC2 Transmit Data Bit 0 | Output | HPS_IOB_17 |
EMAC2_TXD1 | EMAC2 Transmit Data Bit 1 | Output | HPS_IOB_18 |
EMAC2_RXD0 | EMAC2 Receive Data Bit 0 | Input | HPS_IOB_19 |
EMAC2_RXD1 | EMAC2 Receive Data Bit 1 | Input | HPS_IOB_20 |
EMAC2_TXD2 | EMAC2 Transmit Data Bit 2 | Output | HPS_IOB_21 |
EMAC2_TXD3 | EMAC2 Transmit Data Bit 3 | Output | HPS_IOB_22 |
EMAC2_RXD2 | EMAC2 Receive Data Bit 2 | Input | HPS_IOB_23 |
EMAC2_RXD3 | EMAC2 Receive Data Bit 3 | Input | HPS_IOB_24 |
HPS I2C_EMAC and MDIO Pins
There are three sets of I2C_EMAC interfaces that can be used as I2C interfaces or as the MDIO pins for the EMACs. You must take note that the I2C_EMAC and MDIO modules must be used with the corresponding EMAC interfaces. For example, you can use either I2C_EMAC0_SDA and I2C_EMAC0_SCL or MDIO0_MDIO and MDIO0_MDC with EMAC0.
The I2C protocol requires pull-up resistors to VCCIO_HPS on both the serial data and serial clock signals for them to function correctly. The value of the pull-up resistor varies depending on your board loading, but it is typically 4.7-kΩ or lower.
Typically the MDIO pin requires an external pull-up resistor to VCCIO_HPS in the range of 1.0-kΩ to 4.7-kΩ.
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | ||
---|---|---|---|---|---|
Group 1 | Group 2 | Group 3 | |||
I2C_EMAC2_SDA | I2C EMAC2 Serial Data | I/O | HPS_IOA_7 | HPS_IOB_9 | HPS_IOB_21 |
I2C_EMAC2_SCL | I2C EMAC2 Serial Clock | I/O | HPS_IOA_8 | HPS_IOB_10 | HPS_IOB_22 |
I2C_EMAC1_SDA | I2C EMAC1 Serial Data | I/O | HPS_IOA_9 | HPS_IOB_19 | — |
I2C_EMAC1_SCL | I2C EMAC1 Serial Clock | I/O | HPS_IOA_10 | HPS_IOB_20 | — |
I2C_EMAC0_SDA | I2C EMAC0 Serial Data | I/O | HPS_IOA_11 | HPS_IOB_11 | HPS_IOB_23 |
I2C_EMAC0_SCL | I2C EMAC0 Serial Clock | I/O | HPS_IOA_12 | HPS_IOB_12 | HPS_IOB_24 |
MDIO2_MDIO | EMAC2 MDIO | I/O | HPS_IOA_7 | HPS_IOB_9 | — |
MDIO2_MDC | EMAC2 MDC | Output | HPS_IOA_8 | HPS_IOB_10 | — |
MDIO1_MDIO | EMAC1 MDIO | I/O | HPS_IOA_9 | HPS_IOB_19 | — |
MDIO1_MDC | EMAC1 MDC | Output | HPS_IOA_10 | HPS_IOB_20 | — |
MDIO0_MDIO | EMAC0 MDIO | I/O | HPS_IOA_11 | HPS_IOB_11 | HPS_IOB_23 |
MDIO0_MDC | EMAC0 MDC | Output | HPS_IOA_12 | HPS_IOB_12 | HPS_IOB_24 |
HPS I2C Pins
In addition to the three I2C_EMAC controllers, there are two additional I2C controllers (I2C0 and I2C1) for dedicated I2C usage in the Intel® Stratix® 10 HPS.
The I2C protocol requires pull-up resistors to VCCIO_HPS on both the serial data and serial clock signals for them to function correctly. The value of the pull-up resistor varies depending on your board loading, but it is typically 4.7-kΩ or lower.
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | |||
---|---|---|---|---|---|---|
Group 1 | Group 2 | Group 3 | Group 4 | |||
I2C0 _SDA | I2C0 Serial Data | I/O | HPS_IOA_5 | HPS_IOA_23 | HPS_IOB_3 | — |
I2C0 _SCL | I2C0 Serial Clock | I/O | HPS_IOA_6 | HPS_IOA_24 | HPS_IOB_4 | — |
I2C1 _SDA | I2C1 Serial Data | I/O | HPS_IOA_3 | HPS_IOA_21 | HPS_IOB_7 | HPS_IOB_13 |
I2C1 _SCL | I2C1 Serial Clock | I/O | HPS_IOA_4 | HPS_IOA_22 | HPS_IOB_8 | HPS_IOB_14 |
HPS SPI Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the group) | ||
---|---|---|---|---|---|
Group 1 | Group 2 | Group 3 | |||
SPIM0_CLK | SPIM0 Clock | Output | HPS_IOA_5 | HPS_IOB_21 | HPS_IOB_21 |
SPIM0_MOSI | SPIM0 Master Out Slave In | Output | HPS_IOA_6 | HPS_IOB_22 | HPS_IOB_22 |
SPIM0_MISO | SPIM0 Master In Slave Out | Input | HPS_IOA_7 | HPS_IOB_19 | HPS_IOB_23 |
SPIM0_SS0_N |
SPIM0 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_8 | HPS_IOB_20 | HPS_IOB_24 |
SPIM0_SS1_N |
SPIM0 Slave Select 1 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_1 | HPS_IOB_18 | HPS_IOB_18 |
SPIM1_CLK | SPIM1 Clock | Output | HPS_IOA_9 | HPS_IOA_21 | HPS_IOB_1 |
SPIM1_MOSI | SPIM1 Master Out Slave In | Output | HPS_IOA_10 | HPS_IOA_22 | HPS_IOB_2 |
SPIM1_MISO | SPIM1 Master In Slave Out | Input | HPS_IOA_11 | HPS_IOA_23 | HPS_IOB_3 |
SPIM1_SS0_N |
SPIM1 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_12 | HPS_IOA_24 | HPS_IOB_4 |
SPIM1_SS1_N |
SPIM1 Slave Select 1 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_2 | HPS_IOA_20 | HPS_IOB_5 |
SPIS0_CLK | SPIS0 Clock | Input | HPS_IOA_1 | HPS_IOA_21 | HPS_IOB_9 |
SPIS0_MOSI | SPIS0 Master Out Slave In | Input | HPS_IOA_2 | HPS_IOA_22 | HPS_IOB_10 |
SPIS0_MISO | SPIS0 Master In Slave Out | Output | HPS_IOA_4 | HPS_IOA_24 | HPS_IOB_12 |
SPIS0_SS0_N |
SPIS0 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Input | HPS_IOA_3 | HPS_IOA_23 | HPS_IOB_11 |
SPIS1_CLK | SPIS1 Clock | Input | HPS_IOA_9 | HPS_IOB_5 | HPS_IOB_21 |
SPIS1_MOSI | SPIS1 Master Out Slave In | Input | HPS_IOA_10 | HPS_IOB_6 | HPS_IOB_22 |
SPIS1_MISO | SPIS1 Master In Slave Out | Output | HPS_IOA_12 | HPS_IOB_8 | HPS_IOB_24 |
SPIS1_SS0_N |
SPIS1 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Input | HPS_IOA_11 | HPS_IOB_7 | HPS_IOB_23 |
HPS UART Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | ||
---|---|---|---|---|---|
Group 1 | Group 2 | Group 3 | |||
UART0_CTS_N |
UART0 Clear to Send See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Input | HPS_IOA_1 | HPS_IOA_21 | HPS_IOB_1 |
UART0_RTS_N |
UART0 Request to Send See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_2 | HPS_IOA_22 | HPS_IOB_2 |
UART0_TX | UART0 Transmit | Output | HPS_IOA_3 | HPS_IOA_23 | HPS_IOB_3 |
UART0_RX | UART0 Receive | Input | HPS_IOA_4 | HPS_IOA_24 | HPS_IOB_4 |
UART1_CTS_N |
UART1 Clear to Send See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Input | HPS_IOA_5 | HPS_IOB_5 | HPS_IOB_17 |
UART1_RTS_N |
UART1 Request to Send See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_6 | HPS_IOB_6 | HPS_IOB_18 |
UART1_TX | UART1 Transmit | Output | HPS_IOA_7 | HPS_IOB_7 | HPS_IOB_15 |
UART1_RX | UART1 Receive | Input | HPS_IOA_8 | HPS_IOB_8 | HPS_IOB_16 |
HPS Trace Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
Trace_CLK | Trace Clock | Output | HPS_IOA_20 |
HPS_IOB_20 | |||
Trace_D0 | Trace Data 0 | Output | HPS_IOA_21 |
HPS_IOB_21 | |||
Trace_D1 | Trace Data 1 | Output | HPS_IOA_22 |
HPS_IOB_22 | |||
Trace_D2 | Trace Data 2 | Output | HPS_IOA_23 |
HPS_IOB_23 | |||
Trace_D3 | Trace Data 3 | Output | HPS_IOA_24 |
HPS_IOB_24 | |||
Trace_D4 | Trace Data 4 | Output | HPS_IOA_19 |
HPS_IOA_7 | |||
HPS_IOB_19 | |||
HPS_IOB_7 | |||
Trace_D5 | Trace Data 5 | Output | HPS_IOA_18 |
HPS_IOA_6 | |||
HPS_IOB_18 | |||
HPS_IOB_6 | |||
Trace_D6 | Trace Data 6 | Output | HPS_IOA_17 |
HPS_IOA_5 | |||
HPS_IOB_17 | |||
HPS_IOB_5 | |||
Trace_D7 | Trace Data 7 | Output | HPS_IOA_16 |
HPS_IOA_4 | |||
HPS_IOB_16 | |||
HPS_IOB_4 | |||
Trace_D8 | Trace Data 8 | Output | HPS_IOA_15 |
HPS_IOA_3 | |||
HPS_IOB_15 | |||
HPS_IOB_3 | |||
Trace_D9 | Trace Data 9 | Output | HPS_IOA_14 |
HPS_IOA_2 | |||
HPS_IOB_14 | |||
HPS_IOB_2 | |||
Trace_D10 | Trace Data 10 | Output | HPS_IOA_13 |
HPS_IOA_1 | |||
HPS_IOB_13 | |||
HPS_IOB_1 | |||
Trace_D11 | Trace Data 11 | Output | HPS_IOA_12 |
HPS_IOB_12 | |||
Trace_D12 | Trace Data 12 | Output | HPS_IOA_11 |
HPS_IOB_11 | |||
Trace_D13 | Trace Data 13 | Output | HPS_IOA_10 |
HPS_IOB_10 | |||
Trace_D14 | Trace Data 14 | Output | HPS_IOA_9 |
HPS_IOB_9 | |||
Trace_D15 | Trace Data 15 | Output | HPS_IOA_8 |
HPS_IOB_8 |
Notes to Intel Stratix 10 HPS Pins
Intel provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.
- These pin connection guidelines are based on the Intel® Stratix® 10 SX device variant.
- Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
- Use the Intel® Stratix® 10 Early Power Estimator (EPE) to determine the preliminary current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
- These supplies may share power planes across multiple Intel® Stratix® 10 devices.
- Power pins should not share breakout vias from the BGA. Each ball on the BGA must have its own dedicated breakout via.
- Low Noise Switching Regulator - a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800 kHz and 1 MHz and has fast transient response. The switching frequency range is not an Intel requirement.
- The number of modular I/O banks on Intel® Stratix® 10 devices depends on the device density. For the indexes available for a specific device, refer to the I/O Bank section in the Intel® Stratix® 10 General Purpose I/O User Guide.
- For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires that the AC-coupling capacitor is placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
- For item [#], refer to the device pin table for the pin-out mapping.
- The peripheral pins are programmable through pin multiplexors. Each pin may have multiple functions. HPS and SDM dedicated I/O pin multiplexing is programmable using the Quartus Prime software. The pin mux determines how the pins are used.
- These pins are inverted or active-low signals.
- Example 3 through Example 6 illustrate the power supply sharing guidelines for the Intel® Stratix® 10 SX devices.
Power Supply Sharing Guidelines for Intel Stratix 10 Devices
Intel® Stratix® 10 devices have specific power-up and power-down sequence requirements. For more information, refer to the AN692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 Devices and Intel® Stratix® 10 Power Management User Guide.
Example 1— Intel Stratix 10 GX
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 SmartVID |
± 30mV | Switcher (*) | Share | Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCFUSEWR_SDM | 5 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 GX device is provided in the following figure.
Example 2— Intel Stratix 10 GX
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 SmartVID |
± 30mV | Switcher (*) | Share | Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCFUSEWR_SDM | 6 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 GX device is provided in the following figure.
Example 3— Intel Stratix 10 GX (only for the HF35 Package)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 SmartVID |
± 30mV | Switcher (*) | Share | Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO3D | 5 | 1.8 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3D to a 1.8V power supply. |
VCCFUSEWR_SDM | 6 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
VCCIO3C | 7 | 3.0V/3.3V | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3C to a 3.0V or 3.3V power supply. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 GX device is provided in the following figure.
Example 4— Intel Stratix 10 GX (only for the HF35 Package)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 SmartVID |
± 30mV | Switcher (*) | Share | Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO3D | 6 | 1.8 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3D to a 1.8V power supply. |
VCCFUSEWR_SDM | 7 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
VCCIO3C | 8 | 3.0V/3.3V | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3C to a 3.0V or 3.3V power supply. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 GX device is provided in the following figure.
Example 5— Intel Stratix 10 SX (–1V, –2V, and –3V parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
SmartVID |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCP | ||||||
VCCL_HPS | ||||||
VCCPLLDIG_HPS | Filter | |||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCFUSEWR_SDM | 5 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 6— Intel Stratix 10 SX (–2L and –3X parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCL_HPS | ||||||
VCCPLLDIG_SDM | Filter | |||||
VCCPLLDIG_HPS | ||||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCFUSEWR_SDM | 5 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 7— Intel Stratix 10 SX (–1V, –2V, and –3V parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
SmartVID |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCP | ||||||
VCCL_HPS | ||||||
VCCPLLDIG_HPS | Filter | |||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCFUSEWR_SDM | 6 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 8— Intel Stratix 10 SX (–2L and –3X parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCL_HPS | ||||||
VCCPLLDIG_SDM | Filter | |||||
VCCPLLDIG_HPS | ||||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCFUSEWR_SDM | 6 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 9— Intel Stratix 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
SmartVID |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCP | ||||||
VCCL_HPS | ||||||
VCCPLLDIG_HPS | Filter | |||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO3D | 5 | 1.8 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3D to a 1.8V power supply. |
VCCFUSEWR_SDM | 6 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
VCCIO3C | 7 | 3.0V/3.3V | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3C to a 3.0V or 3.3V power supply. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 10— Intel Stratix 10 SX (–2L and –3X parts) (only for the HF35 Package)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCL_HPS | ||||||
VCCPLLDIG_SDM | Filter | |||||
VCCPLLDIG_HPS | ||||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO3D | 5 | 1.8 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3D to a 1.8V power supply. |
VCCFUSEWR_SDM | 6 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
VCCIO3C | 7 | 3.0V/3.3V | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3C to a 3.0V or 3.3V power supply. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 11— Intel Stratix 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
SmartVID |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCP | ||||||
VCCL_HPS | ||||||
VCCPLLDIG_HPS | Filter | |||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO3D | 6 | 1.8 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3D to a 1.8V power supply. |
VCCFUSEWR_SDM | 7 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
VCCIO3C | 8 | 3.0V/3.3V | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3C to a 3.0V or 3.3V power supply. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 12— Intel Stratix 10 SX (–2L and –3X parts) (only for the HF35 Package)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCL_HPS | ||||||
VCCPLLDIG_SDM | Filter | |||||
VCCPLLDIG_HPS | ||||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. |
VCCIO_SDM | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCIO_HPS | 1.8 | |||||
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO3D | 6 | 1.8 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3D to a 1.8V power supply. |
VCCFUSEWR_SDM | 7 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
VCCIO3C | 8 | 3.0V/3.3V | ± 5% (**) | Switcher (*) | Isolate | Connect VCCIO3C to a 3.0V or 3.3V power supply. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 SX device is provided in the following figure.
Example 13— Intel Stratix 10 MX (–1V, –2V, and –3V parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
SmartVID |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCM_WORD_(BL,TL) | 5 | 2.5 | ± 100mV | Switcher (*) | Isolate | Connect VCCM_WORD_(BL,TL) to a 2.5V power supply. |
VCCIO_SDM | 6 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V | You may source VCCIO_SDM, VCCIO, and VCCIO3V from the same regulator if they are at the same 1.8V voltage level. |
VCCIO | Varies | |||||
VCCIO3V | ||||||
VCCIO_UIB_(BL,TL) | 7 | 1.2 | ± 30mV | Switcher (*) | Isolate | Connect VCCIO_UIB_(BL,TL) to a 1.2V power supply. |
VCCFUSEWR_SDM | 8 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 MX device is provided in the following figure.
Example 14— Intel Stratix 10 MX (–1V, –2V, and –3V parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
SmartVID |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCM_WORD_(BL,TL) | 6 | 2.5 | ± 100mV | Switcher (*) | Isolate | Connect VCCM_WORD_(BL,TL) to a 2.5V power supply. |
VCCIO_UIB_(BL,TL) | 7 | 1.2 | ± 30mV | Switcher (*) | Isolate | Connect VCCIO_UIB_(BL,TL) to a 1.2V power supply. |
VCCIO_SDM | 8 | 1.8 | ± 30mV | Switcher (*) | Share if 1.8V | You may source VCCIO, VCCIO_SDM, and VCCIO3V from the same regulator if they are at the same 1.8V voltage level. |
VCCIO | Varies | |||||
VCCIO3V | ||||||
VCCFUSEWR_SDM | 9 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 MX device is provided in the following figure.
Example 15— Intel Stratix 10 MX (E-Tile)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCPLLDIG_SDM to the same regulator as the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Ferrite Bead Filter | |||||
VCCRT_GXE | LC Filter |
Connect VCCRT_GXE to a dedicated 0.9V power supply. You may source VCCRT_GXE from VCCERAM through an LC filter. You may also source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead. When implementing a filtered supply topology, you must considered the IR drop across the filter. |
||||
VCCRTPLL_GXE | Ferrite Bead Filter | |||||
VCCR_GXB[L,R] | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Ferrite Bead Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCH_GXE | 5 | 1.1 | ± 5% (**) | Switcher (*) | Isolate | Connect the VCCH_GXE to a dedicated 1.1V power supply. |
VCCM_WORD_(BL,TL) | 6 | 2.5 | ± 100mV | Switcher (*) | Isolate |
Connect VCCM_WORD_(BL,TL) to a 2.5V power supply. |
VCCCLK_GXE | Ferrite Bead Filter |
Connect VCCCLK_GXE to a dedicated 2.5V power supply. You have the option to share VCCCLK_GXE with VCCM_WORD if the VRM tolerance is ±100mV or better. When sharing, filter the VCCCLK_GXE with a ferrite bead. |
||||
VCCIO_UIB_(BL,TL) | 7 | 1.2 | ± 30mV | Switcher (*) | Isolate | Connect VCCIO_UIB_(BL,TL) to a 1.2V power supply. |
VCCIO_SDM | 8 | 1.8 | ± 30mV | Switcher (*) | Share if 1.8V |
You may source VCCIO, VCCIO_SDM, and VCCIO3V from the same regulator if they are at the same 1.8V voltage level. |
VCCIO | Varies | |||||
VCCIO3V | ||||||
VCCFUSEWR_SDM | 9 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 TX device is provided in the following figure.
Example 16— Intel Stratix 10 TX (–1V, –2V, and –3V parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
SmartVID |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 TX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCP | ||||||
VCCL_HPS | ||||||
VCCPLLDIG_HPS | Filter | |||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM | Filter | |||||
VCCRT_GXE | Filter |
Connect VCCRT_GXE to VCCERAM through an LC filter. For more information about the LC filter design, refer to the Intel® Stratix® 10 Power Management User Guide. |
||||
VCCRTPLL_GXE | Filter |
You may source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead. Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel® Stratix® 10 Power Management User Guide. |
||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCH_GXE | 5 | 1.1 | ± 5% (**) | Switcher (*) | Isolate | Connect the VCCH_GXE to a dedicated 1.1V power supply. |
VCCCLK_GXE | 6 | 2.5 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCCLK_GXE to a dedicated 2.5V power supply. |
VCCPT | 7 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. If you do not intend to utilize the HPS in the Intel® Stratix® 10 TX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO_SDM | 8 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V | You may source VCCIO_SDM, VCCIO, VCCIO3V, and VCCIO_HPS from the same regulator if they are at the same 1.8V voltage level. |
VCCIO_HPS | ||||||
VCCIO | Varies | |||||
VCCIO3V | ||||||
VCCFUSEWR_SDM | 9 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 TX device is provided in the following figure.
Example 17— Intel Stratix 10 TX (–2L and –3X parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 |
0.85 |
± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 TX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCL_HPS | ||||||
VCCPLLDIG_SDM | Filter | |||||
VCCPLLDIG_HPS | ||||||
VCCRT_GXE | Filter |
Connect VCCRT_GXE to VCCERAM through an LC filter. For more information about the LC filter design, refer to the Intel® Stratix® 10 Power Management User Guide. |
||||
VCCRTPLL_GXE | Filter |
You may source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead. Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel® Stratix® 10 Power Management User Guide. |
||||
VCCR_GXB[L,R] | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB[L,R] | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCH_GXE | 5 | 1.1 | ± 5% (**) | Switcher (*) | Isolate | Connect the VCCH_GXE to a dedicated 1.1V power supply. |
VCCCLK_GXE | 6 | 2.5 | ± 5% (**) | Switcher (*) | Isolate | Connect VCCCLK_GXE to a dedicated 2.5V power supply. |
VCCPT | 7 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. If you do not intend to utilize the HPS in the Intel® Stratix® 10 TX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND. TX device,When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCBAT | Varies | |||||
VCCH_GXB[L,R] | 1.8 | Filter | ||||
VCCA_PLL | 1.8 | |||||
VCCPLL_SDM | 1.8 | |||||
VCCPLL_HPS | 1.8 | |||||
VCCADC | 1.8 | |||||
VCCIO_SDM | 8 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V | You may source VCCIO_SDM, VCCIO, VCCIO3V, and VCCIO_HPS from the same regulator if they are at the same 1.8V voltage level. |
VCCIO_HPS | ||||||
VCCIO | Varies | |||||
VCCIO3V | ||||||
VCCFUSEWR_SDM | 9 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 TX device is provided in the following figure.
Example 18— Intel Stratix 10 DX (–1V, –2V, and –3V parts)
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 | SmartVID | ± 30mV | Switcher (*) | Share |
Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. If you do not intend to utilize the HPS in the Intel® Stratix® 10 DX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND. |
VCCP | ||||||
VCCL_HPS | ||||||
VCCPLLDIG_HPS | Ferrite Bead Filter | |||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect VCCERAM and VCCFUSE_GXP to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM and VCCRT_GXP power to the shared VCCERAM and VCCFUSE_GXP power planes with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCFUSE_GXP | ||||||
VCCRT_GXP | Ferrite Bead Filter | |||||
VCCPLLDIG_SDM | Ferrite Bead Filter | |||||
VCCRT_GXE | LC Filter |
Connect the VCCRT_GXE to a dedicated 0.9V power supply. You may source VCCRT_GXE from VCCERAM through an LC filter. You may also source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
||||
VCCRTPLL_GXE | Ferrite Bead Filter | |||||
VCCH_GXE | 3 | 1.1 | ± 5% (**) | Switcher (*) | Isolate | Connect the VCCH_GXE to a dedicated 1.1V power supply. |
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You can source VCCPT and VCCBAT from the same regulator, sharing the same voltage plane. You have the option to connect VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, VCCADC, and VCCCLK_GXP to the same power plane with proper isolation filtering. If you do not intend to utilize the HPS in the Intel® Stratix® 10 DX device, you must still provide power to the HPS power supply. Do not leave the VCCPLL_HPS floating or connect them to GND. When implementing a filtered supply topology you must consider the IR drop across the filter. |
VCCBAT | Varies | |||||
VCCA_PLL | 1.8 | Ferrite Bead Filter | ||||
VCCPLL_SDM | ||||||
VCCPLL_HPS | ||||||
VCCADC | ||||||
VCCCLK_GXP | ||||||
VCCH_GXP | 5 | 1.8 | ± 30mV | Switcher (*) | Ferrite Bead Filter | Connect VCCH_GXP to a dedicated 1.8V power supply. |
VCCM_WORD_(BL,TL) | 6 | 2.5 | ± 100mV | Switcher (*) | Isolate | Connect VCCM_WORD_(BL,TL) to a 2.5V power supply. |
VCCCLK_GXE | Ferrite Bead Filter |
Connect VCCCLK_GXE to a dedicated 2.5V power supply. You have the option to share VCCCLK_GXE with VCCM_WORD if the VRM tolerance is ±100mV or better. When sharing, filter the VCCCLK_GXE with a ferrite bead. |
||||
VCCIO_UIB_(BL,TL) | 7 | 1.2 | ± 30mV | Switcher (*) | Isolate | Connect VCCIO_UIB_(BL,TL) to a 1.2V power supply. |
VCCFUSEWR_SDM | 8 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Connect VCCFUSEWR_SDM to 1.8V power supply if the SDM fuses do not need to be written. Do not tie this pin to GND. |
VCCIO_SDM | 9 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You can source VCCIO_SDM, VCCIO_HPS, and VCCIO from the same regulator, if they are at the same 1.8V voltage level. If you do not intend to utilize the HPS in the Intel® Stratix® 10 DX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS floating or connect them to GND. |
VCCIO_HPS | ||||||
VCCIO | Varies |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 DX device is provided in the following figure.
Example 19— Intel Stratix 10 GX 10M
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 | 0.88 | ± 30mV | Switcher (*) | Share | Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Share |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM_F[1,2] | Filter | |||||
VCCR_GXB1 | 3 | 1.03 | ± 30mV | Switcher (*) | Share |
You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXB1 | ||||||
VCCPT | 4 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCIO_SDM_F[1,2] | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCBAT_F[1,2] | Varies | |||||
VCCH_GXB[L1,R1] | 1.8 | Filter | ||||
VCCA_PLL_F[1,2] | 1.8 | |||||
VCCPLL_SDM_F[1,2] | 1.8 | |||||
VCCADC_F[1,2] | 1.8 | |||||
VCCFUSEWR_SDM_F[1,2] | 5 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 GX device is provided in the following figure.
Example 20— Intel Stratix 10 GX 10M
Power Pin Name | Regulator Group | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC | 1 | 0.88 | ± 30mV | Switcher (*) | Share | Source VCC and VCCP from the same regulator, sharing the same voltage plane. |
VCCP | ||||||
VCCERAM | 2 | 0.9 | ± 30mV | Switcher (*) | Isolate |
Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCPLLDIG_SDM_F[1,2] | Filter | |||||
VCCR_GXBL1 | 3 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCR_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCT_GXBL1 | 4 | 1.12 | ± 20mV | Switcher (*) | Isolate |
Connect the VCCT_GXB to a dedicated 1.12V power supply. The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet. |
VCCPT | 5 | 1.8 | ± 5% (**) | Switcher (*) | Share if 1.8V |
You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices. When implementing a filtered supply topology, you must consider the IR drop across the filter. |
VCCIO_SDM_F[1,2] | 1.8 | |||||
VCCIO | Varies | |||||
VCCIO3V | Varies | |||||
VCCBAT_F[1,2] | Varies | |||||
VCCH_GXB[L1,R1] | 1.8 | Filter | ||||
VCCA_PLL_F[1,2] | 1.8 | |||||
VCCPLL_SDM_F[1,2] | 1.8 | |||||
VCCADC_F[1,2] | 1.8 | |||||
VCCFUSEWR_SDM_F[1,2] | 6 | 2.4 | ± 50mV | Switcher (*) | Isolate | Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 GX device is provided in the following figure.
Document Revision History for the Intel Stratix 10 Device Family Pin Connection Guidelines
Document Version | Changes |
---|---|
2020.12.23 |
Removed the sentence "For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30 dB of isolation for a 1 MHz to 100 MHz bandwidth." from the following tables:
Note: If you have implemented this recommendation on your board and your design functions properly, you do not need to rework the board.
|
2020.12.14 | Corrected the pin name RREF_SPIAUX0 to RREF_SIPAUX0 in Table: H-Tile and L-Tile Pins. |
2020.11.23 | Updated the regulator sharing for VCCM_WORD_(BL,TL) from share to isolate in the following tables:
|
2020.10.23 |
|
2020.08.07 |
|
2020.06.30 |
|
2020.04.20 |
|
2019.12.13 | Updated the jitter specification of the UIB_PLL_REF_CLK_[00,01]p and UIB_PLL_REF_CLK_[00,01]n pins. |
2019.12.11 |
|
2019.09.20 | Added support for
Intel®
Stratix® 10 DX devices.
|
2019.07.01 |
|
2019.06.14 | Updated the following power supply sharing guidelines to remove
VCCL_HPS, VCCPLLDIG_HPS, VCCIO_HPS, and VCCPLL_HPS power rails:
|
2019.01.31 |
|
2019.01.03 |
|
2018.12.14 |
|
2018.08.16 |
|
Date | Version | Description of Changes |
---|---|---|
December 2017 | 2017.12.21 |
|
July 2017 | 2017.07.14 | Added the TEMPDIODEp[0..6] and TEMPDIODEn[0..6] pins. |
June 2017 | 2017.06.16 |
|
February 2017 | 2017.02.24 |
|
October 2016 | 2016.10.31 | Initial release. |