CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]p

CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]p

CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]p

CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]p

Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT Rd, single-ended input OCT Rt, and single-ended output OCT Rs are supported on these pins.

When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins.

CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]n

CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]n

CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]n

CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]n

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FB[0]

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FB[0]

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_FB[0,1]

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_FB[0,1]

Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBp

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBp

Dual-purpose I/O pins that can be used as differential I/Os, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBn

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBn

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]p

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]p

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_CLKOUT[0:1]

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]p

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

For more information about the supported pins, refer to the device pin-out file.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]n

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]n

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]n

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_CLKOUT[0:1]n

Dedicated JTAG test clock input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

Connect this pin through a 1-kΩ pull-down resistor to GND.

This pin has an internal 25-kΩ pull-down.

Do not drive voltage higher than the VCCIO_SDM supply for the TCK pin. The TCK input pin is powered by the VCCIO_SDM supply.

Dedicated JTAG test mode select input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TMS pin to the VCCIO_SDM supply using a 1-kΩ resistor.

This pin has an internal 25-kΩ pull-up.

Do not drive voltage higher than the VCCIO_SDM supply for the TMS pin. The TMS input pin is powered by the VCCIO_SDM supply.

Dedicated JTAG test data output pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

Dedicated JTAG test data input pin. This pin can also be used to access the SDM and HPS JTAG chains. For more information, refer to the HPS JTAG Pins.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TDI pin to the VCCIO_SDM supply using a 1-kΩ resistor.

This pin has an internal 25-kΩ pull-up.

Do not drive voltage higher than the VCCIO_SDM supply for the TDI pin. The TDI input pin is powered by the VCCIO_SDM supply.

When you are using the Avalon-ST configuration scheme, connect this pin to the configuration host.

For other configuration schemes, you can use this pin to monitor the configuration status.

This pin must be pulled up through a 10-kΩ resistor to VCCIO_SDM for all configuration schemes. This pin has an internal 25-kΩ pull-up.

When you use the Avalon-ST configuration scheme, connect this pin to the configuration host.

When you use other configuration schemes, pull this pin to VCCIO_SDM through an external 10-KΩ pull-up resistor. This pin can be used to restart configuration by driving it low and then high again. Ensure that you follow all the requirements for the nCONFIG operation as specified in the Intel^® Stratix^® 10 Configuration User Guide and Intel^® Stratix^® 10 Device Design Guidelines.

You must provide an external clock source to this pin if you are using transceivers.

If you choose to use the external clock source for configuration and/or instantiate any transceivers in your design, you must provide a 25-MHz, 100-MHz, or 125-MHz free-running clock source to this pin and enable it in the Intel^® Quartus^® Prime software when you compile your design. If you are using the internal oscillator for configuration and do not instantiate any transceivers in your design, leave this pin unconnected.

Dual-purpose configuration data input pins.

Use DATA [15:0] pins for Avalon Streaming Interface (Avalon-ST) x16 mode, DATA [31:0] pins for Avalon-ST x32 mode, or as regular I/O pins.

Avalon-ST x8 mode uses the SDM_IO pins.

These pins can also be used as user I/O pins after configuration.

Dual-purpose Avalon-ST interface clock input pin.

This pin is used for Avalon-ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

Dual-purpose Avalon-ST interface data valid input pin.

This pin is used for Avalon-ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

Dual-purpose fundamental reset pin that is only available when you use together with PCI Express^® (PCIe^®) hard IP (HIP).

When the PCIe HIP on a side (left or right) is enabled, the nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe nPERST signal to ensure that both ends of the link start link-training at the same time. The nPERST pins on a side are available as GPIOs only when the PCIe HIP on that side is not enabled.

When the pin is low, the transceivers are in reset. When the pin is high, the transceivers are out of reset. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin.

Connect this pin as defined in the Intel^® Quartus^® Prime software. This pin is powered by the VCCIO3V supply.

When VCCIO3V is connected to a 3.0-V supply, you must use a diode to clamp the 3.3V LVTTL PCIe input signal to the VCCIO3V power of the device.

When VCCIO3V is connected to any voltage other than 3.0V, you must use a level translator to shift down the voltage from 3.3V LVTTL to the corresponding voltage level powering the VCCIO3V pin.

For maximum compatibility, always use the bottom left PCIe HIP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe link.

These are the 3.0V I/O pins. Each H- or L- transceiver tile supports eight 3.0V I/O pins. These pins support 1.2V, 1.25V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.0V I/O standards.

For details about the supported I/O standards, refer to the Intel^® Stratix^® 10 Device Datasheet.

Connect these pins according to the I/O interface standard you are using. You must provide power to the VCCR_GXB, VCCT_GXB, and VCCH_GXB pins of a transceiver tile to enable the 3.0V I/O pins within that tile. For any transceiver tiles that have their VCCR_GXB, VCCT_GXB, and VCCH_GXB unpowered, the corresponding 3.0V I/O pins within that tile is disabled.

Using 3V I/O pins from an unpowered tile can potentially result in configuration failures.

Connect unused pins as defined in the Intel^® Quartus^® Prime software.

IO33_[5:0]_[7:0]

These are 3.3V I/O pins. The I/O bank is known as the 3.3V I/O bank and it is only available in the HF35 package of the GX400 (1SG040) and SX400 (1SX040) devices. These pins support 3.0V and 3.3V I/O.

The index of [5:0] represents the grouping of the I/O pins and the index of [7:0] represents the pin numbering within the same group. The I/O pin can be configured as an input or output within the same grouping index. When any of the pin within the same group is configured as an input or output, the remaining pins will be configured to the same I/O direction. The same I/O buffer setting such as the slew rate and weak pull-up functions will be applied for pins within the same grouping. Intel^® recommends you to plan the I/O resources before implementing your design.

For more details about the supported I/O standards and features, refer to the Intel^® Stratix^® 10 General Purpose I/O User Guide.

Fore more details about the I/O electrical specification, refer to the Intel^® Stratix^® 10 Device Datasheet.

Connect these pins according to the I/O interface standard used in your design. To enable the 3.3V I/O bank, you must provide 3.0V or 3.3V power to VCCIO3C and 1.8V power to VCCIO3D. For unused I/O pins, leave the pins as NC.

Tie VREFB3CN0 to GND.

LVDS[2][A,B,C,D,E, F,G,H,I,J,K,L,M,N]_[1:24][p,n]

LVDS[3][A,B,C,D,E,F,G,H,I,J,K,L,M,N]_[1:24][p,n]

DIFF_3[A,D]_[1:24][p,n]

These I/O banks are only available in the HF35 package of the GX 400 (1SG040), SX 400 (1ST040), and TX 400 (1SX040) devices. These pins support 1.2V, 1.25V, 1.35V, 1.5V, and 1.8V I/O standard. The LVDS, RSDS, and mini-LVDS I/O standards are only supported in the dedicated clock pin. The LVDS SERDES and EMIF functions are not supported in these I/O banks.

Bank 3D of the GX 400 (1SG040) and SX 400 (1SX040) devices in the HF35 package has a maximum of 30 I/O pins only.

DQS[0:47]

DQS[48:95]

DQS[0:47]

DQS[48:95]

DQSn[0:47]

DQSn[48:95]

DQSn[0:47]

DQSn[48:95]

DQ[0:47]

DQ[48:95]

DQ[0:47]

DQ[48:95]

Tie these pins to GND if you do not use the voltage sensor feature. For details on the usage of these pins, refer to the Intel^® Stratix^® 10 Analog to Digital Converter User Guide.

Do not drive VSIGP and VSIGN pins until the VCCADC power rail has reached 1.62V to prevent damage.

F[1,2]_TEMPDIODE0p

T[1,3]_TEMPDIODE1p

T[2,4]_TEMPDIODE4p

Connect this pin to an external temperature sensing device to allow sensing of the FPGA's temperature. If you do not use the temperature sensing diode with an external temperature sensing device, leave this pin unconnected.

For more information about the locations and channel numbers of the temperature sensors, refer to the Intel^® Stratix^® 10 Analog to Digital Converter User Guide.

F[1,2]_TEMPDIODE0n

T[1,3]_TEMPDIODE1n

T[2,4]_TEMPDIODE4n

Connect this pin to an external temperature sensing device to allow sensing of the FPGA's temperature. If you do not use the temperature sensing diode with an external temperature sensing device, leave this pin unconnected.

For more information about the locations and channel numbers of the temperature sensors, refer to the Intel^® Stratix^® 10 Analog to Digital Converter User Guide.

RZQ_[2][A,B,C,F,G,H,I,J,K,L,M,N]

RZQ_[3][A,B,C,D,E,F,G,H,I,J,K,L]

RZQ_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]

RZQ_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]

Reference pins for I/O banks. The RZQ pins share the same VCCIO with the I/O bank where they are located.

Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin.

When using OCT, tie these pins to GND through either a 240-Ω or 100-Ω resistor, depending on the desired OCT impedance. For more information about the OCT schemes, refer to the Intel^® Stratix^® 10 General Purpose I/O User Guide.

When you do not use these pins as dedicated input for the external precision resistor or as I/O pins, leave these pins unconnected.

When designing for device migration, you have the option to connect these pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration.

However, if device migration is not a concern, leave these pins floating.

The following guidelines are for the HF35 package of the Intel^® Stratix^® 10 GX 400 or Intel^® Stratix^® 10 SX 400 to Intel^® Stratix^® 10 GX 650 or Intel^® Stratix^® 10 SX 650 device migration:

• You must tie the I/O pin that is incompatible for vertical migration to GND.
• There are 48 I/O pins from bank 3C and 18 I/O pins from bank 3D that will be affected. You need to compare the device pin-outs and identify the affected pins.

For more information, refer to AN 921: Device Migration Guidelines for Intel^® Stratix^® 10 HF35 Package.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to the Electrical Characteristics in the Intel^® Stratix^® 10 Device Datasheet.

Use the Intel^® Stratix^® 10 Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

See Notes 2, 3, 4, 6, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to the Electrical Characteristics in the Intel^® Stratix^® 10 Device Datasheet.

Use the Intel^® Stratix^® 10 Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

See Notes 2, 3, 4, 6, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

Connect VCCPT to a 1.8V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:

• VCCIO_SDM and VCCIO_HPS
• VCCIO and VCCIO3V if these rails are using the same voltage level
• VCCBAT if this rail is using the same voltage level and the design security key feature is not required
• VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC with proper isolation filtering

Provide a minimum decoupling of 1uF for the VCCPT power rail near the VCCPT pin.

A floating voltage may be observed on VCCPT during device power-up and power-down sequencing due to VCCERAM, with the magnitude of the floating voltage being lower than VCCPT. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Stratix^® 10 Devices.

See Notes 2, 3, 4, 7, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

Connect VCCA_PLL to a 1.8V low noise switching regulator. With proper isolation filtering, you have the option to source VCCA_PLL from the same regulator as VCCPT.

See Notes 2, 3, 4, 7, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

VCCIO2[A,B,C,F,G,H,I, J,K,L,M,N]_F[1,2]

VCCIO3[A,B,C,D,E,F,G,H,I,J,K,L]_F[1,2]

These are the supply voltage pins for the I/O banks. Each bank can support a different voltage level.

Supported VCCIO standards include the following:

• Diff HSTL/HSTL(12,15,18)
• Diff SSTL/SSTL(12,125, 135, 15, 18)
• Diff HSUL/HSUL(12)
• Diff POD 12
• LVDS/Mini_LVDS/RSDS
• 1.2V, 1.5V, and 1.8V

These VCCIO guidelines only apply to non-HF35 package. If you are using the HF35 package of the GX 400 (1SG040), SX 400 (1SX040), and TX 400 (1ST040) devices, refer to the 3.3V I/O Pins table in this document for the VCCIO3C and VCCIO3D connection guidelines.

Connect these pins to 1.2V, 1.25V, 1.35V, 1.5V, or 1.8V supplies, depending on the I/O standard required by the specific bank.

You have the option to power down unused I/O banks by connecting their VCCIO pin to GND.

During the power-up sequence only, a transient current whose magnitude is less than the VCCIO operating static current may be observed as the VCCIO transistors become operational. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed.

When I/O bank 3A is used for AVST x16 or AVST x32 configuration mode, you must connect the VCCIO3A power supply to the VCCIO_SDM power supply for proper device functionality.

For more details, refer to the Intel^® Stratix^® 10 General Purpose I/O User Guide.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Stratix^® 10 Devices.

See Notes 2, 3, 4, 8, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

Connect these pins to 1.2V, 1.5V, 1.8V, 2.5V, or 3.0V supplies, depending on the I/O standard required by the specified bank.

VCCIO3V must be powered on for proper device operation even if the VCCIO3V banks are unused.

VCCR_GXB, VCCT_GXB, and VCCH_GXB must be powered up to operate the VCCIO3V bank.

For more details, refer to the Intel^® Stratix^® 10 General Purpose I/O User Guide.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Stratix^® 10 Devices.

See Notes 2, 3, 4, 8, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

Connect these pins to a 1.8V power supply. When dual-purpose configuration pins are used for configuration, tie VCCIO of the bank where the dual-purpose configuration pins reside to the same regulator as VCCIO_SDM.

When these pins require the same voltage level as VCCIO, you have the option to tie them to the same regulator as VCCIO.

Provide a minimum decoupling of 47nF for the VCCIO_SDM power rail near the VCCIO_SDM pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Stratix^® 10 Devices.

See Notes 2, 3, 4, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

Connect all VCCERAM pins to a 0.9V low noise switching power supply.

VCCPLLDIG_SDM must be sourced from the same regulator as VCCERAM with proper isolation filtering.

For more details, refer to the Intel^® Stratix^® 10 Device Datasheet.

See Notes 2, 3, 7, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

When using the design security volatile key, connect this pin to a non-volatile battery power source in the range of 1.2V - 1.8V.

When not using the volatile key, tie this pin to the 1.8-V VCCPT.

This pin must be properly powered as per the recommended voltage range as the power-on reset (POR) circuitry of the Intel^® Stratix^® 10 devices monitors VCCBAT.

Provide a minimum decoupling of 47nF for the VCCBAT power rail near the VCCBAT pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Stratix^® 10 Devices.

Connect these pins to a 1.8V low noise power supply through a proper isolation filter.

With proper isolation filtering, you have the option to source VCCPLL_SDM from the same regulator as VCCPT when all power rails require 1.8V.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 7 in Notes to Intel^® Stratix^® 10 Core Pins.

VREFB2[A,B,C,F,G,H,I,J,K,L,M,N]N0_F[1,2]

VREFB3[A,B,C,D,E,F,G,H,I,J,K,L]N0_F[1,2]

If VREF pins are not used, connect them to either the VCCIO in the bank in which the pins reside or GND.

See Notes 2, 8, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulators’ differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source.

You must connect the VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs.

You must supply a low noise 1.8V power supply to this pin if you are using the internal voltage sensors of the Intel^® Stratix^® 10 device.

When you are using the voltage sensors, tie this pin to VCCA_PLL with proper isolation filtering.

If you are not using the voltage sensors, tie this pin to VCCA_PLL.

F1_RREF_SDM

F2_RREF_SDM

Reference resistor input for the PLLs of the SDM interface.

Connect a 2kΩ +/-1% resistor to GND.

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[0] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel^® Stratix^® 10 Configuration User Guide.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[1] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel^® Stratix^® 10 Configuration User Guide.

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[2] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel^® Stratix^® 10 Configuration User Guide.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

PMBus Power Management Clock.

This pin is used as the clock pin for the PMBus interface.

This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel^® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V.

Connect this pin to the PMBus clock pin of your regulator.

When a –V device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.

When the PWRMGT_SCL pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain.

SDM_IO0

SDM_IO14

SDM_IO0

SDM_IO0

SDM_IO14

SDM_IO0

SDM_IO14

PMBus Power Management Serial Data.

This pin is used as the data pin for the PMBus interface.

This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel^® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V.

Connect this pin to the PMBus data pin of your regulator.

When a –V device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.

When the PWRMGT_SDA pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain.

SDM_IO11

SDM_IO12

SDM_IO16

SDM_IO12

SDM_IO16

SDM_IO11

SDM_IO12

SDM_IO16

SDM_IO11

SDM_IO12

SDM_IO16

PMBus Power Management Alert.

This pin is used as the ALERT function for the PMBus interface when the Intel^® Stratix^® 10 –V is the PMBus slave.

This pin requires a pull-up resistor to the 1.8V VCCIO_SDM supply. Intel^® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V.

Connect this pin to the PMBus ALERT pin of the external master controller.

When using the SmartVID feature with the Intel^® Stratix^® 10 –V device as a PMBus slave, you must connect the PWRMGT_ALERT signal along with the PWRMGT_SCL and PWRMGT_SDA signals to the PMBus master device to complete the SmartVID power management interface. The PMBus master device reads the VID codes from the Intel^® Stratix^® 10 slave and programs the voltage regulator to output the correct VID voltage.

When the PWRMGT_ALERT pin function of the SDM_IO pin is set to the PMBus, it is set to open-drain.

SDM_IO0

SDM_IO12

SDM_IO0

SDM_IO9

SDM_IO12

SDM_IO0

SDM_IO9

SDM_IO12

SDM_IO0

SDM_IO12

The CONF_DONE pin indicates all configuration data has been received.

For the Intel^® Stratix^® 10 GX 10M device, both F1_CONF_DONE and F2_CONF_DONE pins must be active before use mode can be initiated.

By default, Intel^® recommends using the SDM_IO16 pin to implement the CONF_DONE function.

If SDM_IO16 is unavailable, the CONF_DONE function can also be implemented using any unused SDM_IO pins.

Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are required to connect to an external 4.7-kΩ pull-down resistor for the CONF_DONE signal.

Connect the CONF_DONE pin to the external configuration controller when configuring using the Avalon^® -ST (AVST) interface.

You have an option to monitor this signal with an external component if you are using the active serial (AS) x4 configuration scheme.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO6

SDM_IO7

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

The INIT_DONE pin indicates the device has enter user mode upon completion of configuration. When used for this purpose, this pin must be enabled by the Intel^® Quartus^® Prime software.

When the INIT_DONE function is enabled, this pin will drive high when configuration is completed and the device goes into user mode.

Intel^® recommends you to use SDM_IO0 or SDM_IO16 to implement the INIT_DONE function when available as it has an internal weak pull-down for the correct function of INIT_DONE during power up.

If SDM_IO0 and SDM_IO16 are unavailable, SDM_IO5 can also be used for the INIT_DONE function when the configuration mode is set to Avalon^® –ST x8 or Avalon^® –ST x32 (AVST x8 or AVST x32) as these modes require an external 4.7–kΩ pull-down resistor.

If SDM_IO0, SDM_IO5, and SDM_IO16 are unavailable, the INIT_DONE function can also be implemented using any unused SDM_IO pins provided that an external 4.7–kΩ pull-down resistor is provided for the INIT_DONE signal.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO6

SDM_IO7

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

The CvP_CONFDONE pin indicates the device has received the complete bitstream during configuration via protocol (CvP) core image configuration.

When used for this purpose, enable this pin using the Intel^® Quartus^® Prime software.

Connect this output pin to an external logic that monitors the CvP operation. The VCCIO_SDM power supply must meet the input voltage specification of the receiving side.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

The SEU_ERROR pin drives high to indicate there is an SEU error message inside the SEU error queue. This pin stays high whenever the error message queue contains one or more error messages.

The SEU_ERROR signal goes low only when the SEU error message queue is empty. When used for this purpose, enable this pin using the Intel^® Quartus^® Prime software.

Connect this output pin to an external logic that monitors the SEU event.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

This is an active low, bidirectional pin. By default, this pin acts as an input pin to the SDM. When asserted externally for at least 5ms, this pin will generate interrupt to the SDM. The SDM will then initiate a cold reset procedure to the HPS and its peripherals. If the cold reset is generated from internal sources (for example, the HPS EL3 software), the SDM will switch this pin to output and drive a pulse to indicate reset. Once the cold reset procedure is complete, this pin will be switched back to input.

Connect this pin through a 1–10-kΩ pull up to the VCCIO_SDM supply. Do not connect this pin to the reset input of any connected quad serial peripheral interface (quad SPI) devices.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

Direct to factory input pin.

When using the remote system upgrade feature, this optional pin allows you to choose between factory or application image. Driving logic high into this pin will instruct the device to load factory image, while driving logic low into this pin will instruct the device to load the application image.

Connect this input pin to an external logic that manages the remote system upgrade of the device. By default, the external logic should provide logic low to this pin so that the application image will be the default image of the device, and only switch to factory image if required.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

Connect this pin to the positive terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel^® Quartus^® Prime ESRAM PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

• 20 ps peak-to-peak
• 1.42 ps RMS at 1e-12 BER
• 1.22 ps at 1e-16 BER

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

Connect this pin to the negative terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel^® Quartus^® Prime ESRAM PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

• 20 ps peak-to-peak
• 1.42 ps RMS at 1e-12 BER
• 1.22 ps at 1e-16 BER

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

Connect this pin to the positive terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel^® Quartus^® Prime HBM2 interface PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

• 20 ps peak-to-peak
• 1.42 ps RMS at 1e-12 BER
• 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2) IP is included in your design.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

Connect this pin to the negative terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Intel^® Quartus^® Prime HBM2 interface PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

• 20 ps peak-to-peak
• 1.42 ps RMS at 1e-12 BER
• 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2) IP is included in your design.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

VCCR_GXBL1[C,D,E]_T[1,3]

VCCR_GXBL1[K,L,M]_T[2,4]

Analog power, receiver, specific to each transceiver bank of the left (L) side or right (R) side of the device.

Connect VCCR_GXB pins to a 1.03V or 1.12V low noise switching regulator depending on the transceiver data rate.

VCCR_GXB and VCCT_GXB pins of each bank within a transceiver tile (L-tile or H-tile) must have the same voltage (either 1.03V or 1.12V). However, VCCR_GXB and VCCT_GXB of different banks within the same transceiver tile can have different voltages based on the configured transceiver data rates to further reduce power consumption of the transceiver tile. When the banks within a transceiver tile are powered at different voltages (for example, some banks operating at 1.03V while other banks operating at 1.12V), the xN clock lines are only allowed to transverse between contiguous banks operating at the same VCCR_GXB or VCCT_GXB voltages. The xN clock lines crossing boundaries of banks operating at different voltages is not allowed. For any input reference clock coming into a transceiver tile, that clock can be distributed to any bank within the tile even if the VCCR_GXB and VCCT_GXB operating voltages of the banks are different.

When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND.

Place a 22-nF decoupling capacitor between each VCCR_GXB power pin and GND pin on the back side of the BGA pin field.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

See Notes 2, 3, 4, 7, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

VCCT_GXBL1[C,D,E]_T[1,3]

VCCT_GXBL1[K,LM]_T[2,4]

Connect VCCT_GXB pins to a 1.03V or 1.12V low noise switching regulator depending on the transceiver data rate.

VCCR_GXB and VCCT_GXB pins of each bank within a transceiver tile (L-tile or H-tile) must have the same voltage (either 1.03V or 1.12V). However, VCCR_GXB and VCCT_GXB of different banks within the same transceiver tile can have different voltages based on the configured transceiver data rates to further reduce power consumption of the transceiver tile. When the banks within a transceiver tile are powered at different voltages (for example, some banks operating at 1.03V while other banks operating at 1.12V), the xN clock lines are only allowed to transverse between contiguous banks operating at the same VCCR_GXB or VCCT_GXB voltages. The xN clock lines crossing boundaries of banks operating at different voltages is not allowed. For any input reference clock coming into a transceiver tile, that clock can be distributed to any bank within the tile even if the VCCR_GXB and VCCT_GXB operating voltages of the banks are different.

When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND.

Place a 22-nF decoupling capacitor between each VCCT_GXB power pin and GND pin on the back side of the BGA pin field.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

See Notes 2, 3, 4, 7, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

VCCH_GXBL1_T[1,3]

VCCH_GXBR1_T[2,4]

Connect VCCH_GXB to 1.8V low noise switching regulator.

With a proper isolation filtering, you have the option to source VCCH_GXB from the same regulator as VCCPT.

To minimize the regulator switching noise impact on channel jitter performance, keep the switching frequency for VCCH_GXB regulator below 2 MHz. For OTN applications, the switching frequency for VCCH_GXB is recommended to be below 500 KHz.

Place a 22-nF decoupling capacitor between each VCCH_GXB power pin and GND pin on the back side of the BGA pin field.

A leakage voltage may be observed on the VCCH_GXB power rail before the VCCH_GXB is powered on due to leakage inside the device during the power-up and power-down sequencing. The total magnitude of this leakage voltage is lower than VCCH_GXB and this is an expected behavior.

During the power-up sequence only, a transient current whose magnitude is less than the VCCH_GXB static operating current may be observed. The floating voltage and transient current are expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed.

When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND.

See Notes 2, 3, 4, 7, and 10 in Notes to Intel^® Stratix^® 10 Core Pins.

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]p

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]p

T1_GXBL1[C,D,E,F]_RX_CH[0:5]P

T1_GXBL1[C,D,E,F]_REFCLK[0:5]p

T2_GXBL1[N,M,L,K]_RX_CH[0:5]P

T2_GXBL1[N,M,L,K]_REFCLK[0:5]p

T3_GXBL1[C,D,E,F]_RX_CH[0:5]P

T3_GXBL1[C,D,E,F]_REFCLK[0:5]p

T4_GXBL1[N,M,L,K]_RX_CH[0:5]P

T4_GXBL1[N,M,L,K]_REFCLK[0:5]p

These pins can be AC-coupled or DC-coupled when used. For more information, refer to the transceiver specifications in the Intel^® Stratix^® 10 Device Data Sheet.

Connect all unused GXB_RXp pins directly to GND.

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]n

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]n

T1_GXBL1[C,D,E,F]_RX_CH[0:5]n

T1_GXBL1[C,D,E,F]_REFCLK[0:5]n

T2_GXBL1[N,M,L,K]_RX_CH[0:5]n

T2_GXBL1[N,M,L,K]_REFCLK[0:5]n

T3_GXBL1[C,D,E,F]_RX_CH[0:5]n

T3_GXBL1[C,D,E,F]_REFCLK[0:5]n

T4_GXBL1[N,M,L,K]_RX_CH[0:5]n

T4_GXBL1[N,M,L,K]_REFCLK[0:5]n

These pins can be AC-coupled or DC-coupled when used. For more information, refer to the transceiver specifications in the Intel^® Stratix^® 10 Device Data Sheet.

Connect all unused GXB_RXn pins directly to GND.

T1_GXBL1[C,D,E,F]_TX_CH[0:5]p

T2_GXBL1[N,M,L,K]_TX_CH[0:5]p

T3_GXBL1[C,D,E,F]_TX_CH[0:5]p

T4_GXBL1[N,M,L,K]_TX_CH[0:5]p

T1_GXBL1[C,D,E,F]_TX_CH[0:5]n

T2_GXBL1[N,M,L,K]_TX_CH[0:5]n

T3_GXBL1[C,D,E,F]_TX_CH[0:5]n

T4_GXBL1[N,M,L,K]_TX_CH[0:5]n

T1_REFCLK_GXBL1[C,D,E,F]_CH[B,T]p

T2_REFCLK_GXBL1[N,M,L,K]_CH[B,T]p

T3_REFCLK_GXBL1[C,D,E,F]_CH[B,T]p

T4_REFCLK_GXBL1[N,M,L,K]_CH[B,T]p

High speed differential reference clock positive receiver channels, specific to each transceiver bank of the left (L) side or right (R) side of the device.

REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not used.

These pins should be AC-coupled when connected to any I/O standard other than the HCSL I/O standard. For the HCSL I/O standard, these pins must be DC-coupled. For example, PCIe* reference clocks should be DC-coupled if it uses the HCSL I/O standard.

Connect all unused pins individually to GND.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. For PCIe* , you must follow this clock requirement.

See Note 9 in Notes to Intel^® Stratix^® 10 Core Pins.

T1_REFCLK_GXBL1[C,D,E,F]_CH[B,T]n

T2_REFCLK_GXBL1[N,M,L,K]_CH[B,T]n

T3_REFCLK_GXBL1[C,D,E,F]_CH[B,T]n

T4_REFCLK_GXBL1[N,M,L,K]_CH[B,T]n

High speed differential reference clock complement, complementary receiver channel, specific to each transceiver bank of the left (L) side or right (R) side of the device.

REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not used.

These pins should be AC-coupled when connected to any I/O standard other than the HCSL I/O standard. For the HCSL I/O standard, these pins must be DC-coupled. For example, PCIe* reference clocks should be DC-coupled if it uses the HCSL I/O standard.

Connect all unused pins individually to GND.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. For PCIe* , you must follow this clock requirement.

See Note 9 in Notes to Intel^® Stratix^® 10 Core Pins.

You must connect the RREF_SPIAUX0 pin to a 2kΩ ±1% resistor to GND.

In the PCB layout, the trace from this pin to the resistor must be routed so that it avoids any aggressor signals.

Connect VCCH_GXE to a 1.1V low noise switching regulator.

VCCH_GXE must be powered up even when the E-tile transceivers are not used.

Connect VCCRT_GXE to VCCERAM through an LC filter. For more information about the LC filter design, refer to the Intel^® Stratix^® 10 Power Management User Guide.

VCCRT_GXE must be powered up even when the E-tile transceivers are not used.

You must source the VCCRTPLL_GXE from the VCCRT_GXE with proper isolation filtering.

Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel^® Stratix^® 10 Power Management User Guide.

VCCRTPLL_GXE must be powered up even when the E-tile transceivers are not used.

Connect VCCCLK_GXE to a 2.5V low noise switching regulator.

VCCCLK_GXE must be powered up even when the E-tile transceivers are not used.

GXE(L8, R9)(A, B, C)_RX_CH[0:23][p,n]

For PAM4, no off-chip AC-coupling capacitor is required provided that the RX input common mode voltage is between (GND + 300mV) and (VCCH_GXE-300mV), and the RX input amplitude differential voltage is less than 1200mVp-p. For PAM4, the absolute maximum positive voltage at the RX input of the SerDes is VCCH_GXE to maintain linearity.

For NRZ, no off-chip AC-coupling capacitor is required provided that the RX input common mode voltage is between GND and VCCH_GXE, and the RX input amplitude differential voltage is less than 1200mVp-p. For NRZ, the absolute maximum positive voltage at the RX input to the SerDes is (VCCH_GXE + 300mV) to prevent forward-biasing of the ESD diodes.

For more information, refer to the Electrical Characteristics section in the Intel^® Stratix^® 10 Device Datasheet.

When the RX input common mode voltage is outside its required range (PAM4 or NRZ), external AC-coupling capacitors must be used. When using external AC-coupling capacitors, the RX termination is to the VCCH_GXE supply. A typical value of 100nF can be used as the external AC-coupling capacitor. Select a capacitor package (SMD) similar to that of the trace width to reduce in-line parasitics, and a material of X7R quality or higher. For high speed SerDes, mounting launch pad must be carefully designed.

For more information about the external AC-coupling, refer to the Intel^® Stratix^® 10 E-Tile Transceiver PHY User Guide.

Leave unused pins floating.

High speed differential reference clock connects to the E-tile transceiver of the left (L) side or right (R) side of the device.

REFCLK_GXE is supplied to both RX and TX independently.

REFCLK_GXE can be used as dedicated clock input pins for core clock generation by configuring transceiver channel (Native PHY IP core) in the PLL mode.

Supported I/O standard:

• LVPECL

No off-chip AC-coupling capacitor is required. The default internal REFCLK inputs are 2.5-V LVPECL with a 50-Ω termination.

Optional external termination is 2.5-V LVPECL or 3.3-V LVPECL. For more information about the external termination, refer to section 4.1 in the E-Tile Transceiver PHY User Guide.

Tie each unused REFCLK pin to GND through a 1-kΩ resistor.

REFCLK[1] must always be bonded out on board and connected to a clock source in case dynamic reconfiguration of REFCLK is planned. For more details on how to use it, refer to section 7.12 in the E-tile Transceiver PHY User Guide.

Preservation of unused transceiver channels may need extra REFCLK_GXE to be bonded out on board based on use cases. For more details, refer to section 3.1.10 Unused Transceiver Channel in the E-tile Transceiver PHY User Guide.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

Connect VCCH_GXP to a 1.8V low-noise switching regulator. To minimize the regulator switching noise impact on channel jitter performance, keep the regulator switching frequency below 1 MHz. Place a 22–nF decoupling capacitor between each VCCH_GXP power pin and GND pin on the back side of the BGA pin field.

VCCH_GXP must be filtered through the ferrite bead.

VCCH_GXP must be powered up even when the P-tile transceivers are not used.

Connect VCCRT_GXP to a 0.9V low-noise switching regulator. With a proper isolation filtering, you have the option to source VCCRT_GXP from the same regulator as VCCERAM.

VCCRT_GXP must be powered up even when the P-tile transceivers are not used.

Connect VCCCLK_GXP to a 1.8V low-noise switching regulator. With a proper isolation filtering, you have the option to source VCCCLK_GXP from the same regulator as VCCPT.

VCCCLK_GXP must be powered up even when the P-tile transceivers are not used.

Connect the VCCFUSE_GXP pin to the 0.9V VCCERAM power. Connecting to the VCCERAM power rail adheres to the power-down sequencing requirement for the VCCFUSE_GXP supply. Do not leave this pin floating or tie it to GND.

VCCFUSE_GXP must be powered up even when the P-tile transceivers are not used.

Connect each IO_AUX_RREF pin to a 2.8KΩ resistor (±1%) to GND.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 2.8KΩ resistor between this pin and GND.

Connect each pin to 169Ω (±1%, 100 ppm/C) precision resistor to GND if the UltraPath Interconnect (UPI)/ PCIe* is 85Ω impedance.

Place this resistor very close to the IO_RESREF pin. Avoid routing any noisy signals next to this reference resistor or its traces. Tie resistor to GND plane through a via placed very close to the reference resistor.

External reference resistor parasitic capacitance load must be less than 6.5pF.

In a PCI Express* ( PCIe* ) adapter card implementation, connect the PCIe* nPERST signal from the PCIe* edge connector to each P-tile transceiver bank I_PIN_PERST_N input.

Use a level translator to fan out and change the 3.3V open-drain nPERST signal from the PCIe* connector to the 1.8V I_PIN_PERST_N input of each P-tile transceiver that is used on the board.

Provide a 1.8V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3V PCIe* nPERST signal on the adapter card.

For the UltraPath Interconnect (UPI) mode, contact Intel^® for guidance.

If the tile is unused, tie to GND.

Differential-based transmitter pins, specific to P-tile transceivers on the left (L) side and right (R) side of the device.

These pins support NRZ encoding up to 16Gbps.

Connection guidelines for the PCIe* and UltraPath Interconnect (UPI) modes are as follow:

• PCIe* mode—TX pins must be AC coupled. Capacitor values range from 176nF to 256nF per PCIe* Gen 4 specification.
• UPI mode—TX pins must be DC coupled.

When these pins are not used, they can be floating.

Differential-based receiver pins, specific to P-tile transceivers on the left (L) side and right (R) side of the device.

These pins support NRZ encoding up to 16Gbps.

For the HCSL I/O standard, it only supports DC coupling. In the PCIe* configuration, DC-coupling is allowed on the REFCLK if the selected REFCLK I/O standard is the HCSL I/O standard.

Connect all unused pins individually to GND.

You must connect a 100MHz reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ±300ppm requirement. For 2x8 modes, you can connect both reference clock inputs to the same clock source or connect to two independent clock sources.

If the P-tile is completely unused but still has power applied, tie both REFCLK inputs to GND.

For PCIe* only system, connect to GND.

For UltraPath Interconnect (UPI) applications, connect the strap pins as follows:

• For a two socket (2S) Intel^® Xeon^® system, connect to GND.
• For a four socket (4S) Intel^® Xeon^® system, pull up through a 10kΩ resistor to VCCCLK_GXP (1.8V).

For the UltraPath Interconnect (UPI) mode, contact Intel^® for guidance.

For PCIe* only system, connect both ID pins to GND.

For UltraPath Interconnect (UPI) applications, connect these ID pins to the corresponding CPU ID of the UPI interface.

• NODE_ID0 connects to CPU0.
• NODE_ID1 connects to CPU1.

If the tile is unused, tie to GND.

For the UltraPath Interconnect (UPI) mode, contact Intel^® for guidance.

The VCCL_HPS power supply voltage could vary from 0.8V to 0.94V for –1V, –2V, or –3V devices with the SmartVID feature depending on the SmartVID setting in the device. When using –2L or –3X devices, you must connect to either 0.9V or 0.94V supply. If you are using 0.9V supply, VCCL_HPS can be connected to VCCERAM.

VCCL_HPS can be shared with VCC and VCCP if they are at the same voltage level only when using –1V, –2V, or –3V devices (with the SmartVID feature). VCCL_HPS cannot be shared with VCC and VCCP when using –2L or –3X devices. VCCL_HPS always needs to be equal to VCCPLLDIG_HPS.

Use the Intel^® Stratix^® 10 Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer to determine the current requirements for VCCL_HPS and other power supplies.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 6 in Notes to Intel^® Stratix^® 10 HPS Pins.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCL_HPS floating or connected to GND.

Connect these pins to 1.8V power supply. If these pins have the same voltage requirement as VCCIO and VCCIO_SDM, you have the option to source VCCIO_HPS pins from the same regulator as VCCIO and VCCIO_SDM.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 8 in Notes to Intel^® Stratix^® 10 HPS Pins.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCIO_HPS floating or connected to GND.

Connect these pins to a 1.8V low noise power supply through a proper isolation filter. You have the option to share VCCPLL_HPS with the same regulator as VCCPT when all power rails require 1.8V but only with a proper isolation filter.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 7 in Notes to Intel^® Stratix^® 10 HPS Pins.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCPLL_HPS floating or connected to GND.

Connect this to the VCCL_HPS with proper isolation filtering.

For more information about isolation filters, refer to AN583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave VCCPLLDIG_HPS floating or connected to GND.

Clock input pin that drives the main PLL.

Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS. For more information, refer to the valid frequency range of the clock source in the Intel^® Stratix^® 10 Device Datasheet.

HPS JTAG test clock input pin.

Connect this pin through a 1-kΩ – 10-kΩ pull-down resistor to GND. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. The option to access the HPS JTAG interface through the FPGA JTAG pins is available in the Intel^® Quartus^® Prime Pro Edition. For more details, refer to AN 802: Intel^® Stratix^® 10 SoC Device Design Guidelines.

HPS JTAG test mode select input pin.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

HPS JTAG test data output pin.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

HPS JTAG test data input pin.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

General purpose input output.

Ensure that the I/O standard used is compatible with VCCIO_HPS.

HPS_IOA_[1..24]

HPS_IOB_[1..24]

SDMMC command line

Pull this pin high on the board with a weak pull-up resistor. For example, a 10-kΩ to VCCIO_HPS.

SDMMC Data 3

When using SD card, there is an existing 50-kΩ pull-up on SDMMC Data Bit 3 which can be disabled in the HPS software by using the SET_CLR_CARD_DETECT (ACMD42) command. This is not applicable to the eMMC flash.

NAND Write Enable

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

NAND Read Enable

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

NAND Ready/Busy

Connect this pin through a 1-kΩ to 10-kΩ pull-up resistor to VCCIO_HPS.

NAND Chip Enable

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

SPIM0 Slave Select 0

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

SPIM0 Slave Select 1

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

SPIM1 Slave Select 0

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

SPIM1 Slave Select 1

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

SPIS0 Slave Select 0

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

SPIS1 Slave Select 0

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

UART0 Clear to Send

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

UART0 Request to Send

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

UART1 Clear to Send

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

UART1 Request to Send

See Note 11 in Notes to Intel^® Stratix^® 10 HPS Pins.

0.85

SmartVID

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

0.85

SmartVID

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

SmartVID

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

0.85

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

SmartVID

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCR_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

Connect the VCCT_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

0.85

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

Connect the VCCR_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

Connect the VCCT_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

SmartVID

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

0.85

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

SmartVID

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCR_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

Connect the VCCT_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

0.85

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCL_HPS to the same regulator as VCCERAM when the power rails require the same voltage level. You may also connect the VCCPLLDIG_SDM and VCCPLLDIG_HPS power rails to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

Connect the VCCR_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

Connect the VCCT_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

SmartVID

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

SmartVID

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCR_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

Connect the VCCT_GXB to a dedicated 1.12V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

0.85

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCPLLDIG_SDM to the same regulator as the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect VCCRT_GXE to a dedicated 0.9V power supply. You may source VCCRT_GXE from VCCERAM through an LC filter. You may also source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead.

When implementing a filtered supply topology, you must considered the IR drop across the filter.

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level. For better performance and in order to meet PCIe* Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz to 100MHz bandwidth.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel^® Stratix^® 10 Device Datasheet.

You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Stratix^® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect VCCM_WORD_(BL,TL) to a 2.5V power supply.

Connect VCCCLK_GXE to a dedicated 2.5V power supply.

You have the option to share VCCCLK_GXE with VCCM_WORD if the VRM tolerance is ±100mV or better.

When sharing, filter the VCCCLK_GXE with a ferrite bead.

You may source VCCIO, VCCIO_SDM, and VCCIO3V from the same regulator if they are at the same 1.8V voltage level.

SmartVID

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Intel^® Stratix^® 10 TX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

Connect the VCCERAM to a dedicated 0.9V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect VCCRT_GXE to VCCERAM through an LC filter. For more information about the LC filter design, refer to the Intel^® Stratix^® 10 Power Management User Guide.

You may source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead.

Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel^® Stratix^® 10 Power Management User Guide.