Application Notes

Title	Published Date	End market	Device
AN 866: Mitigating and Debugging Single Event Upsets in Intel Quartus Prime Standard Edition	2018-09-24
AN 870: Stencil Computation Reference Design	2018-10-10	End Market	Intel® Arria® 10
AN 871: Quick Guide for Intel Arria 10 and Intel Cyclone 10 GX Transceiver High-Speed Link Tuning	2018-09-26		Intel® Cyclone® 10 GX\|Intel® Arria® 10
AN 875: Intel Stratix 10 E-Tile PCB Design Guidelines	2018-09-21		Intel® Stratix® 10
Using Intel Arria 10 SoC FPGA Early I/O Release	2018-10-11		Intel® Arria® 10
AN 114: Board Design Guidelines for Intel Programmable Device Packages	2018-10-09
AN 320: Using Intel FPGA IP Evaluation Mode	2018-10-22		All PLDs
AN 737: SEU Detection and Recovery in Intel Arria 10 Devices	2018-09-04	Test & Measurement	Intel® Arria® 10
AN 757: 1G/2.5G Ethernet Design Examples	2018-11-12	End Market	All PLDs
AN 784: Partial Reconfiguration over PCI Express Reference Design for Intel Arria 10 Devices	2018-09-24		Intel® Arria® 10
AN 797: Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Development Board	2018-09-24		Intel® Arria® 10
AN 806: Hierarchical Partial Reconfiguration Tutorial for Intel Arria 10 GX FPGA Development Board	2018-09-28		Intel® Arria® 10
AN 813: Hierarchical Partial Reconfiguration over PCI Express Reference Design for Arria 10 Devices	2018-09-24		Intel® Arria® 10
AN 817: Static Update Partial Reconfiguration Tutorial: for Intel Arria 10 GX FPGA Development Board	2018-10-12	Broadcast\|Computer & Storage\|Wireline\|Automotive	Intel® Arria® 10
AN 818: Static Update Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board	2018-10-12	Broadcast\|Computer & Storage\|Wireline\|Automotive	Intel® Stratix® 10
AN 819: Partial Reconfiguration over PCI Express Reference Design for Intel Stratix 10 Devices	2018-09-24		Intel® Stratix® 10
AN 820: Hierarchical Partial Reconfiguration over PCI Express Reference Design: for Intel Stratix 10 Devices	2018-11-13		Intel® Stratix® 10
AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board	2018-09-24		Intel® Stratix® 10
AN 826: Hierarchical Partial Reconfiguration Tutorial for Intel Stratix 10 GX FPGA Development Board	2018-09-28		Intel® Stratix® 10
AN 827: Unified Tool for Generating Programming Files	2018-10-29
AN 845: Signal Tap Tutorial for Intel Arria 10 Partial Reconfiguration Design	2018-10-08		Intel® Arria® 10
AN 851: Incremental Block-Based Compilation Tutorial: for Intel Arria 10 FPGA Development Board	2018-11-10	Wireless\|Computer & Storage\|Consumer\|Wireline	Arria Series\|Stratix Series
Compiling and Customizing an Intel Arria 10 Custom Platform for OpenCL	2018-10-30		Intel® Arria® 10
Differences Among Intel SoC Device Families	2018-08-22		Cyclone® V\|Intel® Arria® 10\|Arria® V\|Intel® Stratix® 10
Intel Stratix 10 Device Design Guidelines	2018-09-24		Intel® Stratix® 10
Intel Stratix 10 SoC Device Design Guidelines	2018-09-24	Wireline	Intel® Stratix® 10
Introduction to Intel FPGA IP Cores	2018-10-24
Simulation Quick-Start for ModelSim - Intel FPGA Edition: Intel Quartus Prime Pro Edition	2018-09-25	Wireless\|Industrial\|Wireline\|Military\|Broadcast\|Test & Measurement\|Computer & Storage\|Consumer\|Automotive	Intel® Cyclone® 10 GX\|Intel® Stratix® 10\|Intel® Arria® 10
AN 100: In-System Programmability Guidelines	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 265: Using Altera MAX Series as Microcontroller I/O Expanders	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 286: Implementing LED Drivers in Altera MAX Series	2017-12-13		MAX® V\|MAX® II\|Intel® MAX® 10
AN 294: Crosspoint Switch Matrices in Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software	2017-12-18		Intel® Cyclone® 10\|Intel® Arria® 10
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming	2014-09-22		Cyclone® IV\|Intel® Cyclone®\|Arria Series\|Stratix® II\|MAX Series\|Cyclone® III\|MAX® V\|Stratix® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Intel® Arria® 10\|Arria® V\|Stratix® IV\|Stratix® III\|Arria® II\|Intel® MAX® 10\|Cyclone® II\|Stratix Series
AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems	2017-11-06	Wireline	Cyclone® IV\|Intel® Cyclone® 10 LP\|Cyclone® III\|Intel® MAX® 10
AN 485: Serial Peripheral Interface Master in Altera MAX Series	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 486: SPI to I2C Using Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 488: Stepper Motor Controller Using Altera MAX Series	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 490: Altera MAX Series as Voltage Level Shifters	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 491: Power Sequence Auto Start Using Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 492: CF+ Interface Using Altera MAX Series	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 493: I2C Battery Gauge Interface Using Altera MAX Series	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 495: IDE/ATA Controller Using Altera MAX Series	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 496: Using the Internal Oscillator IP Core	2017-11-06		Intel® Cyclone® 10 GX\|Cyclone® IV\|Cyclone® III\|MAX® V\|Stratix® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Intel® Arria® 10\|Intel® Cyclone® 10 LP\|Arria® V\|Arria® II\|Intel® MAX® 10
AN 498: LED Blink Using Power Sequencing in Altera MAX Series	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 500: NAND Flash Memory Interface with Altera MAX Series	2014-09-22		MAX® II\|MAX® V\|Intel® MAX® 10
AN 501: Pulse Width Modulation Using Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 502: Implementing SMBus Controller in Altera MAX Series	-		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 509: Multiplexing SDIO Devices Using Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 630: Real-Time ISP and ISP Clamp for Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 631: Replacing Serial EEPROMs with User Flash Memory in Altera MAX Series	2014-09-22		MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores	2016-05-02		Cyclone® V\|Arria® V\|Stratix® V
AN 687: Implementing QPI Using the Transceiver Native PHY IP Core in Stratix V Devices	2015-12-17		Stratix® V
AN 696: Using the JESD204B MegaCore Function in Arria V Devices	2015-05-11	Wireline	Arria® V
AN 699: Using the Altera Ethernet Design Toolkit	2016-05-13		Intel® Arria® 10
AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY	2017-11-06		Intel® Arria® 10
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller	2017-09-22	Test & Measurement\|Industrial\|Consumer\|Medical	Cyclone Series\|Arria Series
AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report	2015-05-11		Stratix® V
AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report	2016-06-13		Stratix® V
AN 713: DC Coupling in Stratix V Devices	2014-08-20		Stratix® V
AN 717: Nios II Gen2 Hardware Development Tutorial	-		Intel® MAX® 10\|All PLDs
AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report	2014-09-22	Wireline	Stratix® V
AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor	2015-05-04	Wireline	Intel® Arria® 10
AN 730: Nios II Processor Booting Methods in MAX 10 FPGA Devices	2017-02-21		Intel® MAX® 10
AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report	2015-02-09		Stratix® V
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines	2015-05-04		Cyclone® IV\|Stratix® II\|Cyclone® III\|Stratix® V\|Cyclone® V\|Intel® Arria® 10\|Arria® V\|Stratix® IV\|Stratix® III\|Arria® II\|Cyclone® II
AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ)	2016-05-20	Wireless\|Wireline\|Military\|Test & Measurement\|Consumer\|Medical	Intel® Cyclone®\|Stratix® V\|Cyclone® V\|Intel® Arria® 10\|Arria® V\|Arria®
AN 738: Intel Arria 10 Device Design Guidelines	2017-06-30		Intel® Arria® 10
AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor	2017-02-21		Intel® MAX® 10
AN 742: PMBus SmartVID Controller Reference Designs	2017-05-08		Intel® Arria® 10
AN 745: Design Guidelines for Intel FPGA DisplayPort Interface	2018-01-22	Broadcast	Intel® Cyclone® 10 GX\|Cyclone® V\|Intel® Arria® 10\|Arria® V\|Stratix® V
AN 746: SDI II Triple-Rate Reference Designs for Intel Arria 10 Devices	2017-05-08	Broadcast	Intel® Arria® 10
AN 747: Implementing PHYLite in Intel Arria 10 Devices Design Examples	2017-05-08		Intel® Arria® 10
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report	2015-12-18		Intel® Arria® 10
AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report	2015-11-02		Intel® Arria® 10
AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)	2015-12-30		Arria® V
AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines	2017-05-08		Intel® Arria® 10
AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices	2017-05-08	Broadcast	Intel® Arria® 10
AN 770: Partially Reconfiguring a Design on Intel Arria 10 SoC Development Board	2017-11-06		Intel® Arria® 10
AN 773: Drive-On-Chip Reference Design for MAX 10 Devices	2017-11-24	Industrial\|Automotive	Intel® MAX® 10
AN 776: Intel Arria 10 UHD Video Reference Design	2018-01-11	Broadcast\|Medical\|Military	Intel® Arria® 10
AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores	2018-01-12		Intel® Arria® 10
AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report	2017-12-18		Intel® Arria® 10
AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report	2017-12-18		All PLDs
AN 793: Intel Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design	2017-06-13	Broadcast	Intel® Arria® 10
AN 805: Hierarchical Partial Reconfiguration of a Design on Intel Arria 10 SoC Development Board	2017-11-06		Intel® Arria® 10
AN 808: Migration Guidelines from Arria 10 to Stratix 10 for 10G Ethernet Subsystem	2017-06-19		Intel® Stratix® 10\|Intel® Arria® 10
AN 809: SerialLite III IP Core Feature and Interface Differences between Stratix 10, Arria 10, and Stratix V	2017-06-19		Intel® Arria® 10\|Stratix® V\|Intel® Stratix® 10
AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report	2017-12-18		Intel® Arria® 10
AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design	2018-01-30	Wireless\|Broadcast\|Test & Measurement\|Industrial\|Consumer\|Wireline\|Medical\|Military	Intel® Arria® 10
AN 821: Interface Planning for Intel Stratix 10 FPGAs	2017-12-15		Stratix Series
AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices	2017-12-18		Intel® Stratix® 10
AN 824: Intel FPGA SDK for OpenCL Board Support Package Floorplan Optimization Guide	2017-08-08	End Market	Intel® Arria® 10
AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design	2017-12-15		Intel® Stratix® 10
AN 831: Intel FPGA SDK for OpenCL Host Pipelined Multithread	2017-11-20		All PLDs
AN 833: Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design	2017-12-19		Intel® Stratix® 10
AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface	2017-12-18	Wireless\|Industrial\|Wireline\|Military\|Broadcast\|Test & Measurement\|Computer & Storage\|Consumer\|Automotive\|Medical	Intel® Stratix® 10
AN 837: Design Guidelines for Intel FPGA HDMI	2018-01-22	Broadcast	Intel® Cyclone® 10 GX\|Intel® Arria® 10\|Arria® V\|Stratix® V
AN 838: Interoperability between Intel Arria 10 NBASE-T Ethernet Solution with Aquantia* Ethernet PHY Reference Design	2018-01-12		Intel® Arria® 10
AN 839: Design Block Reuse Tutorial for Intel Arria 10 FPGA Development Board	2018-01-15	Wireless\|Computer & Storage\|Consumer\|Wireline	Arria Series\|Stratix Series
AN-693: Remote Hardware Debugging over TCP/IP for Altera SoC	2015-05-11		Cyclone® IV\|Intel® Cyclone®\|Arria Series\|Stratix® II\|MAX Series\|Cyclone® III\|MAX® V\|Stratix® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Intel® Arria® 10\|Arria® V\|Stratix® IV\|Stratix® III\|Arria® II\|Intel® MAX® 10\|Cyclone® II\|Stratix Series
AN-705: Scalable 10G Ethernet MAC using 1G/10G PHY	2016-05-13		Stratix® V
AN-720: Simulating the ASMI Block in Your Design	2015-08-03		Cyclone® V\|Intel® Arria® 10\|Arria® V\|MAX® V\|Stratix® V
AN-731: Simultaneous Switching Noise Guidelines for Intel Cyclone 10 LP, Cyclone IV, and Cyclone III Devices	2017-11-06		Cyclone® IV\|Intel® Cyclone® 10 LP\|Cyclone® III
AN-744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices	2016-04-27		Intel® Arria® 10
AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report	2016-12-06		Intel® Arria® 10
AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel Stratix 10 Devices	2018-01-23		Intel® Stratix® 10
AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design	2015-12-14		Intel® Arria® 10\|Arria® V\|Stratix® IV\|Stratix® V
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP)	2015-11-02		Cyclone® IV\|Arria Series\|MAX Series\|Stratix® II\|Cyclone® III\|MAX® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Arria® V\|Stratix® III\|Intel® MAX® 10\|Intel® Cyclone®\|Stratix® V\|Intel® Arria® 10\|Stratix® IV\|Arria® II\|Cyclone® II\|Stratix Series
AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design	2017-02-01		Intel® Arria® 10
AN795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria 10 Devices	2017-02-01		Intel® Arria® 10
Altera 1588 System Solution	2016-01-28		Arria® V
Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report	2015-06-25	Wireline	Arria® V
Arria 10 SoC Device Design Guidelines	2017-05-08	Broadcast\|Wireless\|Computer & Storage\|Automotive\|Military	Intel® Arria® 10
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms	2016-12-13		Cyclone® IV\|Arria Series\|Stratix® II\|MAX Series\|Cyclone® III\|MAX® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Arria® V\|Stratix® III\|Intel® MAX® 10\|Intel® Cyclone®\|Stratix® V\|Intel® Arria® 10\|Stratix® IV\|Arria® II\|Cyclone® II\|Stratix Series
Creating an FPGA Power Tree	-		Stratix® V
Cyclone V SoC Power Optimization	2015-02-09	Wireless\|Industrial\|Wireline\|Military\|Broadcast\|Test & Measurement\|Consumer\|Automotive\|Medical	Cyclone® V
Designing for Stratix 10 Devices with Power in Mind	2016-06-14		Intel® Stratix® 10
Drive-On-Chip Reference Design	2015-06-24	Industrial\|Military\|Medical\|Broadcast	Cyclone® IV\|Arria Series\|Stratix® II\|MAX Series\|Cyclone® III\|MAX® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Arria® V\|Stratix® III\|Intel® MAX® 10\|Intel® Cyclone®\|Stratix® V\|Intel® Arria® 10\|Stratix® IV\|Arria® II\|Cyclone® II\|Stratix Series
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification	2015-12-01	Industrial\|Automotive	Cyclone® V\|Intel® Arria® 10\|Intel® MAX® 10
Guidelines for Developing a Nios II HAL Device Driver	2015-06-12		Cyclone® IV\|Arria Series\|Stratix® II\|MAX Series\|Cyclone® III\|MAX® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Arria® V\|Stratix® III\|Intel® MAX® 10\|Intel® Cyclone®\|Stratix® V\|Intel® Arria® 10\|Stratix® IV\|Arria® II\|Cyclone® II\|Stratix Series
Guidelines for Handling J-Lead, QFP, BGA, FBGA, and Lidless FBGA Devices	2017-06-28		Cyclone® IV\|Arria Series\|MAX Series\|Stratix® II\|Cyclone® III\|MAX® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Arria® V\|Stratix® III\|Intel® MAX® 10\|Intel® Cyclone®\|Stratix® V\|Intel® Arria® 10\|Stratix® IV\|Arria® II\|Cyclone® II\|Stratix Series
Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices	2013-12-06		Arria® V
Intel Arria 10 SoC Secure Boot User Guide	2017-11-06	Broadcast\|Test & Measurement\|Computer & Storage\|Industrial\|Consumer\|Wireline\|Medical\|Military	Intel® Arria® 10
Intel Cyclone 10 GX Device Design Guidelines	2017-11-06	Industrial	Intel® Cyclone® 10 GX
Interlaken IP Core Feature and Interface Differences Between Stratix 10, Arria 10, and Stratix V Devices	2017-06-12	Wireless\|Industrial\|Wireline\|Military\|Broadcast\|Test & Measurement\|Computer & Storage\|Consumer\|Automotive\|Medical	Stratix® V\|Intel® Stratix® 10\|Intel® Arria® 10
Nios II Classic Processor Reference Guide	2015-06-17	Wireless\|Broadcast\|Consumer\|Industrial\|Wireline\|Automotive	Cyclone® V
Nios II Flash Accelerator Using Max10	2015-06-30		Intel® MAX® 10
Nios II Gen2 Migration Guide	2015-06-12		Cyclone® IV\|Intel® Cyclone®\|Arria Series\|Stratix® II\|MAX Series\|Cyclone® III\|MAX® V\|Stratix® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Intel® Arria® 10\|Arria® V\|Stratix® IV\|Stratix® III\|Arria® II\|Intel® MAX® 10\|Cyclone® II\|Stratix Series
PCB Stackup Design Considerations for Intel FPGAs	2017-06-28	Wireless\|Industrial\|Military\|Computer & Storage\|Consumer\|Medical\|Wireline\|Broadcast\|Test & Measurement\|Automotive	Cyclone® IV\|Cyclone® III\|MAX® V\|Intel® Stratix® 10\|Cyclone® V\|Arria® V\|Intel® MAX® 10\|Stratix® V\|Intel® Cyclone® 10\|Intel® Arria® 10\|Stratix® IV\|Arria® II
PCI Express Avalon -MM DMA Reference Design	2017-05-08	Industrial	Cyclone® V\|Intel® Arria® 10\|Arria® V\|Stratix® V
PCI Express DMA Reference Design Using External Memory	2017-05-17	Industrial	Cyclone® V\|Intel® Arria® 10\|Arria® V\|Stratix® V
PCI Express: Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface	2017-05-08	Computer & Storage	Intel® Arria® 10\|Stratix® V\|Intel® Stratix® 10
Putting Altera MAX Series in Hibernation Mode Using User Flash Memory	2016-01-14	Broadcast	MAX® II\|MAX Series\|MAX® V\|Intel® MAX® 10
Using the Altera PDN Tool to Optimize Your Power Delivery Network Design	2015-07-08		Cyclone® IV\|Intel® Cyclone®\|Arria Series\|MAX Series\|Stratix® II\|Cyclone® III\|MAX® V\|Stratix® V\|Intel® Stratix® 10\|Cyclone® V\|MAX® II\|Intel® Arria® 10\|Arria® V\|Stratix® IV\|Stratix® III\|Arria® II\|Intel® MAX® 10\|Cyclone® II\|Stratix Series
Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices	2015-12-04		Cyclone® V\|Arria® V
Vision Processing with the Canny Edge Detection Reference Design	2015-02-14	Broadcast\|Industrial\|Automotive\|Medical\|Military	Cyclone® V\|Intel® Arria® 10
Vision Processing with the Canny Edge Detection Reference Design	2015-02-14	Broadcast\|Industrial\|Automotive\|Medical	Cyclone® V\|Intel® Arria® 10
DDR and DDR2 SDRAM ECC Reference Design Application Note.pdf	-
Soldering Module Packages Having Large Asymmetric Pads.pdf	-
10-Gbps Ethernet Interoperability Hardware Demonstration Reference Design, Application Note.pdf	-
10-Gbps Ethernet Reference Design User Guide.pdf	-
24K FFT for 3GPP LTE RACH Detection.pdf	-
4K Format Conversion Reference Design.pdf	-
AES3/EBU Reference Design Application Note.pdf	-
ALTMEMPHY Design Tutorials; External Memory Interface Handbook.pdf	-
ALTMEMPHY Design Tutorials; External Memory Interface Handbook.pdf	-
AN 095: In-System Progammability in MAX Devices.pdf	-
AN 109: Using the HP 3070 Tester for In-System Programming.pdf	-
AN 113: Plastic Package Reliability & Testing.pdf	-
AN 119: Implementing High-Speed Search Applications with Altera CAM.pdf	-
AN 132: Implementing Multiprotocol Label Switching with Altera PLDs.pdf	-
AN 174: Excalibur Solutions - Hello_world.c version 2.0 October 2001.pdf	-
AN 185: Thermal Management Using Heat Sinks.pdf	-
AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs.pdf	-
AN 224: High-Speed Board Layout Guidelines.pdf	-
AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices.pdf	-
AN 240:Simulating Excalibur Systems.pdf	-
AN 242: Excalibur Solutions--Simple Excalibur System.pdf	-
AN 244: Using Run-From-Flash Mode with the Excalibur Bootloader.pdf	-
AN 265: Using Altera MAX Series as Microcontroller I/O Expanders.pdf	-
AN 267: Rebuilding the Excalibur Dynamic Reconfiguration with Linux Demonstration. .pdf	-
AN 278: Dynamic Reconfiguration of Excalibur Devices with Linux.pdf	-
AN 284: Implementing Interrupt Service Routines in Nios Systems.pdf	-
AN 286: Implementing LED Drivers in Altera MAX Series.pdf	-
AN 287: Using Excalibur DMA Controllers for Video Imaging.pdf	-
AN 298: Reconfiguring Excalibur Devices Under Processor Control.pdf	-
AN 307: Intel FPGA Design Flow for Xilinx Users	2018-03-20		Intel® Cyclone® 10 GX\|Intel® Arria® 10\|Intel® Stratix® 10
AN 307: Intel® FPGA Design Flow for Xilinx* Users.pdf	-
AN 308: Building Embedded Processor Systems with SOPC Builder and Excalibur Devices.pdf	-
AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices.pdf	-
AN 314 Digital Predistortion Reference Design.pdf	-
AN 315: Guidelines for Designing High-Speed FPGA PCBs.pdf	-
AN 317: Turbo FPGA Coprocessor Reference Design.pdf	-
AN 320: Using Intel® FPGA IP Evaluation Mode.pdf	-
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems.pdf	-
AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices.pdf	-
AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices.pdf	-
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices.pdf	-
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices.pdf	-
AN 332: Link Port Reference Design.pdf	-
AN 333: Developing Peripherals for SOPC Builder.pdf	-
AN 334: ADI Parallel Port SDRAM Controller Reference Design.pdf	-
AN 339 Serial Digital Interface Demonstration for Stratix II GX Devices.pdf	-
AN 340: Altera Software Licensing.pdf	-
AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices.pdf	-
AN 343: OpenCore Evaluation of AMPP Megafunctions.pdf	-
AN 344: ASI Demonstration.pdf	-
AN 346: Using the Nios II Configuration Controller Reference Designs.pdf	-
AN 348: Interfacing DDR SDRAM with Cyclone Devices.pdf	-
AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices.pdf	-
AN 351: Simulating Nios II Processor Designs.pdf	-
AN 352: FPGA Peripheral Expansion & FPGA Co-Processing Application Note.pdf	-
AN 353: SMT Board Assembly Process Recommendations.pdf	-
AN 353: SMT Board Assembly Process Recommendations.pdf	-
AN 355: Stratix II Device System Power Considerations.pdf	-
AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices.pdf	-
AN 361: Interfacing DDR & DDR2 SDRAM with Cyclone II Devices.pdf	-
AN 362: Stratix II Filtering Reference Design Lab.pdf	-
AN 363: FFT Co-Processor Reference Design.pdf	-
AN 364: Edge Detection Reference Design.pdf	-
AN 366: Understanding I/O Output Timing for Altera Devices.pdf	-
AN 367 Implementing PLL Reconfiguration in Stratix II Devices.pdf	-
AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software.pdf	-
AN 376: Cyclone II Filtering Lab.pdf	-
AN 379: Active Serial Interface Controller Reference Design.pdf	-
AN 382: Using Stratix GX Transceivers for CPRI.pdf	-
AN 384: Using Calibrated On-Chip Series Termination in Stratix II Devices.pdf	-
AN 385: Using Stratix GX Transceivers for PCI Express.pdf	-
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces .pdf	-
AN 393: Stratix II Professional Filtering Lab.pdf	-
AN 394: Using SOPC Builder & DSP Builder Tool Flow.pdf	-
AN 395: Stratix II Professional FFT Co-Processor Reference Design.pdf	-
AN 39: IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices.pdf	-
AN 414: The JRunner Software Driver: AN Embedded Solution for PLD JTAG Configuration..pdf	-
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming.pdf	-
AN 423: Configuring the MicroBlaster Passive Serial Software Driver.pdf	-
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming.pdf	-
AN 428: MAX II CPLD Design Guideline.pdf	-
AN 429: Remote Configuration Over Ethernet with the Nios II Processor.pdf	-
AN 431: PCI Express to External Memory Reference Design.pdf	-
AN 431: PCI Express to External Memory Reference Design.pdf	-
AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices.pdf	-
AN 433: Constraining and Analyzing Source-Synchronous Interfaces.pdf	-
AN 435: Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices.pdf	-
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices.pdf	-
AN 437: Power Optimization in Stratix III FPGAs.pdf	-
AN 443: External PHY Support in PCI Express Megacore Functions.pdf	-
AN 447: Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems.pdf	-
AN 448: Stratix III Power Management Design Guide.pdf	-
AN 450: Uplink Desubchannelization for WiMAX.pdf	-
AN 451: Downlink Subchannelization for WiMAX.pdf	-
AN 453: HardCopy II ASIC Fitting Techniques.pdf	-
AN 455: Understanding CIC Compensation Filters.pdf	-
AN 457: Integrating Uplink Desubchannelization & Ranging Modules for WiMAX.pdf	-
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices .pdf	-
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices .pdf	-
AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafuntion.pdf	-
AN 464: DFT/IDFT Reference Design	2018-05-30	Wireless\|Broadcast\|Consumer\|Wireline\|Automotive
AN 464: DFT/IDFT Reference Design.pdf	-
AN 466: Cyclone III Design Guidelines.pdf	-
AN 471: High-Performance FPGA PLL Analysis with TimeQuest.pdf	-
AN 471: High-Performance FPGA PLL Analysis with TimeQuest.pdf	-
AN 472: Stratix II GX SSN Design Guidelines.pdf	-
AN 474: Implementing Stratix III and Stratix IV Programmable I/O Delay Settings in the Quartus II Software.pdf	-
AN 475: Crest Factor Reduction for OFDMA Systems.pdf	-
AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices.pdf	-
AN 477: Designing RGMII Interface with FPGA and HardCopy Devices.pdf	-
AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software.pdf	-
AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices.pdf	-
AN 480: 1536-Point FFT for 3GPP Long Term Evolution.pdf	-
AN 482: High Definition (HD) Video Monitoring Reference Design (Milestone 2).pdf	-
AN 483: Triple Speed Ethernet Data Path Reference Design.pdf	-
AN 484: SMBus for GPIO Pin Expansion in MAX II CPLDs.pdf	-
AN 489: Using the UFM in MAX II Devices.pdf	-
AN 496: Using the Internal Oscillator IP Core.pdf	-
AN 504: DSP System Design in Stratix III Devices.pdf	-
AN 505: 3GPP LTE Turbo Reference Design.pdf	-
AN 506: QR Matrix Decomposition.pdf	-
AN 507: Implementing PLL Reconfiguration in Cyclone III Devices.pdf	-
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines.pdf	-
AN 509: Multiplexing SDIO Devices Using Altera MAX Series.pdf	-
AN 512: Using the Design Security Feature in Stratix III Devices.pdf	-
AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design.pdf	-
AN 514: Power Optimization in Stratix IV FPGAs.pdf	-
AN 519: Stratix IV Design Guidelines.pdf	-
AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design.pdf	-
AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families	2018-07-31	End Market	Intel® Cyclone® 10 GX\|Cyclone® IV\|Cyclone® III\|Stratix® V\|Intel® Stratix® 10\|Cyclone® V\|Intel® Arria® 10\|Intel® Cyclone® 10 LP\|Arria® V\|Stratix® IV\|Stratix® III\|Arria® II\|Intel® MAX® 10
AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families.pdf	-
AN 527: LCD Controller Replacement.pdf	-
AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing.pdf	-
AN 529: Via Optimization Techniques for High-Speed Channel Designs.pdf	-
AN 531: Reducing Power with Hardware Accelerators.pdf	-
AN 532: An SOPC Builder PCI Express Design with GUI Interface.pdf	-
AN 537: Implementing UNH-IOL Test Suite Compliance in Arria GX and Stratix II GX Gigabit Ethernet Designs.pdf	-
AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices	2018-05-07		Cyclone® V\|Arria® V\|Stratix® IV\|Stratix® V\|Stratix® III\|Arria® II
AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices.pdf	-
AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset.pdf	-
AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs.pdf	-
AN 549: Managing Designs with Multiple FPGAs.pdf	-
AN 553: Debugging Transceivers.pdf	-
AN 556: Using the Design Security Features in Intel FPGAs	2018-06-15		Intel® Cyclone® 10 GX\|Cyclone® V\|Intel® Arria® 10\|Arria® V\|Stratix® IV\|Stratix® V\|Arria® II
AN 556: Using the Design Security Features in Intel FPGAs.pdf	-
AN 558: Implementing Dynamic Reconfiguration in Arria II Devices.pdf	-
AN 561: Stratix II GX 10GbE Loopback Reference Design.pdf	-
AN 563: Design Guidelines for Arria II Devices.pdf	-
AN 567: Quartus II Separation Design Flow.pdf	-
AN 568: RapidIO Interoperability With TI 6488 DSP Reference Design.pdf	-
AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices.pdf	-
AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices.pdf	-
AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices.pdf	-
AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers.pdf	-
AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology.pdf	-
AN 577: Recommended Protocol Configurations for Stratix IV GX FPGAs.pdf	-
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode.pdf	-
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs.pdf	-
AN 584: Timing Closure Methodology for Advanced FPGA Designs.pdf	-
AN 586: Porting the Jam STAPL and Jam STAPL Byte-Code Player to an Embedded Sytem.pdf	-
AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Design.pdf	-
AN 589: Using the Design Security Feature in Cyclone III LS Devices.pdf	-
AN 592: Cyclone IV Design Guidelines.pdf	-
AN 593: Anti-tamper Protection for Cyclone III LS Devices.pdf	-
AN 596: Modeling and Design Considerations for 10 Gbps Connectors.pdf	-
AN 597: Getting Started Flow for Board Designs.pdf	-
AN 599: Arria II GX RapidIO Interoperability With TI 6488 DSP Reference Design.pdf	-
AN 603: Active Serial Remote System Upgrade Reference Design.pdf	-
AN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices.pdf	-
AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices.pdf	-
AN 610: Implementing CPRI and OBSAI Protocols in Altera Devices.pdf	-
AN 611: Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design.pdf	-
AN 612: Decision Feedback Equalization in Stratix IV Devices.pdf	-
AN 623: Resampling Filter Designs Using the DSP Builder Advanced Blockset.pdf	-
AN 628: Using the Agilent 3070 Tester for In-System Programming.pdf	-
AN 633: Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and GX Transceivers.pdf	-
AN 634: PHY IP Design Flow with Interlaken for Stratix V Devices.pdf	-
AN 635: Implementing SATA and SAS Protocols in Altera Devices.pdf	-
AN 636: Using Differential I/O Standards in MAX V Devices.pdf	-
AN 642: 2.5G Reed-Solomon II MegaCore Function Reference Design.pdf	-
AN 644: Migration Between Stratix V GX and Stratix V GT Devices.pdf	-
AN 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices.pdf	-
AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores.pdf	-
AN 664: Using the Stratix V Reconfiguration Controller to Perform Dynamic Reconfiguration.pdf	-
AN 670: Thermal Solutions to Address Height Variation in Stratix V Packages.pdf	-
AN 672: Transceiver Link Design Guidelines for High- Gbps Data Rate Transmission.pdf	-
AN 672: Transceiver Link Design Guidelines for High- Gbps Data Rate Transmission.pdf	-
AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission	2017-02-02		Stratix® V
AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs	2014-01-16		Stratix® V
AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs.pdf	-
AN 687: Implementing QPI Using the Transceiver Native PHY IP Core in Stratix V Devices.pdf	-
AN 689: High Speed Channel Design Using the SFF-8431 Protocol.pdf	-
AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices	2018-04-13		Intel® Cyclone® 10 GX\|Intel® Stratix® 10\|Intel® Arria® 10
AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 Devices.pdf	-
AN 696: Using the JESD204B MegaCore Function in Arria V Devices.pdf	-
AN 697: Implementing Audio IP in SDI II on Arria V Development Board.pdf	-
AN 699: Using the Altera Ethernet Design Toolkit.pdf	-
AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY.pdf	-
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller.pdf	-
AN 706: Routing HPS Peripheral Signals to the FPGA External Interface	2018-05-07	End Market	Cyclone® V\|Arria® V
AN 706: Routing HPS Peripheral Signals to the FPGA External Interface.pdf	-
AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report.pdf	-
AN 711: Power Reduction Features in Intel Arria 10 Devices	2018-07-12		Intel® Arria® 10
AN 711: Power Reduction Features in Intel® Arria® 10 Devices.pdf	-
AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report.pdf	-
AN 713: DC Coupling in Stratix V Devices.pdf	-
AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report.pdf	-
AN 723: Serial Digital Interface (SDI) II Implementation in Arria 10 Devices.pdf	-
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 and Intel Cyclone 10 GX Devices	2018-06-15		Intel® Cyclone® 10 GX\|Intel® Arria® 10
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices.pdf	-
AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor.pdf	-
AN 730: Nios II Processor Booting Methods in MAX 10 FPGA Devices.pdf	-
AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report.pdf	-
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines.pdf	-
AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ).pdf	-
AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices.pdf	-
AN 738: Intel® Arria® 10 Device Design Guidelines .pdf	-
AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor .pdf	-
AN 742: PMBus SmartVID Controller Reference Designs.pdf	-
AN 745: Design Guidelines for Intel FPGA DisplayPort Interface.pdf	-
AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices.pdf	-
AN 747: Implementing PHYLite in Intel® Arria® 10 Devices Design Examples.pdf	-
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report.pdf	-
AN 74: Evaluating Power for Altera Devices.pdf	-
AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report.pdf	-
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs	2018-06-15	Automotive	Cyclone® IV\|Cyclone® V\|Intel® Cyclone® 10 LP\|Intel® MAX® 10
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs.pdf	-
AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow).pdf	-
AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines.pdf	-
AN 761: Board Management Controller	2018-06-27		Intel® MAX® 10
AN 761: Board Management Controller.pdf	-
AN 766: Intel Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline	2018-08-14		Intel® Stratix® 10
AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline.pdf	-
AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices.pdf	-
AN 770: Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board.pdf	-
AN 773: Drive-On-Chip Reference Design for MAX® 10 Devices.pdf	-
AN 775: I/O Timing Information Generation Guidelines	2016-10-31		Intel® Arria® 10
AN 775: I/O Timing Information Generation Guidelines.pdf	-
AN 776: Intel® Arria® 10 UHD Video Reference Design .pdf	-
AN 778: Intel Stratix 10 Transceiver Usage	2018-07-13		Intel® Stratix® 10
AN 778: Intel® Stratix® 10 Transceiver Usage.pdf	-
AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report.pdf	-
AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices .pdf	-
AN 787: Intel Stratix 10 Thermal Modeling and Management	2018-08-20		Intel® Stratix® 10
AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design .pdf	-
AN 796: Cyclone V and Arria V SoC Device Design Guidelines	2018-06-18	Wireline	Cyclone® V\|Arria® V
AN 796: Cyclone V and Arria V SoC Device Design Guidelines .pdf	-
AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board.pdf	-
AN 798: Partial Reconfiguration with the Arria 10 HPS	2017-01-25		Intel® Arria® 10
AN 798: Partial Reconfiguration with the Arria 10 HPS.pdf	-
AN 799: Quick Intel Arria 10 Design Debugging Using Signal Probe and Rapid Recompile	2018-08-16		Intel® Arria® 10
AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel Arria 10 JESD204B RX IP Core	2018-02-09		Intel® Arria® 10
AN 807: Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL	2018-05-04	End Market	Intel® Arria® 10
AN 80: Selecting Sockets for Altera Devices.pdf	-
AN 812: Platform Designer System Design Tutorial	2018-04-02		All PLDs
AN 829: PCI Express Avalon -MM DMA Reference Design	2018-06-11	Broadcast\|Computer & Storage\|Industrial\|Medical\|Military	Cyclone Series\|Arria Series\|Stratix Series
AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices	2018-05-24		Intel® Stratix® 10
AN 834: Developing for the Intel HLS Compiler with an IDE	2017-12-04	End Market	Intel® Cyclone® 10 GX\|Cyclone® V\|Intel® Arria® 10\|Arria® V\|Stratix® V\|Intel® Stratix® 10\|Intel® MAX® 10
AN 835: PAM4 Signaling Fundamentals	2018-01-31		Intel® Stratix® 10
AN 83: Binary Numbering Systems.pdf	-
AN 841: Signal Tap Tutorial for Intel Stratix 10 Partial Reconfiguration Design	2018-05-07		Intel® Stratix® 10
AN 846: Intel Stratix 10 Forward Error Correction	2018-07-02		Intel® Stratix® 10
AN 847: Signal Tap Tutorial with Design Block Reuse for Intel Arria 10 FPGA Development Board	2018-05-07		Intel® Arria® 10
AN 848: Implementing Intel Cyclone 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design	2018-07-05		Intel® Cyclone® 10 GX
AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel Stratix 10 Devices	2018-06-12		Intel® Stratix® 10
AN 855: PCI Express High Performance Reference Design for Intel Cyclone 10 GX	2018-06-08		Intel® Cyclone® 10
AN 856: K-Mean Clustering with the Intel FPGA SDK for OpenCL	2018-06-12	End Market	Cyclone® IV\|Stratix® V\|Intel® Stratix® 10\|Intel® Cyclone® 10\|Cyclone® V\|Intel® Arria® 10\|Arria® V\|Stratix® IV\|Arria® II
AN 861: Intel Stratix 10 H-Tile PCI Express Link Hardware Validation	2018-06-29		Intel® Stratix® 10
AN 90: SameFrame Pin-Out Design for FineLine BGA Packages.pdf	-
AN 94: Understanding MAX 7000 Timing.pdf	-
AN-693: Remote Hardware Debugging over TCP/IP for Altera SoC.pdf	-
AN-705: Scalable 10G Ethernet MAC using 1G/10G PHY.pdf	-
AN-720: Simulating the ASMI Block in Your Design.pdf	-
AN-744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices.pdf	-
AN-757: 1G/2.5G Ethernet Design Examples.pdf	-
AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report.pdf	-
AN316 High-Speed Data Interface for Stratix Devices and Fujitsu MB86064 DACx.pdf	-
AN371: Automotive Graphics System Application Note.pdf	-
AN372: Avalon TFT Controller Application Note.pdf	-
AN373: Avalon Video Input Module Application Note.pdf	-
AN375: Cyclone II FFT Co-Processor Reference Design.pdf	-
AN449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices.pdf	-
AN465: Implementing OCT Calibration in Stratix III Devices.pdf	-
AN469: Stratix III Design Guidelines.pdf	-
AN487: SPI to I2S Using MAX II CPLDs.pdf	-
AN497: LCD Controller Using MAX II CPLDs.pdf	-
AN499: Mobile SDRAM Interface Using MAX II CPLDs.pdf	-
AN503: Implementing OFDM Modulation for Wireless Communications.pdf	-
AN511: Polyphase Modulation Using FPGA for High-Speed Applications.pdf	-
AN530: Optimizing Impedance discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs.pdf	-
AN536: Design Guidelines for Preparing HardCopy II ASICs.pdf	-
AN540: Nios II MPU Usage.pdf	-
AN541: SerialLite II Hardware Debugging Guide.pdf	-
AN543: Debugging Nios II Software Using the Lauterbach Debugger.pdf	-
AN548: Nios II Compact Configuration System for Cyclone III.pdf	-
AN557: Stratix III to Stratix IV E Cross-Family Migration Guidelines.pdf	-
AN569: SDI Flywheel Video Decoder Reference Design.pdf	-
AN585: Simulation Debugging Using Triple Speed Ethernet Testbench.pdf	-
AN587: DPRIO and Multiple Instances SDI Application.pdf	-
AN600: Serial Digital Interface Demonstration for Stratix IV Devices.pdf	-
AN601: Serial Digital Interface Reference Design for Arria II GX Devices.pdf	-
AN604: High Definition Video Reference Design (UDX3).pdf	-
AN617: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices.pdf	-
AN624: Debugging with System Console over TCP/IP.pdf	-
AN629: Understanding Timing in Altera CPLDs.pdf	-
AN639: Inferring Stratix V DSP Blocks for FIR Filtering Applications.pdf	-
AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design.pdf	-
AN656: Combining Multiple Configuration Schemes.pdf	-
AN657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices.pdf	-
AN668: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices.pdf	-
AN708.pdf	-
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP).pdf	-
AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design.pdf	-
AN795: Implementing 10G Ethernet Subsystem Using Low Latency 10G MAC IP in Arria 10 Devices.pdf	-
AN804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel Stratix 10 JESD204B RX IP Core	2018-03-09		Intel® Stratix® 10
AN822: Intel FPGA Configuration Device Migration Guideline	2018-03-30	Wireless\|Industrial\|Wireline\|Military\|Broadcast\|Test & Measurement\|Computer & Storage\|Consumer\|Automotive\|Medical	Intel® Cyclone® 10 GX\|Stratix® V\|Intel® Stratix® 10\|Cyclone® V\|Intel® Arria® 10\|Intel® Cyclone® 10 LP\|Arria® V
Accelerating DUC & DDC System Designs for WiMAX.pdf	-
Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum.pdf	-
Accelerating Nios II Networking Appllications.pdf	-
Acceleration Stack for Intel Xeon CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual	2018-08-06	Wireline	Intel® Arria® 10
Accurate Output Ripple Measurement Methods for Enpirion Power Products.pdf	-
Adding New Design Components to the PROFINET IP.pdf	-
Altera 1588 System Solution.pdf	-
Altera Design Flow for Lattice Semiconductor Users.pdf	-
Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report.pdf	-
Altera MAX Series as Voltage Level Shifters.pdf	-
An 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs.pdf	-
An 554: How to Read HardCopy PrimeTime Timing Reports.pdf	-
An OFDM FFT Kernel for Wireless Applications.pdf	-
Analyzing Timing of Memory IP, External Memory Interface Handbook, Volume 2, Chapter 11.pdf	-
Arria 10 Device Design Guidelines.pdf	-
Arria 10 SoC Device Design Guidelines.pdf	-
Arria V Timing Optimization Guidelines.pdf	-
Arria V and Cyclone V Design Guidelines.pdf	-
Automotive Audio Reference Design Application Note.pdf	-
Avalon Blocks in DSP Builder.pdf	-
Battery Management System Reference Design.pdf	-
Best Design Practices for HardCopy Devices, AN 658.pdf	-
Black Boxing in DSP Builder.pdf	-
Board Design Guidelines for Intel Programmable Device Packages.pdf	-
Board Design Layout Guidelines; External Memory Interface Handbook.pdf	-
Board Design Layout Guidelines; External Memory Interface Handbook.pdf	-
Board Design Layout Guidelines; External Memory Interface Handbook.pdf	-
CF+ Interface Using Altera MAX Series.pdf	-
CORDIC Reference Design Application Note.pdf	-
Channel Estimation and Equalization for WiMAX.pdf	-
Clock Reconstruction with Low-cost External DCXO.pdf	-
Compiling and Customizing an Arria 10 Custom Platform for OpenCL.pdf	-
Connecting Altera 3.3-V PCI devices to a 5-V PCI Bus.pdf	-
Constellation Mapper and Demapper for WiMAX Application Note.pdf	-
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms.pdf	-
Creating an FPGA Power Tree.pdf	-
Creating an FPGA Power Tree.pdf	-
Creating an FPGA Power Tree.pdf	-
Crest Factor Reduction Application Note.pdf	-
Crosspoint Switch Matrices in Altera MAX Series.pdf	-
Cyclone II DDR2 SDRAM Demonstration Application Note.pdf	-
Cyclone V SoC Power Optimization.pdf	-
DSP GizMo.pdf	-
Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer Application Note.pdf	-
Description.pdf	-

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All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request.