AN 932: Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices
2020-12-21
Cyclone® V|Intel® Arria® 10|Intel® Agilex™ Series|Intel® Stratix® 10
AN 769: Intel FPGA Remote Temperature Sensing Diode Implementation Guide
2021-02-09
Intel® Stratix® 10
AN 773: Drive-On-Chip Design Example for Intel MAX 10 Devices
2021-02-15
Industrial|Automotive
Intel® MAX® 10
AN 797: Partially Reconfiguring a Design: on Intel Arria 10 GX FPGA Development Board
2020-12-11
Intel® Arria® 10
AN 802: Intel Stratix 10 SoC Device Design Guidelines
2020-12-14
Intel® Stratix® 10
AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel Arria 10 GX FPGA Development Board
2021-02-04
Intel® Arria® 10
AN 813: Hierarchical Partial Reconfiguration over PCI Express Reference Design: for Intel Arria 10 Devices
2021-01-20
Intel® Arria® 10
AN 825: Partially Reconfiguring a Design: on Intel Stratix 10 GX FPGA Development Board
2020-12-07
Intel® Stratix® 10
AN 826: Hierarchical Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board
2021-01-05
Intel® Stratix® 10
AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel Arria 10 FPGA Development Board
2020-12-21
Intel® Arria® 10
AN 866: Mitigating and Debugging Single Event Upsets in Intel Quartus Prime Standard Edition
2021-01-05
Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® V
AN 881: PCI Express Gen3 x16 Avalon Memory Mapped (Avalon-MM) DMA with External and HBM2 Memories Reference Design
2021-03-03
Computer & Storage|Industrial|Consumer
Intel® Stratix® 10
AN 886: Intel Agilex SoC Device Design Guidelines
2021-01-22
Intel® Agilex™ Series
AN 903: Accelerating Timing Closure: in Intel Quartus Prime Pro Edition
2021-02-25
End Market
Intel® Cyclone® 10 GX|Intel® Agilex™|Intel® Arria® 10|Intel® Stratix® 10
AN 910: Intel Agilex Power Distribution Network Design Guidelines
2020-12-18
Intel® Agilex™ F-Series
AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex Devices
2020-12-21
Intel® Agilex™ Series
AN 917: Reset Design Techniques for Intel Hyperflex Architecture FPGAs
2021-01-05
Intel® Agilex™ Series|Intel® Stratix® 10
Intel Stratix 10 Device Design Guidelines
2020-12-14
Intel® Stratix® 10
10-Gbps Ethernet Interoperability Hardware Demonstration Reference Design, Application Note.pdf
-
10-Gbps Ethernet Reference Design User Guide.pdf
-
24K FFT for 3GPP LTE RACH Detection.pdf
-
4K Format Conversion Reference Design.pdf
-
AES3/EBU Reference Design Application Note.pdf
-
ALTMEMPHY Design Tutorials; External Memory Interface Handbook.pdf
-
ALTMEMPHY Design Tutorials; External Memory Interface Handbook.pdf
-
AN 095: In-System Progammability in MAX Devices.pdf
-
AN 100: In-System Programmability Guidelines
2014-09-22
AN 109: Using the HP 3070 Tester for In-System Programming.pdf
-
AN 113: Plastic Package Reliability & Testing.pdf
-
AN 114: Board Design Guidelines for Intel Programmable Device Packages
2019-12-31
AN 119: Implementing High-Speed Search Applications with Altera CAM.pdf
-
AN 132: Implementing Multiprotocol Label Switching with Altera PLDs.pdf
-
AN 174: Excalibur Solutions - Hello_world.c version 2.0 October 2001.pdf
-
AN 185: Thermal Management Using Heat Sinks.pdf
-
AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs.pdf
-
AN 224: High-Speed Board Layout Guidelines.pdf
-
AN 236 (Using Source-Synchronous Signaling with DPA in Stratix GX Devices).pdf
-
AN 240:Simulating Excalibur Systems.pdf
-
AN 242: Excalibur Solutions--Simple Excalibur System.pdf
-
AN 244: Using Run-From-Flash Mode with the Excalibur Bootloader.pdf
-
AN 265: Using Altera MAX Series as Microcontroller I/O Expanders
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 267: Rebuilding the Excalibur Dynamic Reconfiguration with Linux Demonstration..pdf
-
AN 278: Dynamic Reconfiguration of Excalibur Devices with Linux.pdf
-
AN 286: Implementing LED Drivers in Altera MAX Series
2017-12-13
MAX® V|MAX® II|Intel® MAX® 10
AN 287: Using Excalibur DMA Controllers for Video Imaging.pdf
-
AN 294: Crosspoint Switch Matrices in Altera MAX Series
2014-09-22
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 298: Reconfiguring Excalibur Devices Under Processor Control.pdf
-
AN 307: Intel FPGA Design Flow for Xilinx Users
2020-08-24
Intel® Cyclone® 10 GX|Intel® Stratix® 10|Intel® Arria® 10
AN 308: Building Embedded Processor Systems with SOPC Builder and Excalibur Devices.pdf
-
AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices.pdf
-
AN 314 Digital Predistortion Reference Design.pdf
-
AN 315: Guidelines for Designing High-Speed FPGA PCBs.pdf
-
AN 320: Using Intel FPGA IP Evaluation Mode
2018-10-22
All PLDs
AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices.pdf
-
AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices.pdf
-
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices.pdf
-
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices.pdf
-
AN 332: Link Port Reference Design.pdf
-
AN 333: Developing Peripherals for SOPC Builder.pdf
-
AN 334: ADI Parallel Port SDRAM Controller Reference Design.pdf
-
AN 339 Serial Digital Interface Demonstration for Stratix II GX Devices.pdf
-
AN 340: Altera Software Licensing.pdf
-
AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices.pdf
-
AN 343: OpenCore Evaluation of AMPP Megafunctions.pdf
-
AN 344: ASI Demonstration.pdf
-
AN 346: Using the Nios II Configuration Controller Reference Designs.pdf
-
AN 348: Interfacing DDR SDRAM with Cyclone Devices.pdf
-
AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices.pdf
-
AN 351: Simulating Nios II Processor Designs.pdf
-
AN 352: FPGA Peripheral Expansion & FPGA Co-Processing Application Note.pdf
-
AN 353: SMT Board Assembly Process Recommendations.pdf
-
AN 353: SMT Board Assembly Process Recommendations.pdf
-
AN 355: Stratix II Device System Power Considerations.pdf
-
AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices.pdf
-
AN 361: Interfacing DDR & DDR2 SDRAM with Cyclone II Devices.pdf
-
AN 362: Stratix II Filtering Reference Design Lab.pdf
-
AN 363: FFT Co-Processor Reference Design.pdf
-
AN 364: Edge Detection Reference Design.pdf
-
AN 366: Understanding I/O Output Timing for Altera Devices.pdf
-
AN 367 Implementing PLL Reconfiguration in Stratix II Devices.pdf
-
AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software
2019-02-18
Intel® Cyclone® 10|Intel® Arria® 10
AN 376: Cyclone II Filtering Lab.pdf
-
AN 379: Active Serial Interface Controller Reference Design.pdf
-
AN 382: Using Stratix GX Transceivers for CPRI.pdf
-
AN 384: Using Calibrated On-Chip Series Termination in Stratix II Devices.pdf
-
AN 385: Using Stratix GX Transceivers for PCI Express.pdf
-
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces.pdf
-
AN 393: Stratix II Professional Filtering Lab.pdf
-
AN 394: Using SOPC Builder & DSP Builder Tool Flow.pdf
-
AN 395: Stratix II Professional FFT Co-Processor Reference Design.pdf
-
AN 39: IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices.pdf
-
AN 414: The JRunner Software Driver: AN Embedded Solution for PLD JTAG Configuration..pdf
-
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming.pdf
-
AN 423: Configuring the MicroBlaster Passive Serial Software Driver.pdf
-
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
2014-09-22
Cyclone® IV|Intel® Cyclone®|Arria Series|Stratix® II|MAX Series|Cyclone® III|MAX® V|Stratix® V|Intel® Stratix® 10|Cyclone® V|MAX® II|Intel® Arria® 10|Arria® V|Stratix® IV|Stratix® III|Arria® II|Intel® MAX® 10|Cyclone® II|Stratix Series
AN 428: MAX II CPLD Design Guideline.pdf
-
AN 429: Remote Configuration Over Ethernet with the Nios II Processor.pdf
-
AN 431: PCI Express to External Memory Reference Design.pdf
-
AN 431: PCI Express to External Memory Reference Design.pdf
-
AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices.pdf
-
AN 433: Constraining and Analyzing Source-Synchronous Interfaces.pdf
-
AN 435: Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices.pdf
-
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices.pdf
-
AN 437: Power Optimization in Stratix III FPGAs.pdf
-
AN 443: External PHY Support in PCI Express Megacore Functions.pdf
-
AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
2017-11-06
Wireline
Cyclone® IV|Intel® Cyclone® 10 LP|Cyclone® III|Intel® MAX® 10
AN 448: Stratix III Power Management Design Guide.pdf
-
AN 450: Uplink Desubchannelization for WiMAX.pdf
-
AN 451: Downlink Subchannelization for WiMAX.pdf
-
AN 453: HardCopy II ASIC Fitting Techniques.pdf
-
AN 455: Understanding CIC Compensation Filters.pdf
-
AN 457: Integrating Uplink Desubchannelization & Ranging Modules for WiMAX.pdf
-
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices.pdf
-
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices.pdf
-
AN 462, Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafuntion.pdf
-
AN 464: DFT/IDFT Reference Design
2018-05-30
Wireless|Broadcast|Consumer|Wireline|Automotive
AN 466: Cyclone III Design Guidelines.pdf
-
AN 471: High-Performance FPGA PLL Analysis with TimeQuest.pdf
-
AN 471: High-Performance FPGA PLL Analysis with TimeQuest.pdf
-
AN 472: Stratix II GX SSN Design Guidelines.pdf
-
AN 474: Implementing Stratix III and Stratix IV Programmable I/O Delay Settings in the Quartus II Software.pdf
-
AN 475: Crest Factor Reduction for OFDMA Systems.pdf
-
AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices.pdf
-
AN 477: Designing RGMII Interface with FPGA and HardCopy Devices.pdf
-
AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software.pdf
-
AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices.pdf
-
AN 480: 1536-Point FFT for 3GPP Long Term Evolution.pdf
-
AN 482: High Definition (HD) Video Monitoring Reference Design (Milestone 2).pdf
-
AN 483: Triple Speed Ethernet Data Path Reference Design.pdf
-
AN 484: SMBus for GPIO Pin Expansion in MAX II CPLDs.pdf
-
AN 485: Serial Peripheral Interface Master in Altera MAX Series
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 486: SPI to I2C Using Altera MAX Series
2014-09-22
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 488: Stepper Motor Controller Using Altera MAX Series
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 489: Using the UFM in MAX II Devices.pdf
-
AN 490: Altera MAX Series as Voltage Level Shifters
2014-09-22
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 491: Power Sequence Auto Start Using Altera MAX Series
2014-09-22
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 492: CF+ Interface Using Altera MAX Series
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 493: I2C Battery Gauge Interface Using Altera MAX Series
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series
2014-09-22
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 495: IDE/ATA Controller Using Altera MAX Series
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 496: Using the Internal Oscillator IP Core
2017-11-06
Intel® Cyclone® 10 GX|Cyclone® IV|Cyclone® III|MAX® V|Stratix® V|Intel® Stratix® 10|Cyclone® V|MAX® II|Intel® Arria® 10|Intel® Cyclone® 10 LP|Arria® V|Arria® II|Intel® MAX® 10
AN 498: LED Blink Using Power Sequencing in Altera MAX Series
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 500: NAND Flash Memory Interface with Altera MAX Series
2014-09-22
MAX® II|MAX® V|Intel® MAX® 10
AN 501: Pulse Width Modulation Using Altera MAX Series
2014-09-22
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 502: Implementing SMBus Controller in Altera MAX Series
-
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 504: DSP System Design in Stratix III Devices.pdf
-
AN 505: 3GPP LTE Turbo Reference Design.pdf
-
AN 506: QR Matrix Decomposition.pdf
-
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines.pdf
-
AN 509: Multiplexing SDIO Devices Using Altera MAX Series
2014-09-22
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
AN 512: Using the Design Security Feature in Stratix III Devices.pdf
-
AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design.pdf
-
AN 514: Power Optimization in Stratix IV FPGAs.pdf
-
AN 519: Stratix IV Design Guidelines.pdf
-
AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design.pdf
-
AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families
2018-07-31
End Market
Intel® Cyclone® 10 GX|Cyclone® IV|Cyclone® III|Stratix® V|Intel® Stratix® 10|Cyclone® V|Intel® Arria® 10|Intel® Cyclone® 10 LP|Arria® V|Stratix® IV|Stratix® III|Arria® II|Intel® MAX® 10
AN 527: LCD Controller Replacement.pdf
-
AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing.pdf
-
AN 529: Via Optimization Techniques for High-Speed Channel Designs.pdf
-
AN 531: Reducing Power with Hardware Accelerators.pdf
-
AN 532: An SOPC Builder PCI Express Design with GUI Interface.pdf
-
AN 537: Implementing UNH-IOL Test Suite Compliance in Arria GX and Stratix II GX Gigabit Ethernet Designs.pdf
-
AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices
2019-08-09
Cyclone® V|Arria® V|Cyclone® III|Stratix® IV|Stratix® V|Stratix® III|Arria® II
AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset.pdf
-
AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs.pdf
-
AN 549: Managing Designs with Multiple FPGAs.pdf
-
AN 553: Debugging Transceivers.pdf
-
AN 556: Using the Design Security Features in Intel FPGAs
2019-11-12
Intel® Cyclone® 10 GX|Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® IV|Stratix® V|Arria® II
AN 558: Implementing Dynamic Reconfiguration in Arria II Devices.pdf
-
AN 561: Stratix II GX 10GbE Loopback Reference Design.pdf
-
AN 563: Design Guidelines for Arria II Devices.pdf
-
AN 567: Quartus II Separation Design Flow.pdf
-
AN 568: RapidIO Interoperability With TI 6488 DSP Reference Design.pdf
-
AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices.pdf
-
AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices.pdf
-
AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices.pdf
-
AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers.pdf
-
AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology.pdf
-
AN 577: Recommended Protocol Configurations for Stratix IV GX FPGAs.pdf
-
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode.pdf
-
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs.pdf
-
AN 584: Timing Closure Methodology for Advanced FPGA Designs.pdf
-
AN 586: Porting the Jam STAPL and Jam STAPL Byte-Code Player to an Embedded Sytem.pdf
-
AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Design.pdf
-
AN 589: Using the Design Security Feature in Cyclone III LS Devices.pdf
-
AN 592: Cyclone IV Design Guidelines.pdf
-
AN 593: Anti-tamper Protection for Cyclone III LS Devices.pdf
-
AN 596: Modeling and Design Considerations for 10 Gbps Connectors.pdf
-
AN 597: Getting Started Flow for Board Designs.pdf
-
AN 599: Arria II GX RapidIO Interoperability With TI 6488 DSP Reference Design.pdf
-
AN 603: Active Serial Remote System Upgrade Reference Design.pdf
-
AN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices.pdf
-
AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices.pdf
-
AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices.pdf
-
AN 611: Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design.pdf
-
AN 612: Decision Feedback Equalization in Stratix IV Devices.pdf
-
AN 623: Resampling Filter Designs Using the DSP Builder Advanced Blockset.pdf
-
AN 628: Using the Agilent 3070 Tester for In-System Programming.pdf
-
AN 630: Real-Time ISP and ISP Clamp for Intel MAX Series Devices
2020-04-13
MAX® II|MAX® V|Intel® MAX® 10
AN 633: Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and GX Transceivers.pdf
-
AN 634: PHY IP Design Flow with Interlaken for Stratix V Devices.pdf
-
AN 635: Implementing SATA and SAS Protocols in Altera Devices.pdf
-
AN 636: Using Differential I/O Standards in MAX V Devices.pdf
-
AN 642: 2.5G Reed-Solomon II MegaCore Function Reference Design.pdf
-
AN 644: Migration Between Stratix V GX and Stratix V GT Devices.pdf
-
AN 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices.pdf
-
AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
2019-10-14
Cyclone® V|Arria® V|Stratix® V
AN 664: Using the Stratix V Reconfiguration Controller to Perform Dynamic Reconfiguration.pdf
-
AN 669: Drive-On-Chip Reference Design
2020-11-05
Automotive
Cyclone Series|Intel® MAX® 10
AN 670: Thermal Solutions to Address Height Variation in Stratix V Packages.pdf
-
AN 672: Transceiver Link Design Guidelines for High- Gbps Data Rate Transmission.pdf
-
AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
2020-01-29
Stratix® V
AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs
2014-01-16
Stratix® V
AN 687: Implementing QPI Using the Transceiver Native PHY IP Core in Stratix V Devices
2015-12-17
Stratix® V
AN 689: High Speed Channel Design Using the SFF-8431 Protocol.pdf
-
AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, Intel Stratix 10, and Intel Agilex Devices
2019-10-11
Intel® Cyclone® 10 GX|Intel® Agilex™ F-Series|Intel® Arria® 10|Intel® Stratix® 10
AN 696: Using the JESD204B MegaCore Function in Arria V Devices
2015-05-11
Wireline
Arria® V
AN 697: Implementing Audio IP in SDI II on Arria V Development Board.pdf
-
AN 699: Using the Altera Ethernet Design Toolkit
2016-05-13
Intel® Arria® 10
AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
2017-11-06
Intel® Arria® 10
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
2017-09-22
Test & Measurement|Industrial|Consumer|Medical
Cyclone Series|Arria Series
AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
2018-09-01
Industrial|Automotive
Cyclone® V|Intel® Arria® 10|Intel® MAX® 10
AN 706: Routing HPS Peripheral Signals to the FPGA External Interface
2018-05-07
End Market
Cyclone® V|Arria® V
AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report
2015-05-11
Stratix® V
AN 711: Power Reduction Features in Intel Arria 10 Devices
2020-03-18
Intel® Arria® 10
AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report
2016-06-13
Stratix® V
AN 713: DC Coupling in Stratix V Devices
2014-08-20
Stratix® V
AN 717: Nios II Gen2 Hardware Development Tutorial
2014-09-22
AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report
2014-09-22
Wireline
Stratix® V
AN 71: Guidelines for Handling J-Lead, QFP, BGA, FBGA, and Lidless FBGA Devices
2019-03-29
AN 720: Simulating the ASMI Block in Your Design
2020-07-29
Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® V
AN 721: Creating an FPGA Power Tree
2019-06-30
Stratix® V|Intel® Arria® 10
AN 723: Serial Digital Interface (SDI) II Implementation in Arria 10 Devices.pdf
-
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 and Intel Cyclone 10 GX Devices
2019-04-03
Intel® Cyclone® 10 GX|Intel® Arria® 10
AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor
2015-05-04
Wireline
Intel® Arria® 10
AN 730: Nios II Processor Booting Methods in MAX 10 FPGA Devices
2017-02-21
Intel® MAX® 10
AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report
2015-02-09
Stratix® V
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
2015-05-04
Cyclone® IV|Stratix® II|Cyclone® III|Stratix® V|Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® IV|Stratix® III|Arria® II|Cyclone® II
AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ)
2016-05-20
Wireless|Wireline|Military|Test & Measurement|Consumer|Medical
Intel® Cyclone®|Stratix® V|Cyclone® V|Intel® Arria® 10|Arria® V|Arria®
AN 737: SEU Detection and Recovery in Intel Arria 10 Devices
2020-04-13
Test & Measurement
Intel® Arria® 10
AN 738: Intel Arria 10 Device Design Guidelines
2017-06-30
Intel® Arria® 10
AN 738: Intel® Arria® 10 Device Design Guidelines.pdf
-
AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor
2017-02-21
Intel® MAX® 10
AN 742: PMBus SmartVID Controller Reference Designs
2017-05-08
Intel® Arria® 10
AN 745: Design Guidelines for DisplayPort Intel FPGA IP Interface
2020-04-13
Broadcast
Intel® Cyclone® 10 GX|Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® V|Intel® Stratix® 10
AN 746: SDI II Triple-Rate Reference Designs for Intel Arria 10 Devices
2019-12-31
Broadcast
Intel® Arria® 10
AN 747: Implementing PHYLite in Intel Arria 10 Devices Design Examples
2017-05-08
Intel® Arria® 10
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
2015-12-18
Intel® Arria® 10
AN 74: Evaluating Power for Altera Devices.pdf
-
AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report
2015-11-02
Intel® Arria® 10
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs
2019-04-03
Automotive
Cyclone® IV|Cyclone® V|Intel® Cyclone® 10 LP|Intel® MAX® 10
AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
2015-12-30
Arria® V
AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
2017-05-08
Intel® Arria® 10
AN 757: 1G/2.5G Ethernet Design Examples
2018-11-12
End Market
All PLDs
AN 761: Board Management Controller
2018-06-27
Intel® MAX® 10
AN 763: Intel Arria 10 SoC Device Design Guidelines
2020-08-14
Intel® Arria® 10
AN 766: Intel Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline
2019-03-12
Intel® Stratix® 10
AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices
2017-05-08
Broadcast
Intel® Arria® 10
AN 770: Partially Reconfiguring a Design on Intel Arria 10 SoC Development Board
2017-11-06
Intel® Arria® 10
AN 775: Generating Initial I/O Timing Data: for Intel FPGAs
2019-12-08
Intel® Arria® 10|Intel® Agilex™ Series|Intel® Stratix® 10
AN 776: Intel Arria 10 UHD Video Reference Design
2018-01-11
Broadcast|Medical|Military
Intel® Arria® 10
AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores
2018-01-12
Intel® Arria® 10
AN 778: Intel Stratix 10 L-Tile/H-Tile Transceiver Usage
2020-04-21
Intel® Stratix® 10
AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report
2017-12-18
Intel® Arria® 10
AN 784: Partial Reconfiguration over PCI Express Reference Design for Intel Arria 10 Devices
2018-09-24
Intel® Arria® 10
AN 787: Intel Stratix 10 Thermal Modeling and Management
2018-08-20
Intel® Stratix® 10
AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
2017-12-18
Intel® Arria® 10
AN 793: Intel Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design
2017-06-13
Broadcast
Intel® Arria® 10
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel FPGA IP in Intel Arria 10 Devices
2020-10-28
Intel® Arria® 10
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
2020-07-27
Wireline
Cyclone® V|Arria® V
AN 798: Partial Reconfiguration with the Arria 10 HPS
2017-01-25
Intel® Arria® 10
AN 799: Quick Intel Arria 10 Design Debugging Using Signal Probe and Rapid Recompile
2018-08-16
Intel® Arria® 10
AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel Arria 10 JESD204B RX IP Core
2020-02-06
Intel® Arria® 10
AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel Stratix 10 JESD204B RX IP Core
2020-01-16
Intel® Stratix® 10
AN 805: Hierarchical Partial Reconfiguration of a Design on Intel Arria 10 SoC Development Board
2017-11-06
Intel® Arria® 10
AN 807: Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL
2020-02-14
End Market
Intel® Arria® 10
AN 808: Migration Guidelines from Intel Arria 10 to Intel Stratix 10 for 10G Ethernet Subsystem
2019-11-20
Intel® Stratix® 10|Intel® Arria® 10
AN 809: SerialLite III IP Core Feature and Interface Differences between Stratix 10, Arria 10, and Stratix V
2017-06-19
Intel® Arria® 10|Stratix® V|Intel® Stratix® 10
AN 80: Selecting Sockets for Altera Devices.pdf
-
AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
2017-12-18
Intel® Arria® 10
AN 812: Platform Designer System Design Tutorial
2018-04-02
All PLDs
AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design
2018-01-30
Wireless|Broadcast|Test & Measurement|Industrial|Consumer|Wireline|Medical|Military
Intel® Arria® 10
AN 817: Static Update Partial Reconfiguration Tutorial: for Intel Arria 10 GX FPGA Development Board
2019-07-15
Broadcast|Computer & Storage|Wireline|Automotive
Intel® Arria® 10
AN 818: Static Update Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board
2019-07-15
Broadcast|Computer & Storage|Wireline|Automotive
Intel® Stratix® 10
AN 819: Partial Reconfiguration over PCI Express Reference Design for Intel Stratix 10 Devices
2018-09-24
Intel® Stratix® 10
AN 820: Hierarchical Partial Reconfiguration over PCI Express Reference Design for Intel Stratix 10 Devices
2018-09-24
Intel® Stratix® 10
AN 821: Interface Planning for Intel Stratix 10 FPGAs
2017-12-15
Intel® Stratix® 10
AN 822: Intel FPGA Configuration Device Migration Guideline
2020-04-29
Wireless|Industrial|Wireline|Military|Broadcast|Test & Measurement|Computer & Storage|Consumer|Automotive|Medical
Intel® Cyclone® 10 GX|Stratix® V|Intel® Stratix® 10|Cyclone® V|Intel® Arria® 10|Intel® Cyclone® 10 LP|Arria® V
AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices
2017-12-18
Intel® Stratix® 10
AN 824: Intel FPGA SDK for OpenCL Board Support Package Floorplan Optimization Guide
2017-08-08
End Market
Intel® Arria® 10
AN 827: Unified Tool for Generating Programming Files
2018-10-29
AN 829: PCI Express Avalon -MM DMA Reference Design
2018-06-11
Broadcast|Computer & Storage|Industrial|Medical|Military
Cyclone Series|Arria Series|Stratix Series
AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
2020-10-14
Intel® Stratix® 10
AN 831: Intel FPGA SDK for OpenCL Host Pipelined Multithread
2017-11-20
All PLDs
AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices
2018-05-24
Intel® Stratix® 10
AN 833: Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
2017-12-19
Intel® Stratix® 10
AN 834: Using the Intel HLS Compiler Pro Edition with an IDE
2020-05-29
End Market
Intel® Cyclone® 10 GX|Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® V|Intel® Stratix® 10|Intel® MAX® 10
AN 835: PAM4 Signaling Fundamentals
2019-03-12
Intel® Stratix® 10
AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface
2017-12-18
Wireless|Industrial|Wireline|Military|Broadcast|Test & Measurement|Computer & Storage|Consumer|Automotive|Medical
Intel® Stratix® 10
AN 837: Design Guidelines for HDMI Intel FPGA IP
2019-01-28
Broadcast
Intel® Cyclone® 10 GX|Intel® Arria® 10|Arria® V|Stratix® V|Intel® Stratix® 10
AN 838: Interoperability between Intel Arria 10 NBASE-T Ethernet Solution with Aquantia* Ethernet PHY Reference Design
2018-01-12
Intel® Arria® 10
AN 839: Design Block Reuse Tutorial: for Intel Arria 10 FPGA Development Board
2019-07-26
Wireless|Computer & Storage|Consumer|Wireline
Intel® Arria® 10
AN 83: Binary Numbering Systems.pdf
-
AN 841: Signal Tap Tutorial for Intel Stratix 10 Partial Reconfiguration Design
2018-05-07
Intel® Stratix® 10
AN 845: Signal Tap Tutorial for Intel Arria 10 Partial Reconfiguration Design
2018-10-08
Intel® Arria® 10
AN 846: Intel Stratix 10 Forward Error Correction
2018-07-02
Intel® Stratix® 10
AN 848: Implementing Intel Cyclone 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design
2018-07-05
Intel® Cyclone® 10 GX
AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel Stratix 10 Devices
2018-06-12
Intel® Stratix® 10
AN 851: Incremental Block-Based Compilation Tutorial: for Intel Arria 10 FPGA Development Board
2019-07-15
Wireless|Computer & Storage|Consumer|Wireline
Intel® Arria® 10
AN 855: PCI Express High Performance Reference Design for Intel Cyclone 10 GX
2018-06-08
Intel® Cyclone® 10
AN 856: K-Mean Clustering with the Intel FPGA SDK for OpenCL
2018-06-12
End Market
Cyclone® IV|Stratix® V|Intel® Stratix® 10|Intel® Cyclone® 10|Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® IV|Arria® II
AN 860: Using Intel Arria 10 SoC FPGA Early I/O Release
2020-10-22
Intel® Arria® 10
AN 861: Intel Stratix 10 H-Tile PCI Express Link Hardware Validation
2018-06-29
Intel® Stratix® 10
AN 869: Partially Reconfiguring a Design: on Intel Cyclone 10 GX FPGA Development Board
2019-07-15
Intel® Cyclone® 10 GX
AN 870: Stencil Computation Reference Design
2018-10-10
End Market
Intel® Arria® 10
AN 871: Quick Guide for Intel Arria 10 and Intel Cyclone 10 GX Transceiver High-Speed Link Tuning
2018-09-26
Intel® Cyclone® 10 GX|Intel® Arria® 10
AN 872: Thermal and Power Guidelines: For Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA
2019-08-30
Wireless|Computer & Storage
Intel® Arria® 10
AN 875: Intel Stratix 10 E-Tile PCB Design Guidelines
2019-03-12
Intel® Stratix® 10
AN 882: Using ADI AD9217 with Intel Stratix 10 Devices
2020-08-17
End Market
Intel® Stratix® 10
AN 883: Intel Arria 10 DisplayPort TX-only Design
2019-02-20
Broadcast
Intel® Arria® 10
AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel Arria 10 Devices
2019-05-24
Intel® Arria® 10
AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel Stratix 10 Devices
2020-09-11
Intel® Stratix® 10
AN 889: 8K DisplayPort Video Format Conversion Design Example
2019-05-30
Broadcast
Intel® Arria® 10
AN 890: JESD204B Intel FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix 10 L-Tile Devices
2019-05-28
Intel® Stratix® 10
AN 891: Using the Reset Release Intel FPGA IP
2019-09-30
Test & Measurement
Stratix Series
AN 893: Hierarchical Partial Reconfiguration Tutorial: for Intel Cyclone 10 GX FPGA Development Board
2019-07-15
Intel® Arria® 10
AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel Cyclone 10 GX FPGA Development Board
2019-11-11
Intel® Cyclone® 10 GX
AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
2019-09-30
Intel® MAX® 10
AN 899: Reducing Compile Time with Fast Preservation
2019-11-06
Wireless|Wireline|Computer & Storage|Consumer
Intel® Cyclone® 10 GX|Intel® Agilex™ Series|Intel® Stratix® 10|Intel® Arria® 10
AN 900: Intel Arria 10 DisplayPort 8K RX-only Design
2019-12-16
Broadcast
Intel® Arria® 10
AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex FPGA E-Tile JESD204C RX IP
2020-09-21
Intel® Agilex™
AN 904: Intel MAX 10 Hitless Update Implementation Guidelines
2020-02-24
End Market
Intel® MAX® 10
AN 905: JESD204B Intel FPGA IP and ADI AD9213 Interoperability Report for Intel Stratix 10 Devices
2019-12-16
Intel® Stratix® 10
AN 906: Intel Stratix 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines
2020-02-06
Intel® Stratix® 10
AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000
2020-09-10
Wireless
Intel® Arria® 10
AN 908: Enabling 4G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000
2020-01-30
Wireless
Intel® Arria® 10
AN 909: JESD204C Intel FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel Stratix 10 Devices
2020-06-09
Intel® Stratix® 10
AN 90: SameFrame Pin-Out Design for FineLine BGA Packages.pdf
-
AN 915: JESD204B Intel FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix 10 E-Tile Devices
2020-06-01
Intel® Stratix® 10
AN 916: JESD204C Intel FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel Stratix 10 E-Tile Devices
2020-06-22
Intel® Stratix® 10
AN 918: Using the Intel HLS Compiler Standard Edition with an IDE
2020-05-29
End Market
Intel® Cyclone® 10 GX|Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® V|Intel® Stratix® 10|Intel® MAX® 10
AN 919: Improving Quality of Results with Design Assistant
2020-09-30
End Market
AN 921: Device Migration Guidelines for Intel Stratix 10 HF35 Package
2020-09-11
Intel® Stratix® 10
AN 922: Using the ECO Compilation Flow
2020-09-28
Intel® Agilex™ Series|Intel® Stratix® 10
AN 923: Routing Intel Stratix 10 HPS Peripherals to FPGA Fabric
2020-10-12
Intel® Stratix® 10
AN 927: JESD204C Intel FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Stratix 10 E-Tile Devices
2020-09-28
Intel® Stratix® 10
AN 933: Updating Intel Stratix 10 FPGA Firmware
2020-11-18
Intel® Stratix® 10
AN 94: Understanding MAX 7000 Timing.pdf
-
AN Turbo FPGA Coprocessor Reference Design.pdf
-
AN-705: Scalable 10G Ethernet MAC using 1G/10G PHY
2016-05-13
Stratix® V
AN-731: Simultaneous Switching Noise Guidelines for Intel Cyclone 10 LP, Cyclone IV, and Cyclone III Devices
2017-11-06
Cyclone® IV|Intel® Cyclone® 10 LP|Cyclone® III
AN-744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices
2016-04-27
Intel® Arria® 10
AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report
2016-12-06
Intel® Arria® 10
AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel Stratix 10 Devices
2018-01-23
Intel® Stratix® 10
AN316 High-Speed Data Interface for Stratix Devices and Fujitsu MB86064 DACx.pdf
-
AN371: Automotive Graphics System Application Note.pdf
-
AN372: Avalon TFT Controller Application Note.pdf
-
AN373: Avalon Video Input Module Application Note.pdf
-
AN375: Cyclone II FFT Co-Processor Reference Design.pdf
-
AN449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices.pdf
-
AN465: Implementing OCT Calibration in Stratix III Devices.pdf
-
AN469: Stratix III Design Guidelines.pdf
-
AN487: SPI to I2S Using MAX II CPLDs.pdf
-
AN497: LCD Controller Using MAX II CPLDs.pdf
-
AN499: Mobile SDRAM Interface Using MAX II CPLDs.pdf
-
AN503: Implementing OFDM Modulation for Wireless Communications.pdf
-
AN511: Polyphase Modulation Using FPGA for High-Speed Applications.pdf
-
AN530: Optimizing Impedance discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs.pdf
-
AN536: Design Guidelines for Preparing HardCopy II ASICs.pdf
-
AN540: Nios II MPU Usage.pdf
-
AN541: SerialLite II Hardware Debugging Guide.pdf
-
AN543: Debugging Nios II Software Using the Lauterbach Debugger.pdf
-
AN548: Nios II Compact Configuration System for Cyclone III.pdf
-
AN557: Stratix III to Stratix IV E Cross-Family Migration Guidelines.pdf
-
AN569: SDI Flywheel Video Decoder Reference Design.pdf
-
AN585: Simulation Debugging Using Triple Speed Ethernet Testbench.pdf
-
AN587: DPRIO and Multiple Instances SDI Application.pdf
-
AN600: Serial Digital Interface Demonstration for Stratix IV Devices.pdf
-
AN601: Serial Digital Interface Reference Design for Arria II GX Devices.pdf
-
AN604: High Definition Video Reference Design (UDX3).pdf
-
AN617: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices.pdf
-
AN624: Debugging with System Console over TCP/IP.pdf
-
AN629: Understanding Timing in Altera CPLDs.pdf
-
AN639: Inferring Stratix V DSP Blocks for FIR Filtering Applications.pdf
-
AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design
2015-12-14
Intel® Arria® 10|Arria® V|Stratix® IV|Stratix® V
AN656: Combining Multiple Configuration Schemes.pdf
-
AN657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices.pdf
-
AN668: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices.pdf
-
AN708.pdf
-
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP)
2015-11-02
Cyclone® IV|Arria Series|MAX Series|Stratix® II|Cyclone® III|MAX® V|Intel® Stratix® 10|Cyclone® V|MAX® II|Arria® V|Stratix® III|Intel® MAX® 10|Intel® Cyclone®|Stratix® V|Intel® Arria® 10|Stratix® IV|Arria® II|Cyclone® II|Stratix Series
AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
2017-02-01
Intel® Arria® 10
Accelerating DUC & DDC System Designs for WiMAX.pdf
-
Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum.pdf
-
Accelerating Nios II Networking Appllications.pdf
-
Adding New Design Components to the PROFINET IP.pdf
-
Altera 1588 System Solution
2016-01-28
Arria® V
Altera Design Flow for Lattice Semiconductor Users.pdf
-
Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report
2015-06-25
Wireline
Arria® V
An 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs.pdf
-
An 554: How to Read HardCopy PrimeTime Timing Reports.pdf
-
An OFDM FFT Kernel for Wireless Applications.pdf
-
Analyzing Timing of Memory IP, External Memory Interface Handbook, Volume 2, Chapter 11.pdf
-
Arria 10 SoC Device Design Guidelines.pdf
-
Arria V Timing Optimization Guidelines.pdf
-
Arria V and Cyclone V Design Guidelines.pdf
-
Automotive Audio Reference Design Application Note.pdf
-
Avalon Blocks in DSP Builder.pdf
-
Battery Management System Reference Design.pdf
-
Best Design Practices for HardCopy Devices, AN 658.pdf
-
Black Boxing in DSP Builder.pdf
-
Board Design Layout Guidelines; External Memory Interface Handbook.pdf
-
Board Design Layout Guidelines; External Memory Interface Handbook.pdf
-
Board Design Layout Guidelines; External Memory Interface Handbook.pdf
-
CORDIC Reference Design Application Note.pdf
-
Channel Estimation and Equalization for WiMAX.pdf
-
Clock Reconstruction with Low-cost External DCXO.pdf
-
Compiling and Customizing an Intel Arria 10 Custom Platform for OpenCL
2018-10-30
Intel® Arria® 10
Connecting Altera 3.3-V PCI devices to a 5-V PCI Bus.pdf
-
Constellation Mapper and Demapper for WiMAX Application Note.pdf
-
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms
2016-12-13
Cyclone® IV|Arria Series|MAX Series|Stratix® II|Cyclone® III|MAX® V|Intel® Stratix® 10|Cyclone® V|MAX® II|Arria® V|Stratix® III|Intel® MAX® 10|Intel® Cyclone®|Stratix® V|Intel® Arria® 10|Stratix® IV|Arria® II|Cyclone® II|Stratix Series
Creating an FPGA Power Tree.pdf
-
Creating an FPGA Power Tree.pdf
-
Crest Factor Reduction Application Note.pdf
-
Cyclone II DDR2 SDRAM Demonstration Application Note.pdf
-
Cyclone V SoC Power Optimization
2015-02-09
Wireless|Industrial|Wireline|Military|Broadcast|Test & Measurement|Consumer|Automotive|Medical
Cyclone® V
DDR and DDR2 SDRAM ECC Reference Design Application Note.pdf
-
DSP GizMo.pdf
-
Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer Application Note.pdf
-
Description.pdf
-
Description.pdf
-
Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices.pdf
-
Design Guidelines for HardCopy IV GX Devices.pdf
-
Designing for Stratix 10 Devices with Power in Mind
2016-06-14
Intel® Stratix® 10
Dynamic Reconfiguration of Transceiver Channels Using Multiple PLLs in Stratix IV Devices.pdf
-
EN6310QI 5.5Vin 1A Buck PowerSoC Evaluation Board User Guide.pdf
-
ER3105DI 500mA Wide VIN Synchronous Buck Regulator Evaluation Board User Guide.pdf
-
ER3110DI 1A Wide VIN Synchronous Buck Regulator Evaluation Board User Guide.pdf
-
EY1501DI-ADJ 6Vin 1A Linear Regulator Evaluation Board User Guide.pdf
-
EY1601SA-ADJ 40V, Low Quiescent Current 50mA Linear Regulator Evaluation Board User Guide.pdf
-
EY1602S-ADJ 40V, Low Quiescent Current 50mA Linear Regulator Evaluation Board User Guide.pdf
-
EY1603TI 40Vin 150mA Linear Regulator Evaluation Board User Guide.pdf
-
Erasure Decoder Reference Design
2017-05-02
End Market
All PLDs
FFT/IFFT Block Floating Point Scaling.pdf
-
Farrow-based Decimating Sample Rate Converter Application Note.pdf
-
Guidelines for Developing a Nios II HAL Device Driver
2015-06-12
Cyclone® IV|Arria Series|MAX Series|Stratix® II|Cyclone® III|MAX® V|Intel® Stratix® 10|Cyclone® V|MAX® II|Arria® V|Stratix® III|Intel® MAX® 10|Intel® Cyclone®|Stratix® V|Intel® Arria® 10|Stratix® IV|Arria® II|Cyclone® II|Stratix Series
HPS SoC Boot Guide - Cyclone V SoC Development Kit
2016-01-27
Cyclone® V
HPS SoC Boot Guide - Cyclone V SoC Developmnet Kit.pdf
-
High Definition (HD) Video Monitoring Reference Design (Milestone 4).pdf
-
High Definition (HD) Video Monitoring Reference Design (Milestone 5).pdf
-
High Definition (HD) Video Reference Design (V-Series).pdf
-
High Definition (HD) Video Reference Design (V1).pdf
-
High Definition Video Reference Design (UDX4).pdf
-
High-Definition Video Reference Design ( UDX6 ).pdf
-
High-Definition Video Reference Design ( UDX6 ).pdf
-
High-Definition Video Reference Design (UDX5) Application Note.pdf
-
High-Speed Board Designs.pdf
-
High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix V Transceivers.pdf
-
Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices
2013-12-06
Arria® V
Implementing CRCCs in Altera Devices.pdf
-
Implementing Multipliers in FPGA Devices.pdf
-
Implementing PLL Reconfiguration in Cyclone III Devices.pdf
-
Implementing PLL Reconfiguration in Stratix & Stratix GX Devices.pdf
-
Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices.pdf
-
Implementing a Queue Manager in Traffic Management Systems White Paper.pdf
-
Implementing the CPRI Protocol Using the Deterministic Latency Transceiver PHY IP Core.pdf
-
Initializing the UniPHY Nios II Sequencer in HardCopy Devices using FPP Configuration Scheme.pdf
-
Intel Arria 10 SoC Secure Boot User Guide
2017-11-06
Broadcast|Test & Measurement|Computer & Storage|Industrial|Consumer|Wireline|Medical|Military
Intel® Arria® 10
Intel Cyclone 10 GX Device Design Guidelines
2017-11-06
Industrial
Intel® Cyclone® 10 GX
Intel Cyclone 10 LP Device Design Guidelines
2019-03-28
Intel® Cyclone® 10 LP
Intel MAX 10 FPGA Design Guidelines
2020-10-19
Intel® MAX® 10
Interfacing Cyclone III Device with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.pdf
-
Interfacing DDR SDRAM with Stratix & Stratix GX Devices.pdf
-
Interfacing DDR SDRAM with Stratix II Devices.pdf
-
Interlaken IP Core Feature and Interface Differences Between Stratix 10, Arria 10, and Stratix V Devices
2017-06-12
Wireless|Industrial|Wireline|Military|Broadcast|Test & Measurement|Computer & Storage|Consumer|Automotive|Medical
Stratix® V|Intel® Stratix® 10|Intel® Arria® 10
Internal Memory (RAM and ROM) User Guide.pdf
-
MAX II ISP Update with I/O Control & Register Data Retention.pdf
-
Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices (AN 578).pdf
-
Multioutput Scalar Reference Design.pdf
-
Nios II Flash Accelerator Using Max10
2015-06-30
Intel® MAX® 10
Nios II Gen2 Migration Guide
2015-06-12
Cyclone® IV|Intel® Cyclone®|Arria Series|Stratix® II|MAX Series|Cyclone® III|MAX® V|Stratix® V|Intel® Stratix® 10|Cyclone® V|MAX® II|Intel® Arria® 10|Arria® V|Stratix® IV|Stratix® III|Arria® II|Intel® MAX® 10|Cyclone® II|Stratix Series
PCB Breakout Routing for High-Density Serial Channel Designs Beyond 10 Gbps AN 651.pdf
-
PCB Stackup Design Considerations for Intel FPGAs
2017-06-28
Wireless|Industrial|Military|Computer & Storage|Consumer|Medical|Wireline|Broadcast|Test & Measurement|Automotive
Cyclone® IV|Cyclone® III|MAX® V|Intel® Stratix® 10|Cyclone® V|Arria® V|Intel® MAX® 10|Stratix® V|Intel® Cyclone® 10|Intel® Arria® 10|Stratix® IV|Arria® II
PCI Express Avalon -MM DMA Reference Design
2017-05-08
Industrial
Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® V
PCI Express DMA Reference Design Using External Memory
2017-05-17
Industrial
Cyclone® V|Intel® Arria® 10|Arria® V|Stratix® V
PCI Express High Performance Reference Design
2018-12-12
Cyclone Series|Arria Series|Stratix Series
PCI Express: Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface
2017-05-08
Computer & Storage
Intel® Arria® 10|Intel® Stratix® 10
POS-PHY Level 4 (SPI-4.2) Loopback Reference Design.pdf
-
POS-PHY Level 4 MegaCore Function Parameter Selection Calculator.pdf
-
POS-PHY Level 4 MegaCore Function v2.1.0 Wrapper Features.pdf
-
PROFINET IRT: Getting Started with the Siemens CPU 315 PLC Application Note.pdf
-
PROFINET Reference Design Bootstrap and Flash Access Application Note.pdf
-
Parallel Flash Loader Megafunction User Guide.pdf
-
Porting the Nios GERMS Monitor to Work with Different Flash Memories.pdf
-
Power Management in Portable Systems Using MAX II CPLDs.pdf
-
Prime Number Generator - Maker Faire 2014.pdf
-
Product Security Features for Altera Devices.pdf
-
Profiling Nios II Systems Application Note 391.pdf
-
Putting Altera MAX Series in Hibernation Mode Using User Flash Memory
2016-01-14
Broadcast
MAX® II|MAX Series|MAX® V|Intel® MAX® 10
Qsys System Design Tutorial
2015-05-04
All PLDs
RTFM setup and demo..pdf
-
Replacing Serial EEPROMs with User Flash Memory in Altera MAX Series.pdf
2014-09-22
SCHEMATIC1 : PAGE1.pdf
-
SDI-ASI Auto Detect Reference Design for Stratix II GX Devices.pdf
-
SGMII Interface Implementation Using Soft CDR Mode of Altera FPGAs.pdf
-
SMBus Interface for the User Flash Memory in MAX II Devices.pdf
-
SOPC Builder to Qsys Migration Guidelines AN 632.pdf
-
SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices.pdf
-
SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices.pdf
-
Scalable OFDMA Engine for WiMAX Application Note.pdf
-
Serial Digital Interface Reference Design for Cyclone IV GX Devices.pdf
-
Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design.pdf
-
Signal Integrity Analysis with Third-Party Tools.pdf
-
Simulating Altera Devices with IBIS Models.pdf
-
Standard Cell ASIC to FPGA Design Methodology and Guidelines.pdf
-
Stratix Filtering Reference Design, Application Note 245.pdf
-
Stratix GX 1.5-V PCML to Mercury LVDS Interoperability.pdf
-
Stratix V Design Guidelines.pdf
-
Stratix V GT Device Design Guidelines.pdf
-
System Development Tools for Excalibur Devices.pdf
-
Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver Application Note.pdf
-
The Quartus II TimeQuest Timing Analyzer.pdf
-
Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array Application Note.pdf
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Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array Application Note.pdf
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Thermal Management for FPGAs.pdf
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Tool Flow for Design of Digital IF for Wireless Systems.pdf
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Understanding PLL Timing for Stratix II Devices.pdf
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Understanding the Pre-Emphasis and Linear Equalization Features in Stratix IV GX Devices.pdf
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Untitled Document.pdf
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Updating Simulation Models for the POS-PHY Level 4 MegaCore Function.pdf
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Upgrading Nios Processor Systems to the Nios II Processor.pdf
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Upgrading a FIR Compiler v3.1.x Design to v3.2.x.pdf
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Using Altera Devices in Multiple-Voltage Systems.pdf
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Using DDR/DDR2 SDRAM With SOPC Builder.pdf
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Using External Termination with Stratix and Stratix GX Devices.pdf
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Using MAX II CPLDs as Analog Keyboard Encoders.pdf
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Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
2015-07-08
Cyclone® IV|Intel® Cyclone®|Arria Series|MAX Series|Stratix® II|Cyclone® III|MAX® V|Stratix® V|Intel® Stratix® 10|Cyclone® V|MAX® II|Intel® Arria® 10|Arria® V|Stratix® IV|Stratix® III|Arria® II|Intel® MAX® 10|Cyclone® II|Stratix Series
Using the On-Chip Signal Quality Monitoring Circuitry (EyeQ) Feature in Stratix IV Transceivers.pdf
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Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
2015-12-04
Cyclone® V|Arria® V
Vectored Interrupt Controller Usage and Applications.pdf
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Video and Image Processing Design Example.pdf
2018-12-21
Vision Processing with the Canny Edge Detection Reference Design
2015-02-14
Broadcast|Industrial|Automotive|Medical
Cyclone® V|Intel® Arria® 10
an458.fm.pdf
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library ieee;.pdf
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library ieee;.pdf
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