Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel FPGA IP Release Notes

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RN-1206 | 2019.10.25

Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel FPGA IP Release Notes

If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel^® Quartus^® Prime Design Suite Update Release Notes.

IP versions are the same as the Intel^® Quartus^® Prime Design Suite software versions up to v19.1. From Intel^® Quartus^® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:

X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel FPGA IP v19.2.0

Table 1. v19.2.0 2019.09.30
Intel^® Quartus^® Prime Version	Description	Impact
19.3	Initial release for Intel^® Agilex™ devices for the following embedded memory IP cores: RAM: 1-PORT Intel^® FPGA IP RAM: 2-PORT Intel^® FPGA IP RAM: 4-PORT Intel^® FPGA IP ROM: 1-PORT Intel^® FPGA IP ROM: 2-PORT Intel^® FPGA IP	—

Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel FPGA IP v18.0

Table 2. v18.0 May 2018
Description	Impact
Renamed the following IP cores as per Intel rebranding: RAM: 1-PORT IP core to RAM: 1-PORT Intel^® FPGA IP RAM: 2-PORT IP core to RAM: 2-PORT Intel^® FPGA IP RAM: 4-PORT IP core to RAM: 4-PORT Intel^® FPGA IP ROM: 1-PORT IP core to ROM: 1-PORT Intel^® FPGA IP ROM: 2-PORT IP core to ROM: 2-PORT Intel^® FPGA IP	—