Intel Quartus Prime Pro Edition User Guide: Design Constraints
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 21.2 |
1. Constraining Designs
You can specify design constraints in the GUI, with scripts, or directly in the files that store the constraints. The Intel® Quartus® Prime software preserves the constraints that you specify in the GUI in the following files:
- Intel® Quartus® Prime Settings file (<project_directory>/<revision_name>.qsf)—contains project-wide and instance-level assignments for the current revision of the project, in Tcl syntax. Each revision of a project has a separate .qsf file.
- Synopsys* Design Constraints file (<project_directory>/<revision_name>.sdc)—the Timing Analyzer uses industry-standard Synopsys* Design Constraint format and stores those constraints in .sdc files.
1.1. Specifying Design Constraints Designs in the GUI
When you create or update a constraint in the Intel® Quartus® Prime software, the System tab of the Messages window displays the equivalent Tcl command. Utilize these commands as references for future scripted design definition and compilation.
1.1.1. Global Constraints and Assignments
| Setting Type | New Project Wizard | Device Dialog Box | Settings Dialog Box |
|---|---|---|---|
| Project-wide | X | X | X |
| Synthesis | X | X | X |
| Fitter | X | X | X |
| Simulation | X | ||
| Third-party Tools | X | ||
| IP Settings | X |
1.1.2. Node, Entity, and Instance-Level Constraints
| Assignment Type | Assignment Editor | Interface Planner | Chip Planner | Pin Planner |
|---|---|---|---|---|
| Pin | X | X | X | |
| Location | X | X | X | |
| Routing | X | X | ||
| Simulation | X | X | X |
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
- Add, edit, or delete assignments for selected nodes
- Display information about specific assignments
- Enable or disable individual assignments
- Add comments to an assignment
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
For example, you can specify the following assignment to apply a constraint to all bits in the reg [31:0] r [0:2][4:5] three-dimensional bus:
set_instance_assignment -name PRESERVE_REGISTER ON -to r
The constraint then applies to all bits r: [0][4][31], r[0][4][30], … , r[1][5][0].
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner
Interface Planner interacts dynamically with the Intel® Quartus® Prime Fitter to accurately verify placement legality while you plan. You can evaluate different floorplans, using interactive reports to accurately plan the best implementation without iterative compilation. Fitter verification ensures the highest correlation between your interface plan and actual implementation results. You can apply the interface plan constraints to your project with high confidence in the final implementation.
1.1.2.5. Adjust Constraints with the Chip Planner
With the Chip Planner you can adjust existing assignments to device resources, such as pins, logic cells, and LABs in a graphical representation of the device floorplan. You can also view equations and routing information and demote assignments by dragging and dropping to Logic Lock regions in the Logic Lock Regions Window.
1.1.2.6. Constraining Designs with the Design Partition Planner
The Design Partition Planner allows you to view design connectivity and hierarchy and can assist you in creating effective design partitions.
Additionally, the Design Partition Planner allows you to optimize design performance by isolating and resolving failing paths on a partition-by-partition basis.
1.1.3. Probing Between Components of the Intel Quartus Prime GUI
When you are in the Project Navigator, Assignment Editor, Chip Planner, or Pin Planner, and want to display a given resource in other Intel® Quartus® Prime tool:
- Right-click the resource you want to display.
- Click Locate Node, and then click any of the menu options.
The corresponding window opens—or appears in the foreground if it is already open—and shows the element you clicked.
Locate a Resource Selected in the Project Navigator
In the Entity list of the Hierarchy tab, right-click any object, and click .
The Chip Planner opens and displays the instance you selected.
1.1.4. Specifying Timing Constraints in the GUI
When you specify a constraint in the GUI, the dialog box displays the equivalent SDC command syntax.
Create Clock Dialog Box
Individual timing assignments override project-wide requirements.
- To avoid reporting incorrect or irrelevant timing violations, you can assign timing exceptions to nodes and paths.
- The Timing Analyzer supports point-to-point timing constraints, wildcards to identify specific nodes when making constraints, and assignment groups to make individual constraints to groups of nodes.
1.2. Constraining Designs with Tcl Scripts
When you use Intel® Quartus® Prime Tcl packages, your scripts can open projects, make the assignments, compile the design, and compare compilation results against known goals and benchmarks. Furthermore, such a script can automate the iterative design process by modifying constraints and recompiling the design.
1.2.1. Create a Project and Apply Constraints
The example creates a project with a Tcl script and applies project constraints using the tutorial design files in the < Intel® Quartus® Prime installation directory> /qdesigns/fir_filter/ directory.
project_new filtref -overwrite # Assign family, device, and top-level file set_global_assignment -name FAMILY "Arria 10" set_global_assignment -name DEVICE <Device> set_global_assignment -name VERILOG_FILE filtref.v # Assign pins set_location_assignment -to clk Pin_28 set_location_assignment -to clkx2 Pin_29 set_location_assignment -to d[0] Pin_139 set_location_assignment -to d[1] Pin_140 # project_close
Save the script in a file called setup_proj.tcl and type the commands illustrated in the example at a command prompt to create the design, apply constraints, compile the design, and perform fast-corner and slow-corner timing analysis. Timing analysis results are saved in two files, filtref_sta_1.rpt and filtref_sta_2.rpt.
quartus_sh -t setup_proj.tcl quartus_syn filtref quartus_fit filtref quartus_asm filtref quartus_sta filtref --model=fast --export_settings=off mv filtref_sta.rpt filtref_sta_1.rpt quartus_sta filtref --export_settings=off mv filtref_sta.rpt filtref_sta_2.rpt
Type the following commands to create the design, apply constraints, and compile the design, without performing timing analysis:
quartus_sh -t setup_proj.tcl quartus_sh --flow compile filtref
The quartus_sh --flow compile command performs a full compilation, and is equivalent to clicking the Start Compilation button in the toolbar.
1.2.2. Assigning a Pin
To assign a signal to a pin or device location, use the Tcl command shown in this example:
set_location_assignment -to <signal name> <location>
Valid locations are pin location names. Some device families also support edge and I/O bank locations. Edge locations are EDGE_BOTTOM, EDGE_LEFT, EDGE_TOP, and EDGE_RIGHT. I/O bank locations include IOBANK_1 to IOBANK_n, where n is the number of I/O banks in a device.
1.2.3. Generating Intel Quartus Prime Settings Files
To generate a .qsf file from the Intel® Quartus® Prime software, click .
To organize the .qsf in a human readable form, .
Organized .qsf File
This example shows how .qsf files characterize a design revision. The set_global_assignment command makes all global constraints and software settings and set_location_assignment constrains each I/O node in the design to a physical pin on the device.
# Project-Wide Assignments # ======================== set_global_assignment -name SYSTEMVERILOG_FILE top.sv set_global_assignment -name SYSTEMVERILOG_FILE blinking_led.sv set_global_assignment -name SDC_FILE blinking_led.sdc set_global_assignment -name SDC_FILE jtag.sdc set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Pro Edition" set_global_assignment -name TEXT_FILE blinking_led_generated.txt # Pin & Location Assignments # ========================== set_location_assignment PIN_AN18 -to clock set_location_assignment PIN_AR23 -to led_zero_on set_location_assignment PIN_AM21 -to led_two_on set_location_assignment PIN_AR22 -to led_one_on set_location_assignment PIN_AL20 -to led_three_on # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Arria 10" set_global_assignment -name TOP_LEVEL_ENTITY top # Fitter Assignments # ================== set_global_assignment -name DEVICE 10AS066N3F40E2SG # ----------------- # start ENTITY(top) # Fitter Assignments # ================== set_instance_assignment -name IO_STANDARD "1.8 V" -to led_zero_on set_instance_assignment -name IO_STANDARD "1.8 V" -to led_one_on set_instance_assignment -name IO_STANDARD "1.8 V" -to led_two_on set_instance_assignment -name IO_STANDARD "1.8 V" -to led_three_on set_instance_assignment -name SLEW_RATE 1 -to led_zero_on set_instance_assignment -name SLEW_RATE 1 -to led_one_on set_instance_assignment -name SLEW_RATE 1 -to led_two_on set_instance_assignment -name SLEW_RATE 1 -to led_three_on set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to clock set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_zero_on set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_one_on set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_two_on set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_three_on # end ENTITY(top) # ---------------
1.2.4. Synopsys Design Constraint (.sdc) Files
.sdc File
The example shows the timing constrains of a small design.
## PROGRAM "Quartus Prime"
## VERSION "Version 17.1.0 Internal Build 91 05/07/2017 SJ Pro Edition"
## DATE "Wed May 10 14:22:08 2017"
##
## DEVICE "10AX115R4F40I3SG"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_in} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk_in}]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {clk_in}] 1.500 [get_ports {async_rst}]
set_input_delay -add_delay -clock [get_clocks {clk_in}] 1.200 [get_ports {data_in}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {clk_in}] 2.000 [get_ports {data_out}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -setup -end -from [get_keepers *] -to [get_keepers {reg2}] 2
1.2.5. Tcl-only Script Flows
You can export a design's contents to a procedural, executable Tcl (.tcl) file, and then use the generated script to restore settings after experimenting with other constraints.
To export your constraints as an executable Tcl script, click .
blinking_led_generated.tcl File
# Quartus Prime: Generate Tcl File for Project
# File: blinking_led_generated.tcl
# Generated on: Wed May 10 10:14:44 2017
# Load Quartus Prime Tcl Project package
package require ::quartus::project
set need_to_close_project 0
set make_assignments 1
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "blinking_led"]} {
puts "Project blinking_led is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists blinking_led]} {
project_open -revision blinking_led blinking_led
} else {
project_new -revision blinking_led blinking_led
}
set need_to_close_project 1
}
# Make assignments
if {$make_assignments} {
set_global_assignment -name SYSTEMVERILOG_FILE top.sv
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led.sv
set_global_assignment -name SDC_FILE blinking_led.sdc
set_global_assignment -name SDC_FILE jtag.sdc
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Pro Edition"
set_global_assignment -name TEXT_FILE blinking_led_generated.txt
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name DEVICE 10AS066N3F40E2SG
set_location_assignment PIN_AN18 -to clock
set_location_assignment PIN_AR23 -to led_zero_on
set_location_assignment PIN_AM21 -to led_two_on
set_location_assignment PIN_AR22 -to led_one_on
set_location_assignment PIN_AL20 -to led_three_on
set_instance_assignment -name IO_STANDARD "1.8 V" -to led_zero_on
set_instance_assignment -name IO_STANDARD "1.8 V" -to led_one_on
set_instance_assignment -name IO_STANDARD "1.8 V" -to led_two_on
set_instance_assignment -name IO_STANDARD "1.8 V" -to led_three_on
set_instance_assignment -name SLEW_RATE 1 -to led_zero_on
set_instance_assignment -name SLEW_RATE 1 -to led_one_on
set_instance_assignment -name SLEW_RATE 1 -to led_two_on
set_instance_assignment -name SLEW_RATE 1 -to led_three_on
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to clock
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_zero_on
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_one_on
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_two_on
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to led_three_on
# Commit assignments
export_assignments
# Close project
if {$need_to_close_project} {
project_close
}
}
The example:
- Opens the project
- Assigns Constraints
- Writes assignments to QSF file
- Closes project
1.2.5.1. Tcl-only Timing Analysis
1.3. A Fully Iterative Scripted Flow
1.4. Constraining Designs Revision History
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2019.10.16 | 19.3.0 |
|
| 2019.08.21 | 18.1.0 | Corrected minor typo in "Tcl-only Script Flows" topic. |
| 2019.01.04 | 18.1.0 |
|
| 2017.11.06 | 17.1.0 |
|
| 2017.05.08 | 17.0.0 |
|
| 2016.10.31 | 16.1.0 |
|
| 2015.11.02 | 15.1.0 |
|
| June 2014 | 14.0.0 | Formatting updates. |
| November 2012 | 12.1.0 | Update Pin Planner description for task and report windows. |
| June 2012 | 12.0.0 | Removed survey link. |
| November 2011 | 10.0.2 | Template update. |
| December 2010 | 10.0.1 | Template update. |
| July 2010 | 10.0.0 | Rewrote chapter to more broadly cover all design constraint methods. Removed procedural steps and user interface details, and replaced with links to Quartus II Help. |
| November 2009 | 9.1.0 |
|
| March 2009 | 9.0.0 |
|
| November 2008 | 8.1.0 | Changed to 8½” × 11” page size. No change to content. |
| May 2008 | 8.0.0 | Updated Quartus II software 8.0 revision and date. |
2. Interface Planning
You can use the Interface Planner to prototype interface implementations, plan clocks, and rapidly define a legal device floorplan.
Similarly, when targeting the Intel® Agilex™ F-tile devices, you can use the Tile Interface Planner build a plan for placement of IP components in each tile available on the FPGA device.
Interface Planner and Tile Interface Planner interact dynamically with the Intel® Quartus® Prime Fitter to accurately verify placement legality while placing elements. You can evaluate different floorplans, using interactive reports to accurately plan the best implementation without iterative compilation. Fitter verification ensures the highest correlation between your interface plan or tile interface plan and actual implementation results. You can apply the interface plan or tile interface plan constraints to your project with high confidence in the final implementation.
2.1. Using Interface Planner
Interface Planner displays your project's logical hierarchy, post-synthesis design elements, and Fitter-created design elements, alongside a view of target device locations. The GUI supports a variety of methods for placing design elements in the floorplan. As you place elements in the floorplan, the Fitter verifies legality in real time to ensure accurate correlation with the final implementation.
Intel® FPGAs contain core and periphery device locations. The device core locations are adaptive look-up tables (ALUTs), core flip-flops, RAMs, and digital signal processors (DSPs). Device periphery locations include I/O elements, phase-locked loops (PLLs), clock buffers, and hard processor systems (HPS).
Intel® FPGAs contain many silicon features in the device periphery, such as hard PCI Express® IP cores, high speed transceivers, hard memory interface circuitry, and embedded processors. Interactions among these periphery elements can be complex. Interface Planner simplifies this complexity and allows you to quickly visualize and place I/O interface and periphery elements, such as:
- I/O elements
- LVDS interfaces
- PLLs
- Clocks
- Hard interface IP Cores
- High-Speed Transceivers
- Hard Memory Interface IP Cores
- Embedded Processors
2.1.1. Interface Planner User Interface
2.1.1.1. Flow Controls
| Command | Description |
|---|---|
| Open Project | Allows you to select and open an Intel® Quartus® Prime project in Interface Planner. Use of Open Project command is only required when using Interface Planner in standalone mode. |
| Initialize Interface Planner | Loads the synthesis netlist, starts the Fitter verification engine, and imports assignments from your Intel® Quartus® Prime project. |
| View Assignments | Opens the Assignments tab, which allows you to review and reconcile any conflicting assignments that Interface Planner imports from your project. Enable or disable specific project assignments to resolve any conflicts. |
| Update Plan | Applies the enabled project assignments to your interface plan. You cannot perform periphery planning on the Plan tab until you update the plan. |
| Plan Design | Opens the Plan tab for placing logic in the interface plan. |
| Export Constraints | Saves your interface plan as a Tcl script file for subsequent application in your project. This command is available only after successfully running Validate Plan. |
| Validate plan | Verifies that all constraints in the interface plan are compatible with placement of all remaining unplaced design elements. You can then directly locate and resolve the source of any reported validation errors. You must successfully validate the plan before running Write Plan File. |
| View Reports | Opens the Reports tab for filtering data and finding entities and locations. |
2.1.1.2. Home Tab Controls
| Command | Description |
|---|---|
| Recent Projects | Provides quick access to recently opened Intel® Quartus® Prime projects. A named tile represents each project. Click the tile to display Details about the project. Double-click the tile to open the project in Interface Planner. |
| Browse | Allows you to locate and open an Intel® Quartus® Prime project in Interface Planner. Interface Planner requires the project's synthesized netlist for operation. |
| Details | Provides project and file details such as the file path, revision, and creation date of the Intel® Quartus® Prime project. You can select a specific project revision. |
2.1.1.3. Assignments Tab Controls
You can enable or disable specific or classes of assignments until you resolve all potential conflicts. After you are satisfied with the status of all project assignments, click Update Plan to update your interface plan with the enabled project assignments. Interface Planner reports an error for any remaining assignment conflicts.
| Command | Description |
|---|---|
| Filter field | Supports creation of wildcard expressions for assignment targets. Enabled and Disabled buttons filter only enabled or disabled assignments in the list. |
| Enable All Project Assignments | Enables all imported project assignments in your interface plan. |
| Disable All Project Assignments | Disables all imported project assignments in the plan. |
| Clear | Clears any filter from the Assignments list. |
2.1.1.4. Plan Tab Controls
Placement or unplacement in the interface plan does not apply to your Intel® Quartus® Prime project until you add the generated Interface Planner constraints script to your project.
| Command | Description |
|---|---|
|
Lists legal locations for placement. |
| Locate Node | Display a list of Intel® Quartus® Prime Pro Edition tools where the selected design element is referenced in the hierarchical database. If the Locate Node command is disabled for a specific element in the Design Elements list, it is because that element is not represented as an element in the design. |
| Autoplace All | Attempts to place all unplaced design elements in legal locations in the interface plan. |
| Autoplace Fixed | Attempts to place all unplaced design elements that have only one legal location into the interface plan. |
| Unplace All | Unplaces all placed design elements in the interface plan. |
| Attempts to place the selected design element and all its children in a legal location in the interface plan. | |
| Chip View | Displays the target device chip. Zoom in to display chip details. |
| Package View | Displays the target device package. Zoom in to display chip details. |
| Show I/O Banks | Selects and color codes the I/O banks in the Plan tab. |
| Show Differential Pin Pair Connections | Displays a red connection line between a pair of differential pins. The Package View labels the positive and negative pins with the letters p and n, respectively. |
| Show PCIe Hard IP Interface Pins | Selects and color codes the PCIe Hard IP interface pins in the Plan tab. To access this command, right-click in the Plan tab package view, and select x1 Lanes, x2 Lanes, x4 Lanes, x8 Lanes, or by 16 Lanes. After enabling, view color coding in the Color Legend. |
| Show DQ/DQS Pins | Selects and color codes the PCIe Hard IP interface pins in the Plan tab. To access this command, right-click in the Plan tab package view, and select x4 Mode, x8/x9 Mode, x16/x16 Mode, or x32/x36 Mode. After enabling, view color coding in the Color Legend. |
| Displays detailed information on the Reports tab, showing legal locations in the interface plan for the selected cell in order of suitability for fitting. | |
| Copy Current View | Copies the current interface plan to the clipboard for pasting into other files, such as word processing or presentation files. |
| Reset Plan | Unplaces all placed design elements and removes applied project assignments from the interface plan. Resets all project assignments to the enabled state. You must subsequently run Update Plan prior to placing design elements. This command only applies to your interface plan and does not impact your Intel® Quartus® Prime project assignments until you apply the Interface Planner script. |
| Load Floorplan | Allows you to select and load an Interface Planner Floorplan Format (.plan) file. You can save Interface Planner floorplan files in the format by clicking Save Floorplan. |
| Save Floorplan | Allows you to save your Interface Planner floorplan as a .plan file. |
| Undo/Redo buttons | The Undo button reverts the last change made in the Plan tab. Redo re-implements the last undo. Use these commands to step forward and backward though your plan changes. |
2.1.1.5. Reports Tab Controls
| Command | Description |
|---|---|
| Create all Summary Reports | Creates the following summary
reports:
|
| Report All Placed/Unplaced Pins | Reports the name, parent (if any), and type of all placed (Report All Placed Pins) or unplaced (Report All Unplaced Pins) pins in the interface plan, respectively. The Placed Pins report includes the placement location name. The Unplaced Pins report includes the number of potential placement locations. Right-click any cell to place, unplace, or report connectivity or location information. |
| Report All Placed/Unplaced HSSI Channels | Reports the name, parent (if any), and type of all placed (Report All Placed HSSI Channels) or unplaced (Report All Unplaced HSSI Channels) channels in the interface plan, respectively. The Placed HSSI Channels report includes the placement location name. The Unplaced HSSI Channels report includes the number of potential placement locations. Right-click any cell to place, unplace, or report connectivity or location information. |
| Reports the name, parent (if any), and type of placed (Report Placed Periphery Cells of Selected Type) or unplaced (Report Unplaced Periphery Cells of Selected Type) cells matching the selected type. The placed cells report includes the placement location name. The unplaced cells report includes the number of potential placement locations. Right-click any cell to place, unplace, or report connectivity or location information. | |
| Reports all locations in the device of the selected type, and whether the location supports merging. | |
| Reports the source port and type, destination port and type, of connections to the selected cell. Right-click any cell to report the individual cell connectivity. | |
| Places the cell in the selected location of the interface plan. Similarly, you can right-click any cell and then click Place Cell of Selected Type or Unplace Cell of Selected Type to place or unplace multiple cells of the same type. | |
| Reports the preferred legal locations for the selected cell in the interface plan in the Legal Location report. Right-click to immediately place the cell in a location or report all periphery location of the selected type. | |
| Remove Invalid Reports | Removes outdated Interface Planner reports that you invalidate by changes to the interface plan. |
| Report Instance Assignments | Shows all imported project assignments in the interface plan. You can delete these assignments from the plan. |
2.1.2. Interface Planner Tool Flow
As you run each step in the Flow control, downstream commands and the Assignments, Plan, and Reports tabs become available. Interface Planner only allows you to run commands after completing any prerequisite steps in the flow.
After you Initialize Interface Planner , you are prompted to confirm any project assignments that you made before planning starts. Disable or enable any imported project assignments on the Assignments tab to resolve any conflicts and evaluate different implementations.
After you Update Plan with the project assignments, you are ready to place design elements onto the target device Chip View or Package View on the Plan tab. As you place design elements in the Plan tab, the Fitter verifies placement legality in real-time. Once planning is complete and validated, you export the constraints as a Tcl script for application in your project.
The following topics describe these interface planning flow steps in detail:
2.1.2.1. Step 1: Setup and Synthesize the Project
2.1.2.2. Step 2: Initialize Interface Planner
2.1.2.3. Step 3: Update Plan with Project Assignments
2.1.2.4. Step 4: Plan Periphery Placement
For efficiency, place design elements in the following order in Interface Planner:
- Place all I/O pins or elements, such as PLLs, that have known, specific location requirements.
- Place all known periphery interface IP.
- (Optional) Place all remaining unplaced cells.
Use the following controls to place design elements in the Interface Planner floorplan:
- Locate design elements that you want to place in the Design Element list. You can search and filter the list by name, IP, placement status, I/Os, and other criteria.
- To customize design element color coding definitions, click the Highlight column. Figure 13. Interface Planner (Plan Tab)
- Use any of the following methods to place design elements in the floorplan:
- Drag elements from the Design Elements list and drop them onto available device resources in the Chip or Package view. Use Ctrl+Click to drag and pan across the Chip or Package views. You may experience a small delay while dragging as Interface Planner calculates the legal locations.
- To allow Interface Planner to place an unplaced design element in a legal location, right-click and select Autoplace Selected. You must use Autoplace Selected for all unplaced clocks .
- Click the button next to the Design Elements to display a list of Legal Locations. Click any legal location in the list to
highlight the location in the floorplan. Double-click any location in the list to place
the element in the location.
Figure 14. Listing Legal Locations - To step forward and backward though your plan changes, click the Undo and Redo buttons.
- To visualize and traverse design connectivity (for example, to view the reference clock pin and driven destination cells of a PLL), select any design element and then click the Link Info tab. Click the Back and Forward buttons to traverse design connectivity.
- To generate a report that shows the placement locations the Fitter prefers, select a design element and click Report Placeability of Selected Element.
2.1.2.4.1. Plan Clock Networks
Interface Planner generates a Clocks report that details the signals using low-skew routing networks (clock networks) in the device.
To identify and place clocking elements in your design, click the Clocking filter in the Plan tab. You can refine the list further by entering search text in the Design Element Filter. Interface Planner represents clock networks as groupings of the following clock network elements:
- Clock source
- Clock mux
- Clock region
You can place an entire clock group or individual clock elements by dragging into the location, or using the Report Legal Locations of Selected Element or the Autoplace Selected commands. After placement, hover the cursor over the item in the Design Element list to highlight the placement. The placement of clock elements impacts the placement of dependent core and periphery elements.
You can edit the clock type for clocking design elements. The clock type impacts the placement of dependent core and periphery elements. Right-click any clock element to specify one of the following clock types:
- Not Set
- Locally Routed
- Global
- Large Periphery
- Periphery
- Regional
2.1.2.4.2. Saving & Loading Floorplans
- To save an Interface Planner floorplan, click and specify a file name.
- To load an Interface Planner floorplan, click and browse for the .plan file.
2.1.2.5. Step 5: Report Placement Data
2.1.2.6. Step 6: Validate and Export Plan Constraints
2.1.3. Interface Planner Reports
2.1.3.1. Report Summary
| Command | Description |
|---|---|
| Create all Summary Reports | Creates the following summary
reports:
|
2.1.3.2. Report Pins
| Command | Description |
|---|---|
| Report All Placed Pins | Generates the Placed Pins report. This report lists the name, parent, type, and location of all placed pins in the interface plan. |
| Report All Unplaced Pins | Generates the Unplaced Pins report. This report lists the name, parent, type, and the number of potential placements for all unplaced pins in the interface plan. |
2.1.3.3. Report HSSI Channels
| Command | Description |
|---|---|
| Report All Placed HSSI Channels | Generates the Placed HSSI Channels report. This report lists the name, parent, type, and location of all placed HSSI RX/TX channels in the interface plan. |
| Report All Unplaced HSSI Channels | Generates the Unplaced HSSI Channels report. This report lists the name, parent, type, and location of all unplaced HSSI RX/TX channels in the interface plan. |
2.1.3.4. Report Clocks
| Command | Description |
|---|---|
| Report Clocks | Generates the Global and other Fast Signals report. |
2.1.3.5. Report Periphery Locations
| Command | Description |
|---|---|
| Accessible from the All Periphery Cells report. This command reports the name, parent (if any), type, and location of the selected placed periphery cells matching the selected type. Right-click any cell to place, unplace, or report connectivity or location information. | |
| Accessible from the All Periphery Cells report. This command reports the name, parent (if any), type, and number of suitable locations for the selected unplaced periphery cells matching the selected type. Right-click any cell to place, unplace, or report connectivity or location information. | |
| Reports all locations in the device of the selected type, and whether the location supports merging. |
2.1.3.6. Report Cell Connectivity
| Command | Description |
|---|---|
| Right-click any Cell Name in the reports to Report Periphery Cell Connectivity. The report lists the source and destination ports and type of connections to the selected cell. Right-click any cell to report all connections to the cell. |
2.1.3.7. Report Instance Assignments
| Command | Description |
|---|---|
| Report Instance Assignments | Reports all enabled instance assignments in your design. Right-click any cell to delete the assignment or to delete all assignments of the same type. |
2.2. Using Tile Interface Planner
The Intel® Quartus® Prime Tile Interface Planner helps you to quickly place component IP in legal tile locations of F-tile. Tile Interface Planner is an interactive floorplanning tool that simplifies legal placement of component IP on device tiles.
Tile Interface Planner displays your project component IP in a hierarchical tree view, next to a visual representation of the device tile segments. You can then locate the potential legal locations for each IP within the tile, place the IP at the location, and apply the placement constraints to the project for downstream Compiler stages.
As you place elements in the tile floorplan, the legality engine verifies that the placement is legal in real-time, thus ensuring correlation with your intent in the final implementation.
In contrast with Interface Planner, Tile Interface Planner is specifically for placing component IP on the F-tile, and requires you to run an initial Design Analysis stage before you define a legal tile floorplan for all component IP targeting device tiles.
2.2.1. Tile Interface Planner Terminology
| Term | Description |
|---|---|
| Floorplan | The layout of physical resources on the device. Creating a design floorplan, or floorplanning, is the process of mapping the logical design hierarchy to physical regions in the device. Tile Interface Planner is a tile IP floorplanning tool. |
| IP building block |
Intel® FPGA IP cores are comprised of building blocks that combine to provide all functionality of the IP. The Design Tree view displays each IP's building blocks. Building blocks can be movable, fixed, or always movable type of building blocks. |
| Intel® Quartus® Prime Settings File (.qsf) | Intel® Quartus® Prime software internal file that preserves project settings and assignments, including the placement of fixed IP building blocks and fixed tile assignments that you specify in Tile Interface Planner. |
| JSON file | Intel® Quartus® Prime software internal file that preserves the placement of movable IP building blocks that you specify in Tile Interface Planner. You can load this file when you click Update Assignments, so that you see the same movable placements from a prior session. |
| Legal location | Tile Interface Planner legality engine identifies the legal locations in the tile floorplan for placement of the IP or building block that you select in the Design Tree. |
| Legality engine | Tile Interface Planner function that generates valid legal locations for tile placement, and places movable and always movable building blocks in the tile plan. |
| Placed design element | IP or building block that you or the legality engine has assigned to a fixed or movable legal location. |
|
Support-Logic Generation stage |
A Compiler stage, preceding Analysis & Synthesis, that includes the
Design Analysis and Logic Generation sub-stages. This stage is only
present when targeting F-tile.
|
| Tile plan | One or more fixed placements that you define and save in Tile Interface Planner using the (.qsf). |
| Unplaced design element | IP or building blocks that are unassigned to a fixed or movable legal location. |
2.2.2. Tile Interface Planner Tool Flow
- Step 1: Instantiate IP and Run Design Analysis—Tile Interface Planner first requires a design with component IP, targeting the Intel® Agilex™ FPGA with F-tile. After initial design setup, you run Design Analysis to elaborate the component IP in the design.
- Step 2: Initialize Tile Interface Planner—launch Tile Interface Planner, load component IP and existing assignment data, and initialize the legality engine.
- Step 3: Update Plan with Project Assignments—enable or disable any existing placement assignments and optionally load placement data from previous planning sessions for the current tile planning session.
- Step 4: Create a Tile Plan—use the Plan tab to locate the potential legal locations for each unplaced component IP, place the IP in the tile location, and verify that the placement is legal in real-time to ensure correlation in the final implementation.
- Step 5: Save Tile Plan Assignments—save the tile IP plan assignments to the project for design compilation.
- Step 6: Run Logic Generation and Design Synthesis—run the Compiler Logic Generation stage to implement your tile plan and continue synthesis and the remaining design compilation stages.
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis
After instantiating the component IP in a top-level project design file (for example, top.v), you run the Design Analysis compilation stage to elaborate the design RTL to extract component IP and target device information. Upon launch, Tile Interface Planner initializes and displays this component IP information in the Design Tree view.
2.2.2.2. Step 2: Initialize Tile Interface Planner
The Tile Interface Planner Flow control steps you through the main initialization, planning, and assignment saving functions of the flow in sequence.
2.2.2.3. Step 3: Update Plan with Project Assignments
2.2.2.4. Step 4: Create a Tile Plan
Recommended Two-Stage Tile IP Placement
Handle IP tile placement in two stages for the most efficiency:
| Tile IP Placement | Description |
|---|---|
| Stage 1 |
|
| Stage 2 |
|
2.2.2.4.1. Placing IP Components
-
Use any of the following methods to locate legal tile placements for component
IP:
- In the Design Element list, right-click the
tile interface IP that you want to place, and then click Generate Legal
Locations for Selected Element. Note: You can select multiple IP targeting the same tile to generate legal locations for all IP at once.
- Click the button next to the Design Element to display a list of Legal Locations.
Figure 34. Listing Legal Locations for Tile Placement - In the Design Element list, right-click the
tile interface IP that you want to place, and then click Generate Legal
Locations for Selected Element.
2.2.2.4.2. Constraining IP Building Blocks
When you place component IP, Tile Interface Planner also places the corresponding IP building blocks in the tile. Each building block has a movable, fixed, or always movable state. You can review the building block placement and determine whether to refine any building block placement, or allow the legality engine to determine the best building block placement.
The following building block types are present:
- Movable building blocks—building blocks are initially movable. Movable building blocks can be re-placed by the legality engine in potentially one of several legal locations to accommodate other building blocks. You can convert a movable building block to fixed by specifying a fixed placement location. The legality engine cannot change the placement of fixed building blocks. Movable building block placements appear in italic text in the Design Tree view. Movable building blocks have a dithered fill in Chip View
- Fixed building blocks—building blocks that you place in a fixed, legal location that the legality engine cannot change. You can convert a movable building block to fixed, and a fixed building block to movable. Fixed building block placements appear in plain text in the Design Tree view. Fixed building blocks have a solid fill In the Chip View.
- Always movable building blocks—building blocks that are always movable by the legality engine and cannot be fixed. These building blocks must remain movable to prevent inadvertent conflicting constraints. Always movable building blocks appear in gray italic text in the Design Tree view.
Tooltips in the placement column indicate the movable, fixed, and always-movable state of the design element.
In general, use movable building block placement to allow placement flexibility. Only apply fixed building blocks if a specific building block placement is essential.
2.2.2.5. Step 5: Save Tile Plan Assignments
The Compiler reads the .qsf assignments during the Logic Generation stage. The .json allows you to reload the same tile plan in Tile Interface Planner.
2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
2.2.3. Tile Interface Planner GUI Reference
2.2.3.1. Flow Controls
| Command | Description |
|---|---|
| Initialize Tile Interface Planner | Launches the placement legality engine and loads the component IP and target device data that Design Analysis extracts. |
| View Assignments | Opens the Assignments tab, which allows you to review and enable or disable any existing placement assignments for the current planning session. |
| Update Plan | Optionally applies a previous tile planning session fixed placement assignments from the .qsf, and movable placements from a .json to the current tile interface plan. |
| Plan Design | Opens the Plan tab for placing component IP in the tile interface plan. |
| Save Assignments | Opens the Save Assignments dialog box for saving the fixed tile constraints to the project .qsf and the movable building block constraints to a .json file. |
2.2.3.2. Home Tab
2.2.3.3. Assignments Tab Controls
You can enable or disable any placement assignments that Design Analysis finds. After you are satisfied with the status of all project assignments, click Update Plan on the Flow control to update your tile interface plan with the enabled project assignments.
| Command | Description |
|---|---|
| Filter field | Supports creation of wildcard expressions for assignment targets. Enabled and Disabled buttons filter only enabled or disabled assignments in the list. |
| Enable All Project Assignments | Enables all existing assignments for the current tile interface planning session. |
| Disable All Project Assignments | Disables all existing assignments for the current tile interface planning session. |
| Clear | Clears any filter from the Assignments list. |
| Plan Assignment Options |
|
2.2.3.4. Plan Tab Controls
Click Plan Design on the Flow control to display the Plan tab.
| Command | Description |
|---|---|
|
|
Lists legal locations for placement in the Legal Locations pane. |
| Unplace All | Unplaces all placed design elements in the interface plan. |
| Chip View | Displays the target device chip. Zoom in to display chip details. |
| Package View | Displays the target device package. Zoom in to display chip details. |
| Birdseye View | Displays the target device chip or package view from at maximum Zoom Out. |
| Reset Plan | Unplaces all placed design elements and removes applied project assignments from the tile interface plan. |
| Zoom In and Zoom Out | Increases or decreases the magnification of the tile view to show more or less detail. |
| Fit in Window | Increases or decreases the magnification of the tile view to fit in the current window. |
2.2.3.4.1. Design Tree and Filters
The Design Tree view includes these columns:
- Design Element—lists all component IP and building blocks that Design Analysis identifies. IP cores and building blocks are distinguished by different icons. Fixed IP building blocks are shown in plain text. Movable IP building blocks are shown in italic text. Always movable building blocks are shown in gray italic text.
- Highlight—indicates the color for display of design elements in the tile visualization pane.
- Placement—indicates the placement status (placed, unplaced) or placement tile location for design elements.
You can type a partial or complete name in the design element filter field to refine the list of elements displayed.
- Click the Full icon to show all design elements in the tree.
- Click the IP icon to show only IP level hierarchy in the tree.
- Click the Unplaced icon to show only unplaced design elements in the tree.
- Click the I/Os icon to show only I/O design elements in the tree.
2.2.3.4.2. Legal Locations Pane
- Click any legal location in the list to highlight that location in the tile visualization pane.
- Double-click any legal location in the list to assign placement to that tile location.
2.2.3.5. Tcl Console Window
2.3. Interface Planning Revision History
| Document Version | Intel Quartus Prime Version | Changes |
|---|---|---|
| 2021.06.21 | 21.2 |
|
| 2019.04.01 | 19.1.0 |
|
| 2018.05.07 | 18.0.0 |
|
| 2017.11.06 | 17.1.0 |
|
| 2016.10.31 | 16.1.0 |
|
| 2016.05.03 | 16.0.0 |
|
| 2015.11.02 | 15.1.0 |
|
| 2015.05.04 | 15.0.0 | Second beta release of document on Molson. Added information about the following subjects:
|
| 2014.12.15 | 14.1. | First beta release of document on Molson. |
3. Managing Device I/O Pins
This chapter describes efficient planning and assignment of I/O pins in your target device. Consider I/O standards, pin placement rules, and your PCB characteristics early in the design phase.
|
I/O Planning Task |
Click to Access |
|---|---|
| Plan interfaces and device periphery | |
|
Edit, validate, or export pin assignments |
For more information about special pin assignment features for the Intel® Arria® 10 SoC devices, refer to Instantiating the HPS Component in the Intel® Arria® 10 Hard Processor System Technical Reference Manual.
3.1. I/O Planning Overview
You can plan your I/O pins even before defining design files. Assign expected nodes not yet defined in design files, including interface IP core signals, and then generate a top-level file. The top-level file instantiates the next level of design hierarchy and includes interface port information like memory, high-speed I/O, device configuration, and debugging tools.
Assign design elements, I/O standards, interface IP, and other properties to the device I/O pins by name or by dragging to cells. You can then generate a top-level design file for I/O validation.
Use I/O assignment validation to fully analyze I/O pins against VCCIO, VREF, electromigration (current density), Simultaneous Switching Output (SSO), drive strength, I/O standard, PCI_IO clamp diode, and I/O pin direction compatibility rules.
Intel® Quartus® Prime software provides the Pin Planner tool to view, assign, and validate device I/O pin logic and properties. Alternatively, you can enter I/O assignments in a Tcl script, or directly in HDL code.
3.1.1. Basic I/O Planning Flow
- Click and select a target device that meets your logic, performance, and I/O requirements. Consider and specify I/O standards, voltage and power supply requirements, and available I/O pins.
- Click .
- Assign I/O properties to match your device and PCB characteristics, including assigning logic, I/O standards, output loading, slew rate, and current strength.
- Click Run I/O Assignment Analysis in the Tasks pane to validate assignments and generate a synthesized design netlist. Correct any problems reported.
- Click . During compilation, the Intel® Quartus® Prime software runs I/O assignment analysis.
3.1.2. Integrating PCB Design Tools
The Intel® Quartus® Prime software integrates with board layout tools by allowing import and export of pin assignment information in Intel® Quartus® Prime Settings Files (.qsf) or Pin-Out Files (.pin).
|
PCB Tool Integration |
Supported PCB Tool |
|---|---|
|
Define and validate I/O assignments in the Pin Planner, and then export the assignments to the PCB tool for validation |
Cadence Allegro |
|
Define I/O assignments in your PCB tool, and then import the assignments into the Pin Planner for validation |
Cadence Allegro |
3.1.3. Intel Device Terms
The following terms describe Intel device and I/O structures:
3.2. Assigning I/O Pins
To assign I/O pins in the Pin Planner, follow these steps:
- Open an Intel® Quartus® Prime project, and then click .
- Click to elaborate the design and display All Pins in the device view.
- To locate or highlight pins for assignment, click Pin Finder or a pin type under Highlight Pins in the Tasks pane.
- (Optional) To define a custom group of nodes for assignment, select one or more nodes in the Groups or All Pins list, and click Create Group.
- Enter assignments of logic, I/O standards, interface IP, and properties for device I/O pins in the All Pins spreadsheet, or by dragging into the package view.
- To assign properties to differential pin pairs, click Show Differential Pin Pair Connections. A red connection line appears between positive (p) and negative (n) differential pins.
-
(Optional) To create board trace model assignments:
- Right-click an output or bidirectional pin, and click Board Trace Model. For differential I/O standards, the board trace model uses a differential pin pair with two symmetrical board trace models.
- Specify board trace parameters on the positive end of the differential pin pair. The assignment applies to the corresponding value on the negative end of the differential pin pair.
- To run a full I/O assignment analysis, click Run I/O Assignment Analysis. The Fitter reports analysis results. Only reserved pins are analyzed prior to design synthesis.
3.2.1. Assigning to Exclusive Pin Groups
You can designate groups of pins for exclusive assignment. When you assign pins to an Exclusive I/O Group, the Fitter does not place the signals in the same I/O bank with any other exclusive I/O group. For example, if you have a set of signals assigned exclusively to group_a, and another set of signals assigned to group_b, the Fitter ensures placement of each group in different I/O banks.
3.2.2. Assigning Slew Rate and Drive Strength
You can designate the device pin slew rate and drive strength. These properties affect the pin’s outgoing signal integrity. Use either the Slew Rate or Slow Slew Rate assignment to adjust the drive strength of a pin with the Current Strength assignment.
3.2.3. Assigning Differential Pins
When you assign a differential I/O standard to a single-ended top-level pin in your design, the Pin Planner automatically recognizes the negative pin as part of the differential pin pair assignment and creates the negative pin for you. The Intel® Quartus® Prime software writes the location assignment for the negative pin to the .qsf; however, the I/O standard assignment is not added to the .qsf for the negative pin of the differential pair.
The following example shows a design with lvds_in top-level pin, to which you assign a differential I/O standard. The Pin Planner automatically creates the differential pin, lvds_in(n) to complete the differential pin pair.
If your design contains a large bus that exceeds the pins available in a particular I/O bank, you can use edge location assignments to place the bus. Edge location assignments improve the circuit board routing ability of large buses, because they are close together near an edge. The following figure shows Intel device package edges.
3.2.3.1. Overriding I/O Placement Rules on Differential Pins
I/O placement rules ensure that noisy signals do not corrupt neighboring signals. Each device family has predefined I/O placement rules.
I/O placement rules define, for example, the allowed placement of single-ended I/O with respect to differential pins, or how many output and bidirectional pins you can place within a VREF group when using voltage referenced input standards.
Use the IO_MAXIMUM_TOGGLE_RATE assignment to override I/O placement rules on pins, such as system reset pins that do not switch during normal design activity. Setting a value of 0 MHz for this assignment causes the Fitter to recognize the pin at a DC state throughout device operation. The Fitter excludes the assigned pin from placement rule analysis. Do not assign an IO_MAXIMUM_TOGGLE_RATE of 0 MHz to any actively switching pin, or your design may not function as you intend.
3.2.4. Entering Pin Assignments with Tcl Commands
You can apply pin assignments with Tcl scripts, by either entering individual Tcl commands in the Tcl Console, or creating a .tcl script and the typing the following in the command line:
Applying Tcl Script Assignments
quartus_sh -t <my_tcl_script>.tcl
Scripted Pin Assignment
The following example uses set_location_assignment and set_instance_assignment Tcl commands to assign a pin to a specific location, I/O standard, and drive strength.
set_location_assignment PIN M20 -to address[10] set_instance_assignment -name IO_STANDARD "2.5 V" -to address[10] set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to address[10]
3.2.5. Entering Pin Assignments in HDL Code
You can use synthesis attributes or low‑level I/O primitives to embed I/O pin assignments directly in your HDL code. When you analyze and synthesize the HDL code, the information is converted into the appropriate I/O pin assignments. You can use either of the following methods to specify pin‑related assignments with HDL code:
- Assigning synthesis attributes for signal names that are top‑level pins
- Using low‑level I/O primitives, such as ALT_BUF_IN, to specify input, output, and differential buffers, and for setting parameters or attributes
3.2.5.1. Using Low-Level I/O Primitives
You can alternatively enter I/O pin assignments using low-level I/O primitives. You can assign pin locations, I/O standards, drive strengths, slew rates, and on-chip termination (OCT) value assignments. You can also use low-level differential I/O primitives to define both positive and negative pins of a differential pair in the HDL code for your design.
Primitive-based assignments do not appear in the Pin Planner until after you perform a full compilation and back-annotate pin assignments (Assignments > Back Annotate Assignments).
3.3. Importing and Exporting I/O Pin Assignments
The Intel® Quartus® Prime software supports transfer of I/O pin assignments across projects, or for analysis in third-party PCB tools. You can import or export I/O pin assignments in the following ways:
|
Import Assignments |
Export Assignments |
|
|---|---|---|
|
Scenario |
|
|
|
Command |
|
|
|
File formats |
.qsf, .esf, .acf, .csv, .txt,.sdc |
.pin, .csv, .tcl, .qsf |
|
Notes |
N/A |
Exported .csv files retain column and row order and format. Do not modify the row of column headings if importing the .csv file |
3.3.1. Importing and Exporting for PCB Tools
The Pin Planner supports import and export of assignments with PCB tools. You can export valid assignments as a .pin file for analysis in other supported PCB tools. You can also import optimized assignment from supported PCB tools. The .pin file contains pin name, number, and detailed properties.
|
File Column Name |
Description |
|---|---|
|
Pin Name/Usage |
The name of the design pin, or whether the pin is GND or VCC pin |
|
Location |
The pin number of the location on the device package |
|
Dir |
The direction of the pin |
|
I/O Standard |
The name of the I/O standard to which the pin is configured |
|
Voltage |
The voltage level that is required to be connected to the pin |
|
I/O Bank |
The I/O bank to which the pin belongs |
|
User Assignment |
Y or N indicating if the location assignment for the design pin was user assigned (Y) or assigned by the Fitter (N) |
3.3.2. Migrating Assignments to Another Target Device
You can migrate compatible pin assignments from one target device to another. You can migrate to a different density and the same device package. You can also migrate between device packages with different densities and pin counts.
The Intel® Quartus® Prime software ignores invalid assignments and generates an error message during compilation. After evaluating migration compatibility, modify any incompatible assignments, and then click Export to export the assignments to another project.
The migration result for the pin function of highlighted PIN_AC23 is not an NC but a voltage reference VREFB1N2 even though the pin is an NC in the migration device. VREF standards have a higher priority than an NC, thus the migration result displays the voltage reference. Even if you do not use that pin for a port connection in the design, you must use the VREF standard for I/O standards that require it on the actual board for the migration device.
If one of the migration devices has pins intended for connection to VCC or GND and these same pins are I/O pins on a different device in the migration path, the Intel® Quartus® Prime software ensures these pins are not used for I/O. Ensure that these pins are connected to the correct PCB plane.
When migrating between two devices in the same package, pins that are not connected to the smaller die may be intended to connect to VCC or GND on the larger die. To facilitate migration, you can connect these pins to VCC or GND in the original design because the pins are not physically connected to the smaller die.
3.4. Validating Pin Assignments
The Intel® Quartus® Prime software validates I/O pin assignments against predefined I/O rules for your target device. You can use the following tools to validate your I/O pin assignments throughout the pin planning process:
|
I/O Validation Tool |
Description |
Click to Run |
|---|---|---|
|
Advanced I/O Timing |
Fully validates I/O assignments against all I/O and timing checks during compilation |
|
3.4.1. I/O Assignment Validation Rules
I/O Assignment Analysis validates your assignments against the following rules:
| Rule | Description | HDL Required? |
|---|---|---|
|
I/O bank capacity |
Checks the number of pins assigned to an I/O bank against the number of pins allowed in the I/O bank. |
No |
|
I/O bank VCCIO voltage compatibility |
Checks that no more than one VCCIO is required for the pins assigned to the I/O bank. |
No |
|
I/O bank VREF voltage compatibility |
Checks that no more than one VREF is required for the pins assigned to the I/O bank. |
No |
|
I/O standard and location conflicts |
Checks whether the pin location supports the assigned I/O standard. |
No |
|
I/O standard and signal direction conflicts |
Checks whether the pin location supports the assigned I/O standard and direction. For example, certain I/O standards on a particular pin location can only support output pins. |
No |
|
Differential I/O standards cannot have open drain turned on |
Checks that open drain is turned off for all pins with a differential I/O standard. |
No |
|
I/O standard and drive strength conflicts |
Checks whether the drive strength assignments are within the specifications of the I/O standard. |
No |
|
Drive strength and location conflicts |
Checks whether the pin location supports the assigned drive strength. |
No |
|
BUSHOLD and location conflicts |
Checks whether the pin location supports BUSHOLD. For example, dedicated clock pins do not support BUSHOLD. |
No |
|
WEAK_PULLUP and location conflicts |
Checks whether the pin location supports WEAK_PULLUP (for example, dedicated clock pins do not support WEAK_PULLUP). |
No |
|
Electromigration check |
Checks whether combined drive strength of consecutive pads exceeds a certain limit. For example, the total current drive for 10 consecutive pads on a Stratix® II device cannot exceed 200 mA. |
No |
|
PCI_IO clamp diode, location, and I/O standard conflicts |
Checks whether the pin location along with the I/O standard assigned supports PCI_IO clamp diode. |
No |
|
SERDES and I/O pin location compatibility check |
Checks that all pins connected to a SERDES in your design are assigned to dedicated SERDES pin locations. |
Yes |
|
PLL and I/O pin location compatibility check |
Checks whether pins connected to a PLL are assigned to the dedicated PLL pin locations. |
Yes |
| Rule | Description | HDL Required? |
|---|---|---|
|
I/O bank cannot have single-ended I/O when DPA exists |
Checks that no single-ended I/O pin exists in the same I/O bank as a DPA. |
No |
|
A PLL I/O bank does not support both a single-ended I/O and a differential signal simultaneously |
Checks that there are no single-ended I/O pins present in the PLL I/O Bank when a differential signal exists. |
No |
|
Single-ended output is required to be a certain distance away from a differential I/O pin |
Checks whether single-ended output pins are a certain distance away from a differential I/O pin. |
No |
|
Single-ended output must be a certain distance away from a VREF pad |
Checks whether single-ended output pins are a certain distance away from a VREF pad. |
No |
|
Single-ended input is required to be a certain distance away from a differential I/O pin |
Checks whether single-ended input pins are a certain distance away from a differential I/O pin. |
No |
|
Too many outputs or bidirectional pins in a VREFGROUP when a VREF is used |
Checks that there are no more than a certain number of outputs or bidirectional pins in a VREFGROUP when a VREF is used. |
No |
|
Too many outputs in a VREFGROUP |
Checks whether too many outputs are in a VREFGROUP. |
No |
3.4.2. I/O Assignment Analysis
I/O assignment analysis validates I/O assignments against the complete set of I/O system and board layout rules. Full I/O assignment analysis validates blocks that directly feed or are fed by resources such as a PLL, LVDS, or gigabit transceiver blocks. In addition, the checker validates the legality of proper VREF pin use, pin locations, and acceptable mixed I/O standards
Run I/O assignment analysis during early pin planning to validate initial reserved pin assignments before compilation. Once you define design files, run I/O assignment analysis to perform more thorough legality checks with respect to the synthesized netlist. Run I/O assignment analysis whenever you modify I/O assignments.
The Fitter assigns pins to accommodate your constraints. For example, if you assign an edge location to a group of LVDS pins, the Fitter assigns pin locations for each LVDS pin in the specified edge location and then performs legality checks. To display the Fitter-placed pins, click Show Fitter Placements in the Pin Planner. To accept these suggested pin locations, you must back-annotate your pin assignments.
View the I/O Assignment Warnings report to view and resolve all assignment warnings. For example, a warning that some design pins have undefined drive strength or slew rate. The Fitter recognizes undefined, single-ended output and bidirectional pins as non-calibrated OCT. To resolve the warning, assign the Current Strength, Slew Rate or Slow Slew Rate for the reported pin. Alternatively, can assign the Termination to the pin. You cannot assign drive strength or slew rate settings when a pin has an OCT assignment.
3.4.2.1. Early I/O Assignment Analysis Without Design Files
You can perform basic I/O legality checks before defining HDL design files. This technique produces a preliminary board layout. For example, you can specify a target device and enter pin assignments that correspond to PCB characteristics. You can reserve and assign I/O standards to each pin, and then run I/O assignment analysis to ensure that there are no I/O standard conflicts in each I/O bank.
You must reserve all pins you intend to use as I/O pins, so that the Fitter can determine each pin type. After performing I/O assignment analysis, correct any errors reported by the Fitter and rerun I/O assignment analysis until all errors are corrected. A complete I/O assignment analysis requires all design files.
3.4.2.2. I/O Assignment Analysis With Design Files
I/O assignment analysis allows you to perform full I/O legality checks after fully defining HDL design files. When you run I/O assignment analysis on a complete design, the tool verifies all I/O pin assignments against all I/O rules. When you run I/O assignment analysis on a partial design, the tool checks legality only for defined portions of the design. The following figure shows the work flow for analyzing pin-outs with design files.
Even if I/O assignment analysis passes on incomplete design files, you may still encounter errors during full compilation. For example, you can assign a clock to a user I/O pin instead of assigning to a dedicated clock pin, or design the clock to drive a PLL that you have not yet instantiated in the design. This issues occur because I/O assignment analysis does not account for the logic that the pin drives and does not verify that only dedicated clock inputs can drive the a PLL clock port.
To obtain better coverage, analyze as much of the design as possible over time, especially logic that connects to pins. For example, if your design includes PLLs or LVDS blocks, define these files prior to full analysis. After performing I/O assignment analysis, correct any errors reported by the Fitter and rerun I/O assignment analysis until all errors are corrected.
The following figure shows the compilation time benefit of performing I/O assignment analysis before running a full compilation.
3.4.2.3. Overriding Default I/O Pin Analysis
You can override the default I/O analysis of pins to accommodate I/O rule exceptions, such as for analyzing VREF or inactive pins.
Each device contains VREF pins, each supporting one or more I/O pins. A VREF pin and its I/O pins comprise a VREF bank. The VREF pins are typically assigned inputs with VREF I/O standards, such as HSTL- and SSTL-type I/O standards. Conversely, VREF outputs do not require the VREF pin. When a voltage-referenced input is present in a VREF bank, only a certain number of outputs can be present in that VREF bank. I/O assignment analysis treats bidirectional signals controlled by different output enables as independent output enables.
To assign the Output Enable Group option to bidirectional signals to analyze the signals as a single output enable group, follow these steps:
- To access this assignment in the Pin Planner, right-click the All pins list and click Customize Columns.
- Under Available columns, add Output Enable Group to Show these columns in this order. The column appears in the All Pins list.
- Enter the same integer value for the Output Enable Group assignment for all sets of signals that are driving in the same direction.
3.4.3. Understanding I/O Analysis Reports
The detailed I/O assignment analysis reports include the affected pin name and a problem description. The Fitter section of the Compilation report contains information generated during I/O assignment analysis, including the following reports:
- I/O Assignment Warnings—lists warnings generated for each pin
- Resource Section—quantifies use of various pin types and I/O banks
- I/O Rules Section—lists summary, details, and matrix information about the I/O rules tested
The Status column indicates whether rules passed, failed, or were not checked. A severity rating indicates the rule’s importance for effective analysis. “Inapplicable” rules do not apply to the target device family.
3.5. Verifying I/O Timing
For example, if you change the slew rates or drive strengths of some I/O pins with ECOs, you can verify timing without recompiling the design. You must understand I/O timing and what factors affect I/O timing paths in your design. The accuracy of the output load specification of the output and bidirectional pins affects the I/O timing results.
The Intel® Quartus® Prime software supports three different methods of I/O timing analysis:
|
I/O Timing Analysis |
Description |
|---|---|
|
Advanced I/O timing analysis |
Analyze I/O timing with your board trace model to report accurate, “board-aware” simulation models. Configures a complete board trace model for each I/O standard or pin. Timing Analyzer applies simulation results of the I/O buffer, package, and board trace model to generate accurate I/O delays and system level signal information. Use this information to improve timing and signal integrity. |
|
I/O timing analysis |
Analyze I/O timing with default or specified capacitive load without signal integrity analysis. Timing Analyzer reports tCO to an I/O pin using a default or user-specified value for a capacitive load. |
|
Full board routing simulation |
Use Intel-provided or Intel® Quartus® Prime software-generated IBIS or HSPICE I/O models for simulation in Mentor Graphics* HyperLynx* and Synopsys* HSPICE. |
For more information about advanced I/O timing support, refer to the appropriate device handbook for your target device. For more information about board-level signal integrity and tips on how to improve signal integrity in your high-speed designs, refer to the Signal Integrity and Power Integrity – Support Center website.
For information about creating IBIS and HSPICE models with the Intel® Quartus® Prime software and integrating those models into HyperLynx* and HSPICE simulations, refer to the Signal Integrity Analysis with Third Party Tools chapter.
3.5.1. Running Advanced I/O Timing
Advanced I/O timing analysis uses your board trace model and termination network specification to report accurate output buffer-to-pin timing estimates, FPGA pin and board trace signal integrity and delay values. Advanced I/O timing runs automatically for supported devices during compilation.
3.5.1.1. Board Trace Models
The Intel® Quartus® Prime software provides board trace model templates for various I/O standards.
The following figure shows the template for a 2.5 V I/O standard. This model consists of near-end and far-end board component parameters.
Near-end board trace modeling includes the elements which are close to the device. Far-end modeling includes the elements which are at the receiver end of the link, closer to the receiving device. Board trace model topology is conceptual and does not necessarily match the actual board trace for every component. For example, near-end model parameters can represent device-end discrete termination and breakout traces. Far-end modeling can represent the bulk of the board trace to discrete external memory components, and the far end termination network. You can analyze the same circuit with near-end modeling of the entire board, including memory component termination, and far-end modeling of the actual memory component.
The following figure shows the template for the LVDS I/O standard. The far-end capacitance (Cf) represents the external-device or multiple-device capacitive load. If you have multiple devices on the far-end, you must find the equivalent capacitance at the far-end, taking into account all receiver capacitances. The far-end capacitance can be the sum of all the receiver capacitances.
The Intel® Quartus® Prime software models of transmission lines do not consider transmission-line resistance (lossless models). You only need to specify distributed inductance (L) and capacitance (C) values on a per-inch basis, which you can obtain from the PCB vendor or manufacturer, the CAD Design tool, or a signal integrity tool, such as the Mentor Graphics* HyperLynx* software.
3.5.1.2. Defining the Board Trace Model
Advanced I/O Timing uses the model to simulate the output signal from the output buffer to the far end of the board trace. You can define the capacitive load, any termination components, and trace impedances in the board routing for any output pin or bidirectional pin in output mode. You can configure an overall board trace model for each I/O standard or for specific pins. Define an overall board trace model for each I/O standard in your design. Use that model for all pins that use the I/O standard. You can customize the model for specific pins using the Board Trace Model window in the Pin Planner.
- Click .
- Click Board Trace Model and define board trace model values for each I/O standard.
- Click I/O Timing and define default I/O timing options at board trace near and far ends.
- Click and assign board trace model values to individual pins.
Specifying Board Trace Model
## setting the near end series resistance model of sel_p output pin to 25 ohms set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R 25 -to se1_p ## Setting the far end capacitance model for sel_p output signal to 6 picofarads set_instance_assignment -name BOARD_MODEL_FAR_C 6P -to se1_p
3.5.1.3. Modifying the Board Trace Model
You can modify any of the board trace model parameters within a graphical representation of the board trace model.
The Board Trace Model window displays the routing and components for positive and negative signals in a differential signal pair. Only modify the positive signal of the pair, as the setting automatically applies to the negative signal. Use standard unit prefixes such as p, n, and k to represent pico, nano, and kilo, respectively. Use the short or open value to designate a short or open circuit for a parallel component.
3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis
You can select a near-end or far-end point for I/O timing analysis. Near-end timing analysis extends to the device pin. You can apply the set_output_delay constraint during near-end analysis to account for the delay across the board.
With far-end I/O timing analysis, the advanced I/O timing analysis extends to the external device input, at the far-end of the board trace. Whether you choose a near-end or far-end timing endpoint, the board trace models are taken into account during timing analysis.
3.5.1.5. Advanced I/O Timing Analysis Reports
The following reports show advanced I/O timing analysis information:
| I/O Timing Report | Description |
|---|---|
| Timing Analyzer Report | Reports signal integrity and board delay data. |
| Board Trace Model Assignments report | Summarizes the board trace model component settings for each output and bidirectional signal. |
| Signal Integrity Metrics report | Contains all the signal integrity metrics calculated during advanced I/O timing analysis based on the board trace model settings for each output or bidirectional pin. Includes measurements at both the FPGA pin and at the far-end load of board delay, steady state voltages, and rise and fall times. |
3.5.2. Adjusting I/O Timing and Power with Capacitive Loading
When calculating tCO and power for output and bidirectional pins, the Timing Analyzer and the Power Analyzer use a bulk capacitive load. You can adjust the value of the capacitive load per I/O standard to obtain more precise tCO and power measurements, reflecting the behavior of the output or bidirectional net on your PCB. The Intel® Quartus® Prime software ignores capacitive load settings on input pins. You can adjust the capacitive load settings per I/O standard, in picofarads (pF), for your entire design. During compilation, the Compiler measures power and tCO measurements based on your settings. You can also adjust the capacitive load on an individual pin with the Output Pin Load logic option.
3.6. Viewing Routing and Timing Delays
Right-click any node and click Locate > Locate in Chip Planner to visualize and adjust I/O timing delays and routing between user I/O pads and VCC, GND, and VREF pads. The Chip Planner graphically displays logic placement, Logic Lock regions, relative resource usage, detailed routing information, fan-in and fan-out, register paths, and high-speed transceiver channels. You can view physical timing estimates, routing congestion, and clock regions. Use the Chip Planner to change connections between resources and make post-compilation changes to logic cell and I/O atom placement. When you select items in the Pin Planner, the corresponding item is highlighted in Chip Planner.
3.7. Scripting API
The Intel® Quartus® Prime software allows you to access I/O management functions through Tcl commands, rather than with the GUI. For detailed information about scripting command options and Tcl API packages, type the following at a system command prompt to view the Tcl API Help browser:
quartus_sh --qhelp
3.7.1. Generate Mapped Netlist
Enter the following in the Tcl console or in a Tcl script:
execute_module -tool map
The execute_module command is in the flow package.
Type the following at a system command prompt:
quartus_syn <project name>
3.7.2. Reserve Pins
Use the following Tcl command to reserve a pin:
set_instance_assignment -name RESERVE_PIN <value> -to <signal name>
Use one of the following valid reserved pin values:
- "AS BIDIRECTIONAL"
- "AS INPUT TRI STATED"
- "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
- "AS OUTPUT DRIVING GROUND"
- "AS SIGNALPROBE OUTPUT"
3.7.3. Set Location
Use the following Tcl command to assign a signal to a pin or device location:
set_location_assignment <location> -to <signal name>
Valid locations are pin locations, I/O bank locations, or edge locations. Pin locations include pin names, such as PIN_A3. I/O bank locations include IOBANK_1 up to IOBANK_ n, where n is the number of I/O banks in the device.
Use one of the following valid edge location values:
- EDGE_BOTTOM
- EDGE_LEFT
- EDGE_TOP
- EDGE_RIGHT
3.7.4. Exclusive I/O Group
The following Tcl command creates an exclusive I/O group assignment:
set_instance_assignment -name "EXCLUSIVE_IO_GROUP" -to pin
3.7.5. Slew Rate and Current Strength
Use the following Tcl commands to create a slew rate and drive strength assignments:
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to e[0] set_instance_assignment -name SLEW_RATE 2 -to e[0]
3.8. Managing Device I/O Pins Revision History
The following table shows the revision history for this chapter:
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2020.11.04 | 19.3 | Removed references to obsolete FPGA Xchange file (.fx) support from "Integrating PCB Design Tools" and "Importing and Exporting I/O Pin Assignments" topics. |
| 2018.05.07 | 18.0 |
|
| 2017.11.06 | 17.1 |
|
| 2017.05.08 | 17.0 |
|
| 2016.10.31 | 16.1 |
|
| 2015.11.02 | 15.1 |
|
| 2014.12.15 | 14.1 |
|
| 2014.08.30 | 14.0a10 |
|
| 2014.06.30 | 14.0 |
|
| November 2013 | 13.1 |
|
| May 2013 | 13.0 |
|
| November 2012 | 12.1 |
|
| June 2012 | 12.0.0 |
|
| November 2011 | 11.1 |
|
| December 2010 | 10.0 | Template update |
| July 2010 | 10.0 |
|
| November 2009 | 9.1 |
|
| March 2009 | 9.0 |
|
A. Intel Quartus Prime Pro Edition User Guides
Refer to the following user guides for comprehensive information on all phases of the Intel® Quartus® Prime Pro Edition FPGA design flow.