• 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY Release Notes
• 10-Gbps Ethernet (10GbE) MAC IP Core Release Notes
• 1G/2.5G/10G Multi-rate Ethernet PHY Release Notes
• 10GBASE-R PHY IP Core Release Notes
• 25G Ethernet IP Core Release Notes
• 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes
• 50G Ethernet IP Core Release Notes
• 50G Interlaken IP Core Release Notes
• 100G Interlaken IP Core Release Notes
• Advanced SEU Detection Intel FPGA IP Core Release Notes
• Arria V GZ Hard IP for PCI Express IP Core Release Notes
• Arria V Hard IP for PCI Express IP Core Release Notes
• Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes
• Intel Arria 10 External Memory Interface IP Core Release Notes
• Arria 10 FPLL IP Core Release Notes
• Intel Arria 10 and Intel Cyclone 10 Hard IP for PCI Express IP Core Release Notes
• Arria 10 Transceiver ATX PLL IP Core Release Notes
• Arria 10 Transceiver CMU PLL IP Core Release Notes
• Arria 10 Transceiver Native PHY IP Core Release Notes
• ASMI Parallel II Core Release Notes
• BCH IP Core Release Notes
• CIC IP Core Release Notes
• Clock Control Intel Stratix 10 FPGA IP Core Release Notes
• CPRI IP Core Release Notes
• Cyclone V Hard IP for PCI Express IP Core Release Notes
• DDR2 and DDR3 SDRAM Controller with UniPHY IP Core Release Notes
• Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT IP Core Release Notes
• eSRAM IP Core Release Notes
• Intel FPGA DisplayPort IP Core Release Notes
• FIFO IP Core Release Notes
• FIFO2 IP Core Release Notes
• FIR II IP Core Release Notes
• FFT IP Core Release Notes
• Intel FPGA HDMI IP Core Release Notes
• High-speed Reed-Solomon IP Core Release Notes
• Hybrid Memory Cube Controller IP Core Release Notes
• Intel^® Stratix^® 10 H-Tile Hard IP for Ethernet IP Core Release Notes
• Intel^® Stratix^® 10 Hard IP for PCI Express* IP Core Release Notes
• Intel^® Stratix^® 10 Low Latency 40-Gbps Ethernet IP Core Release Notes
• Low Latency 100G Ethernet Intel^® Stratix^® 10 FPGA IP Core Release Notes
• Intel^® Stratix^® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Release Notes
• Intel^® Stratix^® 10 10GBASE-KR PHY IP Core Release Notes
• Interlaken IP Core (2nd Generation) Release Notes
• Interlaken PHY IP Core Release Notes
• IP Compiler for PCI Express Release Notes
• IOPLL Intel FPGA IP Core Release Notes
• IOPLL Reconfig Intel FPGA IP Core Release Notes
• JESD204B IP Core Release Notes
• LDPC IP Core Release Notes
• Low Latency 100-Gbps Ethernet IP Core Release Notes
• Low Latency 40-Gbps Ethernet IP Core Release Notes
• Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes
• Low Latency Ethernet 10G MAC IP Core Release Notes
• Native Fixed Point DSP Intel Stratix 10 FPGA IP Core Release Notes
• Native Fixed Point DSP Intel Arria 10 FPGA IP Release Notes
• Native Fixed Point DSP Intel Cyclone 10 FPGA IP Core Release Notes
• Native Floating Point DSP Intel Stratix 10 FPGA IP Core Release Notes
• Native Floating Point DSP Intel Arria 10 FPGA IP Core Release Notes
• Native Floating Point DSP Intel Cyclone 10 FPGA IP Core Release Notes
• Nios II and Embedded IP Release Notes
• NCO IP Core Release Notes
• PHY Lite for Parallel Interfaces Intel FPGA IP Core Release Notes
• QDR II and QDR II+ SRAM Controller with UniPHY IP Core Release Notes
• RapidIO IP Core Release Notes
• RapidIO II IP Core Release Notes
• Reed-Solomon II IP Core Release Notes
• RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core Release Notes
• SDI IP Core Release Notes
• Intel FPGA SDI II IP Core Release Notes
• Intel FPGA SDI Audio IP Cores Release Notes
• SerialLite II Release Notes
• SerialLite III Streaming IP Core Release Notes
• SmartVID Controller IP Core Release Notes
• Stratix V Hard IP for PCI Express IP Core Release Notes
• Triple Speed Ethernet IP Core Release Notes
• Turbo IP Core Release Notes
• Video and Image Processing Suite Release Notes
• Viterbi IP Core Release Notes
• V-Series Avalon-MM DMA for PCI Express IP Core Release Notes
• XAUI PHY Release Notes
• Other IP Cores Release Notes
• Other Transceiver IP Cores Product Release Notes

Errata are functional defects or errors, which may cause the product to deviate from published specifications. Documentation errata include errors, unclear descriptions, or omissions from current published specifications or product documents.

For full information on errata and the versions affected by errata, refer to the Knowledge Base on the Intel FPGA website.