Low Latency Ethernet 10G MAC Intel FPGA IP Release Notes
RN-1122 | 2019.04.24
Low Latency Ethernet 10G MAC Intel FPGA IP Release Notes
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel® Quartus® Prime Design Suite Update Release Notes.
Related Information
Low Latency Ethernet 10G MAC Intel FPGA IP v19.1
| Description | Impact |
|---|---|
| Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel® rebranding in the Intel® Quartus® Prime Pro Edition software. The Intel® Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint. | — |
Low Latency Ethernet 10G MAC Intel FPGA IP v18.1
| Description | Impact |
|---|---|
Added support for the following operation mode for
Intel®
Cyclone® 10 GX devices:
|
— |
Design Example for Low Latency 10G Ethernet MAC
Intel® FPGA IP:
|
— |
Low Latency Ethernet 10G MAC Intel FPGA IP v18.0
| Description | Impact |
|---|---|
| Renamed Low Latency Ethernet 10G MAC IP core to Low Latency Ethernet 10G MAC Intel® FPGA IP core as per Intel rebranding. | — |
Added support for the following operation modes
for
Intel®
Stratix® 10 devices:
|
— |
Added support for the following operation mode for
Intel®
Arria® 10 devices:
|
— |
Added new parameter for LL Ethernet 10G MAC
Intel® FPGA IP:
|
— |
Design Examples for Low Latency 10G Ethernet MAC
Intel® FPGA IP:
|
— |
Related Information
Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Update 1
| Description | Impact |
|---|---|
| 10GBASE-R register mode is now supported in Intel® Stratix® 10 devices. | — |
Related Information
Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1
| Description | Impact |
|---|---|
| Added support for the Intel® Cyclone® 10 GX device family. | This device is only available in Intel® Quartus® Prime software version 17.1 onwards. |
Added support for the following operation modes for
Intel®
Stratix® 10 devices:
|
— |
Added a new feature—Peer-to-Peer:
|
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
| You cannot turn on the Enable ECC on memory blocks parameter with the Enable time stamping parameter. | The IP core may not exhibit the expected behavior when both parameters are turned on at the same time. This is applicable in Intel® Quartus® Prime Pro Edition and Intel® Quartus® Prime Standard Edition version 17.0 and earlier. |
Design Examples for Low Latency 10G Ethernet
MAC:
|
— |
|
In previous versions of the Low Latency Ethernet 10G MAC design example for Intel® Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in Intel® Quartus® Prime version 17.1. |
If you are upgrading designs that have these additional constraints from the previous versions of Intel® Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information. |
| 10GBASE-R register mode is not supported in Intel® Stratix® 10 devices. | — |
Related Information
Low Latency Ethernet 10G MAC IP Core v17.0
| Description | Impact |
|---|---|
Stratix 10 supports for the following operation modes:
|
— |
Design Examples for Low Latency 10G Ethernet MAC:
|
Low Latency Ethernet 10G MAC IP Core v16.1
| Description | Impact |
|---|---|
| Added support for Stratix 10 devices. | — |
Added new parameter for LL Ethernet 10G MAC IP Core:
|
Low Latency Ethernet 10G MAC IP Core v16.0
| Description | Impact |
|---|---|
|
— |
Low Latency Ethernet 10G MAC IP Core v15.1
| Description | Impact |
|---|---|
|
— |
Low Latency Ethernet 10G MAC IP Core v15.0
| Description | Impact |
|---|---|
Added new registers:
|
If you do not upgrade your IP core, it does not have this new feature. |
Low Latency Ethernet 10G MAC IP Core v14.1
| Description | Impact |
|---|---|
Added new parameter options:
|
If you do not upgrade your IP core, it does not have this new feature. |
Added new signals to support 10GBASE-R register
mode:
|
Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition
| Description | Impact |
|---|---|
| Verified in the Quartus II software v14.0 Arria 10 Edition. (Added support for Arria 10 devices). | If you upgrade your IP core to the Quartus II software v14.0 Arria 10 Edition, all of the changes require that you regenerate the IP core manually and reconnect it in your design. |
Low Latency Ethernet 10G MAC IP Core v14.0
| Description | Impact |
|---|---|
| Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. | - |
| Added support for unidirectional feature. | The following changes are optional. If you do not upgrade your IP core, it does not have these new features. |
| Modified the reset behavior—TX and RX reset signals changed from asynchronous reset to synchronous reset. | |
| Resource improvement with no impact to performance. |
Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition
| Description | Impact |
|---|---|
|
Added support for Arria 10 devices. |
- |
Low Latency Ethernet 10G MAC IP Core v13.1
| Description | Impact |
|---|---|
Initial release.
|
- |