Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes
If a release note is not available for a specific IP core version, the IP core has no changes in that version. Information on the latest update releases is in the Quartus Prime Design Suite Update Release Notes.
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v16.0 Revision History
Description | Impact |
---|---|
Verified in Quartus Prime software v16.0 | - |
Made the following changes:
|
- |
Bit | RW | Old Register Name | New Register Name | Description |
---|---|---|---|---|
1 | RW | dis_max_wait_tmr | — | When set to 1, disables the LT max_wait_timer. Used for characterization mode when setting much longer BER timer values. The default value is 0. |
14:12 | RW | equal_cnt [2:0] | — |
Adds hysteresis to the error count to avoid local minimums. The
following values are defined:
The default value is 101. |
21:20 | RW | rx_ctle_vga_mode | dfe_freeze_mode |
Defines the behavior of DFE taps at the end of link training
The default value is 01. Note: These bits will be effective only when bit [19] is set to
0.
|
22 | RW | adp_ctle_vga_mode | — |
Defines whether or not CTLE/VGA adaptation is in adaptive or manual
mode. The following values are defined:
The default value is 0 for hardware. |
31:29 | RW | Manual VGA | — |
Defines the VGA value used by the link training algorithm when in manual VGA mode. These bits are only effective when 0x4D0[22] is set to 1. The default value is 4 for simulation. The default value is 7 for hardware. |
22 | RW | adp_ctle_vga_mode | — |
Defines whether or not CTLE/VGA adaptation is in adaptive or manual
mode. The following values are defined:
The default value is 0 for hardware. |
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.1 Revision History
Description | Impact |
---|---|
Verified in Quartus Prime software v15.1 | - |
Made the following changes:
|
- |
Bit | RW | Old Register Name | New Register Name | Description |
---|---|---|---|---|
12 | RW | N/A | LT failure response | When set to 1, LT failure causes the PHY to go into data mode. When set to 0, LT failure restarts auto-negotiation (if enabled). If auto-negotiation is not enabled, the PHY will restart LT. |
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0.1 Revision History
Description | Impact |
---|---|
Verified in Quartus II software v15.0.1 | - |
Made the following improvements to the
link training (LT) algorithm:
|
- |
Bit | RW | Old Register Name | New Register Name | Description |
---|---|---|---|---|
2 | RW | quick_mode | Reserved | Reserved |
3 | RW | pass_one | Reserved | Reserved |
18 | RW | Ctle_depth | VOD Training Enable |
Defines whether or not to skip adjustment of the link partner’s VOD (main tap) during link training. The following values are defined:
The default value is 0. |
19 | RW | Ctle_depth | Bypass DFE |
Defines whether or not Decision Feedback Equalization (DFE) is enabled at the end of link training. The following values are defined:
The default value for simulation is 1. The default value for hardware is 0. |
21:20 | RW | rx_ctle_mode | rx_ctle_vga_mode |
Defines the point at which to enable the RX CTLE in the adaptation algorithm. The following values are defined:
The default value is 00.
Note: These bits are only effective when 0x4D0[22] is
set to 0.
|
22 | RW | Reserved | adp_ctle_vga_mode |
Defines whether or not CTLE/VGA adaptation is in adaptive or manual mode. The following values are defined:
The default value is 1. |
28:24 | RW | Reserved | Manual CTLE |
Defines the CTLE value used by the link training algorithm when in manual CTLE mode. These bits are only effective when 0x4D0[22] is set to 1. The default value is 1. |
31:29 | RW | max_post_step[2:0] | Manual VGA |
Defines the VGA value used by the link training algorithm when in manual VGA mode. These bits are only effective when 0x4D0[22] is set to 1. The default value is 4. |
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0 Revision History
Description | Impact |
---|---|
When adaptation is enabled, the 10GBASE-KR link training may not finish in the required 500 ms. This results in a Link Training Failure. When this occurs, equalization may not be trained optimally for the link. | You can disable adaptation and use a fixed CTLE value during link training. This is done by setting 0x4D0[22:20] to 4, and 0x4D0[28:24] to the desired CTLE value. |
The 10GBASE-KR register, 0x4d2[0] Link Trained – Receiver status, is read incorrectly as 0 when testing on HW. It will be read back correctly during simulation. | - |
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.1 Revision History
Description | Impact |
---|---|
Verified in Quartus II software v14.1 | - |
The Quartus II software v14.1 requires that you specify a device if your IP core targets the Arria 10 device family. If you do not specify your target Arria 10 device, the IP Upgrade tool insists that your IP core requires upgrade but does not clarify the reason. | You must ensure that you specify a device for your v13.1 Arria 10 Edition or v14.0 Arria 10 Edition IP core variation and regenerate it in the Quartus II software v14.1. |
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.0 Revision History
Description | Impact |
---|---|
Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. | - |
Removed the following parameters from the
Link Training tab:
|
- |
Changed the default values of the following PMA
parameters under the
Link Training tab:
|
- |
Changed Avalon Memory-Mapped (AVMM) clock frequency from 125 MHz to 161 MHz to support NIOS II. The AVMM slave interface provides access to the IP core registers. | - |
IEEE 1588 Precision Time Protocols are not supported in backplane applications. | - |
Link Training takes more time in simulation as NIOS command processing is slower. | - |
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v13.1 Revision History
Description | Impact |
---|---|
Initial release | - |