If a release note is not available for a specific IP core
version, the IP core has no changes in that version. Information on the latest update
releases is in the Intel Quartus Prime Design Suite Update Release
Added new Enable
Native XCVR PHY ADME
for Arria 10 variations..
the IP core to incorporate this feature is optional. This change does
not affect the top-level signals of the IP
parameter exposes control of transceiver configuration
Changed behavior of irx_err signal. Previously, if the IP
core could not determine the burst in which the error occurred, it
asserted the irx_err signal anyway,
and the client could also not determine the associated burst. Now, if
the IP core cannot determine the burst in which an error occurred, it
does not assert the irx_err signal.
If it can determine the burst in which an error occurred, it asserts the
irx_err signal during the end of
burst cycle (when it also asserts irx_eob).
This change ensures that apparent
errors that occur during Idle cycles do not cause the irx_err signal to assert.
Upgrading the IP core to incorporate this feature
is optional. If you upgrade your IP core you should be aware of the
change in signal behavior.
Refer to 100G Interlaken IP Core
Signal Changes v15.1 table.
Added hardware design example for
Arria 10 variations.
A hardware design example is now
available with tArria 10 variations of the 100G Interlaken IP core.
Modified instructions to generate
Table 3. 100G Interlaken IP Core Signal Changes v15.1. Signals added or modified in version 15.1.
Old Signal Name
New Signal Name
Changed behavior of irx_err signal. The IP core asserts the
signal in a subset of the cases in which it asserted this signal in the
previous release, and always asserts this signal synchronously with the
irx_eob signal of the burst in
which the error occurred.
This feature adds support for modification of the TX
scrambler seed for Arria 10 variations. If your design includes multiple
IP cores, you should ensure they have different TX scrambler seed
values. Previously this functionality was not available for Arria 10
In addition, starting in the IP core
version 15.0, you must refrain from modifying the RTL parameter
SCRAM_CONST in Stratix V and
Arria V GZ variations, and use the new parameter in the Parameter
The Quartus II software v14.1 requires that
you specify a device if your IP core targets the Arria 10 device family. If you
do not specify your target Arria 10 device, the IP Upgrade tool insists that
your IP core requires upgrade, but does not clarify the reason.
You must ensure that you specify a device for
your v13.1 Arria 10 Edition or v14.0 Arria 10 Edition IP core variation and
regenerate it in the Quartus II software v14.1.
Table 8. Version 13.1 Arria 10 Edition December 2013
Added support for Arria 10 devices. IP core variations that
target an Arria 10 device have additional interfaces and design requirements.
Table 9. 100G Interlaken IP Core Signal Changes. Signals added or modified in version 13.1 Arria 10 Edition.
Old Signal Name
New Signal Name
New interface to external TX PLL.
Relevant for Arria 10 variations only.
New Arria 10 transceiver
reconfiguration interface. Relevant for Arria 10 variations only.
Not present in Arria 10 variations.
interface for Arria V and Stratix V variations. This interface is present only
in Arria V and Stratix V variations (as supported in past and future versions
of the Quartus II software). It is not present in Arria 10 variations.
Added optional ECC feature on M20K blocks in
Stratix V devices.
Added bit error injection testing feature to
check CRC24 error detection.
Changed implementation of single segment mode:
Received data format to
If you select Single
segment mode, the IP core can no longer handle incoming dual segment traffic on
the TX client data interface.
Added four new parameters to optionally include
advanced error reporting and handling, Stratix V M20K block ECC feature,
diagnostic features, and in-band flow control functionality. Excluding the
features improves resource utilization.
Changed the behavior of the management
interface during read operations. The IP core asserts the
mm_rddata_valid signal two
mm_clk cycles after the
mm_read signal is asserted, instead of one
mm_clk cycle as in previous versions of the IP