40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes
If a release note is not available for a specific IP core version, the IP
core has no changes in that version. Information on the latest update releases is in the
Altera Complete Design Suite Update Release Notes.
40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Update 2
Table 2. Version 14.0 Update 2 September 2014
Fixed an issue in which incoming runt Ethernet packets of size
one byte to eight bytes caused the 40GbE IP core to hang instead of handling
If you upgrade to version 14.0 Update 2 of
the Quartus II software, you must upgrade your 40-100GbE IP core to incorporate
this fix. The fix has no effect on 100GbE IP cores, which did not have the
issue. However, the previous versions of the 40-100GbE IP core require upgrade
with the Quartus II software.
40- and 100-Gbps Ethernet MAC and PHY IP Core v13.1
Table 4. Version 13.1 November 2013
Added 40GBASE-KR4 option with FEC and with
auto-negotiation and link training mode options.
Added Synchronous Ethernet clock support option
in Stratix V devices. The option separates the TX PLL and RX CDR input
reference clocks (tx_ref_clk and
rx_ref_clk signals replace
ref_clk for these variations) and exposes the RX
Exposed link fault signals
local_fault_status in duplex variations.
Exposed PHY status signals
lanes_deskewed in MAC&PHY variations.
Updated and simplified the example design and
testbench. The testbench stimulus is simpler and the user no longer needs to
configure the DUT with a specific name and clock rate.