10-Gbps Ethernet (10GbE) MAC IP Core Release Notes
RN-1121 | 2016.05.02
10-Gbps Ethernet (10GbE) MAC IP Core Release Notes
If a release note is not available for a specific IP core version, the IP core has no changes in that version. Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related information
10-Gbps Ethernet (10GbE) MAC v15.1
Description | Impact |
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Enhanced unidirectional feature to support user-triggered remote fault notification through the register bit. | — |
10-Gbps Ethernet (10GbE) MAC v15.0
Description | Impact |
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Added new TX and RX registers, vlandet_dis, in the frame decoder for the option to disable VLAN or stacked VLAN tag detection. To disable the detection of VLAN/SVLAN type frame (length type field = 0x8100), set the register to 1. | This new register is available when you upgrade the IP core to v15.0 |
10-Gbps Ethernet (10GbE) MAC v14.0
Description | Impact |
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Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. | - |
Added support for clause 66 of IEEE 802.3—synthesis option. | This change is optional. If you do not upgrade your IP core, it does not have this new feature. |
10-Gbps Ethernet (10GbE) MAC v13.1
Description | Impact |
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Removed support for the following devices:
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Removed 1G/10GbE MAC and 10M-10GbE MAC with IEEE 1588v2 design examples from the directory. | - |
The 10GbE MAC with 10GBASE-R PHY and IEEE 1588v2 configuration supports only Arria V GT device with speed grade 3_H3. | - |
Increased the width for path delay interface signals such as tx_path_delay_10g_data (16 bits), tx_path_delay_1g_data (22 bits), rx_path_delay_10g_data (16 bits), and rx_path_delay_1g_data (22 bits) | - |