An FPGA power tree is a graphical
representation of your system’s power management architecture. The power tree
the main supply power flow through a tree of power converters that convert the main supply
power to the voltage and current required to drive various loads.
FPGA design has unique power consumption requirements requiring a unique power tree. This topic
describes optimizing an FPGA power tree for your FPGA design.
FPGAs have several inputs requiring power for the FPGA to operate. These
inputs produce power to various resource blocks within the FPGA, including logic, RAM,
digital signal processing (DSP), phase-locked loops (PLLs), clocks, I/Os, and transceivers.
These resource blocks have static and dynamic power requirements that vary by your selected
FPGA and utilization. Your selected FPGA does not have a fixed power requirement. The total
power consumption, and your FPGA power tree, depends on your design. To create an FPGA
Obtain power requirements with the Early Power Estimator (EPE).
Obtaining Power Requirements with the Early Power Estimator
Your FPGA's power consumption is determined by
the implementation of your FPGA
components such as logic requirements, the quantity and type of I/Os, the quantity and
speed of transceivers, and the use of other FPGA features contribute to your FPGA's
must understand your FPGA power requirements to create an FPGA power
Calculate your FPGA power requirements with the Microsoft Excel-based Early
Power Estimator (EPE) spreadsheet.
Estimate power consumption at any point in your design cycle, including before
you begin your design, or before your design is complete.
The EPE spreadsheet allows you to submit estimates of how you will use the
various resource blocks in your FPGA. When you enter your estimates, the EPE
spreadsheet automatically estimates the required power consumption. For detailed
information on using the EPE spreadsheet, see the Early
Power Estimator for
Arria® 10 User
switching from the EPE spreadsheet to the Power Analyzer in the
Quartus® Prime software when your design is available. The Power Analyzer can
access the implemented design details to produce more accurate results. For detailed
information on using the Power Analyzer, refer toIntel Quartus
Prime Pro Edition User Guide: Power Analysis and Optimization.
the input supply voltage
FPGA power tree. Systems typically favor one of two implementations: a 12V input source, or a
low voltage (5V or 3.3V) input source.
Most FPGA inputs require a voltage of ≤3.3V. Building an FPGA power tree from a
low voltage input source often allows for a smaller, more efficient system. If you use an
input source of 12V or higher, or if the
Power Estimator (EPE) spreadsheet estimates the total FPGA current consumption is very high,
Intel recommends that you use a
two-stage voltage solution, where:
A first-stage power converter converts a high voltage to a lower intermediate voltage, and
A second-stage power converter converts the intermediate voltage to the final FPGA input voltages
Figure 1. Two-Stage FPGA Power TreeThis two-stage FPGA power tree voltage solution allows you to power
the FPGA inputs with efficient, low-voltage converters. The figure
a 12V power converter converting the input supply to a lower 5V or 3.3V intermediate
voltage. The point of load (POL) low-voltage converter then converts the intermediate
voltage to the final FPGA input voltages, usually between 0.85V and 3.3V.
input supply voltage and voltage architecture
you select power converters.
power rails that
your design requires.
power tree only needs to supply power to the
power rails. It is unlikely that all of your FPGA resource blocks are in use, even in a
The Report tab in the
Power Estimator (EPE) spreadsheet
the expected voltage and current requirements for each FPGA power rail based on your
spreadsheet indicates which FPGA power rails require a power supply in two ways:
The FPGA input line has a non-zero value in the Total
Current (A) column.
For EPE spreadsheet versions 18.0 and later, the FPGA input
line has an assigned (not gray) entry in the Power
Regulator Settings Regulator Group column next to the Total Current (A) column.
Figure 2. ICCIO Section Call Out from the
Spreadsheet Report TabThis figure
the Report tab of the
spreadsheet highlighting utilized inputs. Some inputs, such as FPGA I/O (ICCIO), are generic inputs that may have a total
current value that is the sum of the currents required for various I/O inputs at
different voltage levels. In this case,
the individual ICCxx rows indicate the various I/O
input currents at each voltage level. In this example, you must use different
power rail groupings for the ICCIO
V) and ICCIO (1.8
V) power rails.
You must identify the power rails requiring power in your design
of the power
Intel FPGAs have several inputs
requiring power, but each input does not necessarily require a dedicated power
in a group
with a single regulator supplying the sum total of the
a group of
inputs can reduce the
on your PCB and reduce your system costs. When creating your FPGA
power tree, you should
of all relevant extracted FPGA power rails for use with a single
Refer to the Pin Connection Guidelines
for your selected
Intel FPGA to determine what
together; the Pin Connection Guidelines recommend a
power supply block architecture for each FPGA configuration and provide details
about each input pin required during hardware design.
Figure 3. Example Power
Arria® 10 SX Device with Transceiver Data
Rates ≤ 11.3 Gbps for Chip-to-Chip application
figure shows a recommended
Arria® 10 GX, GT, and
Family Pin Connection Guidelines.
When using a switcher to supply these voltages, the
switcher must be a low noise switcher as defined in note 7 in the notes
in the Intel Arria 10 SX Pin Connection
The supported tolerance for the VCCIO power supply
varies depending on the I/O standards. For more details, refer to the
I/O standard specification in the Intel Arria 10
Device Datasheet. Use the EPE tool to determine the power
required for your specific design.
Each board design requires its own power analysis to
determine the required power regulators needed to satisfy the specific
board design requirements.
Intel suggests power rail
groupings in the Pin Connection Guidelines for each
Intel FPGA, but there are two
other factors to consider when grouping your power rails. First, each of the FPGA
power rail inputs in a group must have the same supply voltage requirement. This
limitation is important for FPGA resource blocks such as I/O inputs that might
require different voltages depending on the specific interface protocols
in your design. For example, a
PCI Express® (
PCIe®) I/O interface might
require a 3
V input supply and an LVDS I/O interface might require a 2.5
V input supply; while both are I/O inputs, and the Pin Connection Guidelines simplified the I/O inputs as a
single VCCIO rail, these two I/O inputs must be powered by different converters.
The second power rail grouping factor to consider is power-up sequencing. Not
every FPGA or system requires power-up sequencing, but many advanced FPGAs require
that power is supplied to various inputs in a specific order during system power-up.
You can locate the power-up sequence guidelines for your selected
Intel FPGA in the device’s
Pin Connection Guidelines or Handbook. If your design requires power-up sequencing, you must ensure
that grouped power rail inputs meet the sequence requirements for your
provide power to
if it depends upon another rail in the same group or a rail in a
provide power to
inputs in your design
combination with another group of FPGA inputs that share their voltage and
Figure 4. Power-Up Sequence Requirement for
Arria® 10 DevicesThis figure
power-up sequence requirements for the
Arria® 10 V device as described in
Power Management in
Arria® 10 Devices
your power rail input groupings,
Power Estimator (EPE) spreadsheet to determine the total power required for the
input group. The
spreadsheet combines the current requirements for each load by summing each FPGA
The result are
column in the
spreadsheet Report tab.
Figure 5. Power
inputs at any point in your design cycle, including before you
your design, or before your design is complete.
your FPGA power tree architecture and power requirements, you must select your power
every FPGA power rail input group requires a power converter.
The converters must meet the minimum electrical requirements for input voltage, output
voltage, and output load current.
Once you determine what converters meet the minimum electrical requirements,
you must prioritize your system requirements, including size, efficiency, switching
frequency, power supply noise, and cost. Optimizing some parameters or resources may
degrade the performance of others. For example, increasing the switching frequency
allows for a smaller system size with lower switching noise in critical frequency
bands, but higher switching frequency requires more DC-DC switching and reduces
efficiency by generating more switching loss. The
power solutions use special design techniques and laterally diffused metal oxide
semiconductor technology to reduce loss at high switching frequencies to minimize
Figure 6. Equations Relating Switching Frequency, Inductance, Capacitance, and Switch LossThese four equations can help you prioritize your system requirements.
Equation a describes how inductance gets
smaller with higher switching frequencies. Lower inductance enables the use of
smaller, more efficient inductors. Equations b and c illustrate that input
and output capacitance are smaller with higher switching frequency. Lower
capacitance generally enables the use of smaller, cheaper capacitors. Equation
d represents power loss, or a combination
of conduction losses and switching losses. Power loss, even at high switching
frequencies, can be minimized by
devices designed to minimize CISS and COSS.
System priorities also vary depending upon the load. For example, the FPGA core power rail input (VCC) requires high power supply accuracy and low ripple to meet tight tolerance specifications, while power supply noise is a key parameter for sensitive power rails (such as transceiver voltage rails) to minimize both jitter and the bit error rate (BER).
Some power management decisions impact designs at the system level and must be
considered early in the design process for successful implementation in the final
system design. Some components support more advanced system power management and
FPGA power reduction techniques; these components typically require special
interfaces and feature sets that you should specify early in the FPGA design
process. For example, you can include
Enpirion® power solutions that support SmartVID
Arria® 10 10 device designs, or use
Enpirion® digital controllers and
PowerSoCs with a PMBus interface to implement system telemetry.
converter groupings and recommendations
Power Estimator (EPE) versions 13.1 and later. The
tool automatically and seamlessly groups relevant FPGA power rails according to the
recommendations in your selected
Intel FPGA’s Pin Connection Guidelines. Based on the resulting current requirements, the
Enpirion® power solutions that best meet
Enpirion tab of the
the recommended power solution.
Report tab of the PowerPlay EPE
to manually adjust groupings based on your design. Modifications
can include: using I/O protocols at different voltages; separating sensitive rails;
and implementing sequencing.
to adjust the power solution recommendations based on your design
priorities. Modifications can include: selecting rails to choose a low-dropout (LDO)
regulator for lower noise or lower cost; and selecting devices with a “Power Good”
(POK) flag for sequencing or other fault monitoring.
Figure 7. The
Enpirion® Tab in the