functional defects or errors, which may cause the product to deviate from published
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information on errata and the versions affected by errata, refer to the Knowledge Base
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DSP Builder for Intel FPGAs Advanced Blockset Revision History
Table 1. Revision History
Added support for two new floating-point types float16_m7 (bfloat) and float19_m10.
Added dependent latency feature.
Added FIFO buffer fill-level reporting.
Added HDL import.
Added C++ software models.
Added support for automatic reset minimization
of DSP Builder designs. Reset minimization determines the
minimal set of registers in a design that require reset, while
retaining the design’s correct functionality. Reducing the
number of registers that DSP Builder resets may give improved
quality of results i.e. reduced area and increased Fmax.
Added support for bit fields to the SharedMem block. These fields
provide analogous functionality to the existing bit field
support in the RegField
and RegOut blocks.
Added beta support for HDL import, which
incorporates VHDL or Verilog HDL synthesizable designs into a
DSP Builder design. You can then cosimulate the imported design
with DSP Builder Simulink components. HDL import includes a
minimal user interface, but requires some manual setup. To use
this feature, you require a license for the MathWorks HDL
Added super-sample NCO design example.
Added support for
Cyclone® 10 and
Stratix® 10 devices.
Removed instances of Signals block.
Deleted WYSIWYG option on SynthesisInfo block.
Rebranded as Intel
Deprecated Signals block
Added Gaussian and Random Number Generator
Added variable-size supersampled FFT design
Added HybridVFFT block
Added GeneralVTwiddle and GeneralMultVTwiddle blocks
Added 4-channel 2-antenna DUC and DDC for LTE
Added BFU_simple block
Created Standard and Pro editions. Pro supports
Arria 10 devices; Standard supports all other families.
Deprecated the Signals block
Added functionality for setting the Avalon-MM
interface settings in the DSP Builder menu
Improved folding results on MAX 10 devices
Added new design examples:
Gaussian Random Number Generator
DUC_4C4T4R and DDC_4C4T4R LTE
digital-up and down-conversion
Added new FFT pruning strategy: prune_to_widths()
Quartus II and Run
Added clock crossing support
Added reconfigurable FIR filters
Improved bus interfaces:
Improved error checking and reporting
Improved simulation accuracy
Improved bus slave logic implementation
Improved clock crossing
Changed some Avalon-MM interfaces
Added new blocks:
Added IIR: full-rate fixed-point and IIR:
full-rate floating-point demos
Added transmit and receive modem reference
Added support for SystemVerilog output
Added external memories library
Added new Allow
write on both ports parameter to DualMem block
Changed parameters on AvalonMMSlaveSettings
Added support for Arria 10 hard-floating-point
Added BusStimulus and BusStimulusFileReader
blocks to memory-mapped registers design example.
Added AvalonMMSlaveSettings block and
DSP Builder > Avalon
Interfaces > Avalon-MM slave menu option
Removed bus parameters from Control and Signal
Removed the following design examples:
Color Space Converter (Resource Sharing
Interpolating FIR Filter with Updating