Intel Quartus Prime Design Suite Version 18.1 Update Release Notes
RN-01080-18.1.2.0 | 2019.04.17
Intel Quartus Prime Design Suite Version 18.1 Update Release Notes
The Intel® Quartus® Prime Design Suite Update Release Notes describe the contents of Intel® Quartus® Prime Design Suite Version 18.1 software updates.
The Intel® Quartus® Prime Design Suite Version 18.1 updates apply only to Intel® Quartus® Prime Pro Edition.
Issues Addressed in Update 1
To take advantage of these updates, install Intel® Quartus® Prime Design Suite Version 18.1 Update 1 as soon as possible.
Intel Quartus Prime Pro Edition Software
Intel® Quartus® Prime Software
-
Starting in V18.1.1, you cannot set the following Advanced I/O Timing
assignments as a global setting. You can still use these assignments as pin
assignments.
- OUTPUT_IO_TIMING_NEAR_END_VMEAS
- OUTPUT_IO_TIMING_FAR_END_VMEAS
- OUTPUT_IO_TIMING_ENDPOINT
- BOARD_MODEL_NEAR_PULLUP_R
- BOARD_MODEL_NEAR_PULLDOWN_R
- BOARD_MODEL_NEAR_C
- BOARD_MODEL_NEAR_SERIES_R
- BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
- BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
- BOARD_MODEL_NEAR_TLINE_LENGTH
- BOARD_MODEL_TLINE_C_PER_LENGTH
- BOARD_MODEL_TLINE_L_PER_LENGTH
- BOARD_MODEL_TLINE_LENGTH
- BOARD_MODEL_FAR_SERIES_R
- BOARD_MODEL_FAR_C
- BOARD_MODEL_FAR_PULLUP_R
- BOARD_MODEL_FAR_PULLDOWN_R
- BOARD_MODEL_TERMINATION_V
- BOARD_MODEL_NEAR_SERIES_C
- BOARD_MODEL_NEAR_DIFFERENTIAL_R
- BOARD_MODEL_FAR_DIFFERENTIAL_R
Intel® Quartus® Prime Device Support
- Enabled advanced support for Intel® Stratix® 10 1SG211H and 1SG166H device families.
- Enabled full support for Intel® Stratix® 10 1SM16BH, 1SM16CH, 1SM21BH, 1SM21CH, 1ST250E, and 1ST280E device families.
- Enabled SRAM object file (.sof) support for Intel® Stratix® 10 1ST280 and 1ST250 device families.
- The timing model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.
- The power model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.
Intel® Quartus® Prime Compilation and Design Flows
- The Intel® Quartus® Prime Compiler uses a parallel IP generation scheme now by default. Previously, using parallel IP generation was optional.
- The Enable Early Place flow setting is not supported with "Compile Time" Optimization Mode. The Compilation Dashboard shows status failed for the Fitter (Early Place) module, because it has been skipped in the compilation flow.
Fitter
- Fixed bug with overly restrictive placement check for preserved logic in an incremental compile.
- Improved estimation of Hyper-Registers for device limit resource checking.
- Improved compile time in Quartus placement for Windows.
- Removed “Optimize for High Utilization” option from the “Physical Placement Effort” setting. Changes to improve placement for high utilization designs were incorporated into the default compilation flow.
- Improved compiler to use more accurate estimation for clock resources at the row level thus helping to avoid errors in routing.
-
Fixed an issue that could cause the
following fitter error to be incorrectly printed in incremental compilations when global
signals are driven to partitions and left
unused.
Error (18974): Signal is constrained to be routed locally to destination(s), but signal must be routed globally
- The Enable Early Place flow setting is not supported with "Compile Time" Optimization Mode. The Compilation Dashboard shows status failed for the Fitter (Early Place) module, because it has been skipped in the compilation flow.
- Fixed incorrect bit settings for 8LUT LUTMASKs in cases where the fitter performs optimizations on them.
Partial Reconfiguration
- Compilation support added to support a hardware issue affecting Intel® Arria® 10 10AX16-10AX32 and 10AS16-10AS32 device families and Intel® Cyclone® 10 devices that use Partial Reconfiguration or EDCRC. The changes ensure that resources that might be susceptible to glitches are not used during these compilations.
- For Intel® Stratix® 10 devices, a POF ID feature is added to help you with PR bitstream incompatibility checks. This feature is turned on by default. To enable this feature for an existing design, you must recompile the design and regenerate your bitstream using Version 18.1.1. PR POF ID must be enabled if you want to enable PR authentication. The maximum number of PR regions is 32 with PR POF ID enabled.
Platform Designer
- Fixed the Parameters tool, which would continuously flicker after changing a parameter, for some video IPs, such as the Color Plane Sequencer II, and Color Space Converter II.
- Platform Designer uses a parallel IP generation scheme now by default. Previously, using parallel IP generation was optional.
Power Analyzer
- For Intel® Stratix® 10 L-tile devices, the power model is updated for VCCIO3V rail. For details, see the Intel® FPGAs and Programmable Devices Knowledge Base.
- The power model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.
Programmer
- For Intel® Stratix® 10 devices, fixed the JAM/JBC syntax error for 2 Gb QSPI flash.
- Fixed an internal error that occurred in the Programmer GUI when autodetecting the EPCQA and S25FL flash.
- Fixed an issue where flash smaller than 128 Mb was not detected automatically.
- The complete Design Hash value in .sof file can now be found in the Compilation report, under Assembler -> Device Option -> Design hash.
- Fixed an error in the Intel® Stratix® 10 signing tool, which might cause unexpected behavior when the signing tool hashes the data.
- Fixed an unexpected closing of the Programmer GUI when an error occurred in the signing tool.
- For Intel® Stratix® 10 devices, added support for RSU upgrade and PR compatibility check.
- For Intel® Stratix® 10 devices, added support for signing certificates and allowing key cancel ID of 32-63.
Timing Models
- For Intel® Stratix® 10 devices, the timing model is updated. For details, see the Intel® FPGAs and Programmable Devices Knowledge Base.
- The timing model status for Intel® Stratix® 10 1SG280H, 1SX280H, 1SG250H, 1SX250H, 1SG210H, 1SX210H, 1SG165H, 1SX165H, 1SG110H, 1SX110H, 1SG085H, and 1SX085H devices is now set to Final.
Intel Quartus Prime Standard Edition Software
Intel® Quartus® Prime Software
- Intel® Quartus® Prime Standard Edition Software Version 18.1 Update 1 has been updated with Curl 7.64.0, CygWin 3.0.3, flexnet_publisher 11.16.1.0, openssl 1.0.2r, python 3.6.8, ccl_sqlite3 3.27.0, sqlite3 (python) 3.26.0, xerces-c++ 3.2.2, and zlib 1.2.11, which include functional and security updates. Update to the latest version of Intel Quartus Prime Design Software as soon as possible.
- Added Generic Flash Programmer tool, which supports a wide range of third-party QSPI flash devices.
Intel® Quartus® Prime Software GUI
-
In the IP Catalog, the following IP
core names were changed:
- FIR II Intel FPGA IP (was FIR II)
- FP_ACC_CUSTOM Intel FPGA IP (was ALTERA_FP_ACC_CUSTOM)
- FP_FUNCTIONS Intel FPGA IP (was ALTERA_FP_FUNCTIONS)
Also, other IP cores might be renamed to remove "Altera" from their name in the IP Catalog.
- Added a link to the Intel® Quartus® Prime License Agreements to the About Quartus Prime dialog box.
- For Cyclone® IV and Intel® Cyclone® 10 LP device families, removed 2.5 V as a valid device I/O voltage.
Intel® Quartus® Prime Command Line
- Added a link to the Intel® Quartus® Prime License Agreements to the command-line banner.
Intel® Quartus® Prime Device Support
- For Cyclone® IV and Cyclone® V devices, updated the Serial Flash Loader (SFL) factory image to allow the devices to be programmed with a JTAG indirect configuration file (.jic).
Intel® Quartus® Prime Compilation and Design Flows
- Updated synthesis to ensure that a non-dedicated reference clock signal (refclk) generates an error message.
- Fixed an issue causing abnormally large memory size when inferring ROM with read enabled.
-
Fixed an issue that resulted in the
following error
message:
Internal Error: Sub-system: AMM, File: /quartus/db/amm/amm_atom_mod_util_impl.cpp, Line: 4729
Advanced Link Analyzer (formerly JNEye)
-
Enhanced Advanced
Link Analyzer:
- Added full end-to-end mixed-mode simulation support.
- Enhanced Channel Viewer to show effective return loss (ERL).
- Enhanced Channel Designer to add support for both far-end (FEXT) and near-end (NEXT) crosstalk extractions.
Platform Designer (former Qsys)
- Fixed an issue that prevented simulation of systems using a Intel® Quartus® Prime Standard Edition design.
Programmer
- Fixed issues that caused programming failures when using Macronix MX25L and Cypress S25FL flash memory devices.
- Fixed issues that caused programming failures when using Intel EPCQ-A serial configuration devices.
Timing Analyzer
-
Fixed an issue that resulted in the
following error
message:
Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_report_metastability.cpp, Line: 2264
IP and IP Cores
Unless stated otherwise, the following IP issues apply only to the Intel® Quartus® Prime Pro Edition software.
For
Intel®
Quartus® Prime Standard Edition software, multiple IP cores
were fixed to prevent the following error message that occurred when trying open
generated
IP:
Failed to launch MegaWizard Plug-In Manager. <IP_name> could not be found in the specified library paths.
25G Ethernet IP Core
- For Intel® Quartus® Prime Standard Edition software, updated the alignment marker format of Soft 25G Ethernet to align with the IEEE 802.3by-2016 standard.
40G Ethernet IP Core
- Fixed an error with the reconfiguration arbitration logic in the hardware example top-level file.
DisplayPort IP Core
- For Intel® Stratix® 10 devices, enabled Pixel Clock Recovery function.
- Changed Synopsys Design Constraints to entity-based Synopsys Design Constraints.
- Cleaned up compilation warnings found in Intel® Stratix® 10 design example with pixel clock recovery.
- Enabled Intel® Stratix® 10 design example with Pixel Clock Recovery variant.
- Enabled initiation of Tx in software regardless of the setting of DP_SUPPORT_EDID_PASSTHRU.
- Fixed an Intel® Arria® 10 design example when no display output occurred in non GPU mode.
- Enabled extended receiver capabilities when the maximum link rate is HBR3.
- For Intel® Stratix® 10 H-Tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.
External Memory Interface IP Cores
- For Intel® Cyclone® 10 devices, enabled DDR3x72 support for 10CX085 FBGA672 devices.
- For Intel® Stratix® 10 devices, added support for DDR4 clamshell layout.
Fixed Point Functions Intel FPGA IP Core
- The Fixed Point Functions Intel FPGA IP depends on the dspip_recipes library, which was unintentionally removed in Intel® Quartus® Prime Pro Edition Version 18.1. The dspip_recipes library has been restored in Version 18.1.1.
HDMI IP Core
- For Intel® Stratix® 10 H-Tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.
High Bandwidth Memory Interface IP Core
- Enabled Intel® Stratix® 10 MX production devices.
High Speed Serial Interface (HSSI) IP Core
- Some configurations of the Intel® Stratix® 10 Transceiver IP with multiple reconfiguration profiles enabled might have more pessimistic timing analysis on data transfers between the transceivers and main fabric. Run the Version 18.1.1 Timing Analyzer on such designs to ensure timing closure.
- Improved timing driven placement and routing support for reconfigurable HSSI designs.
- Disabled the use of hyper-pipeline registers in the GUI.
Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Core
- Fixed signal connections for manual reset mode.
- Fixed the reset IP option to enable individual channels when individual Tx/Rx is enabled.
-
Disabled the following GUI options:
- Enable TX fast pipeline registers
- Enable RX fast pipeline registers
- Updated the ical and pcal tuning parameters.
- Improved PHY performance in 3m DAC cables.
- Enabled BTI protection on the unused slave channels for dual-channel PAM4 Native PHY instances.
Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP Core
- Removed a redundant character that caused warning message.
- Fixed an issue where an incorrect clock might be used when AN mode switches to data mode.
Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Core
- Added multi-segment mode support.
- Added Number of Segments parameter.
- Added support for lane and data rate combinations as
follows:
- For
Intel®
Stratix® 10
L-tile devices:
- 4 lanes with 12.5/25.3/25.8 Gbps lane rates
- 8 lanes with 12.5 Gbps lane rates
- For
Intel®
Stratix® 10
H-tile devices:
- 4 lanes with 12.5/25.3/25.8 Gbps lane rates
- 8 lanes with 12.5/25.3/25.8 Gbps lane rates
- 10 lanes with 25.3/25.8 Gbps lane rates
- For
Intel®
Stratix® 10
E-tile (NRZ) devices:
- 4 lanes with 6.25/12.5/25.3/25.8 Gbps lane rates
- 8 lanes with 12.5/25.3/25.8 Gbps lane rates
- 10 lanes with 25.3/25.8 Gbps lane rates
- 12 lanes with 10.3125 Gbps lane rate
- For
Intel®
Stratix® 10
L-tile devices:
- Added the following new transmit user interface
signals:
- itx_eob1
- itx_eopbits1
- itx_chan1
- Added the following new receiver user interface
signals:
-
irx_eob1
-
irx_eopbits1
-
irx_chan1
-
irx_err1
-
irx_err
-
Remote Update IP Core
- Corrected pinout names to prevent errors during synthesis.
Serial Digital Interface (SDI) II Intel® FPGA IP Core
- For Intel® Stratix® 10 H-Tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.
Triple-Speed Ethernet IP Core
- For Intel® Quartus® Prime Standard Edition software, fixed an issue preventing generated IP files from being displayed in the IP Catalog.
Virtual JTAG IP Core
- For Intel® Quartus® Prime Standard Edition software, fixed an issue with possible broken JTAG continuity when a virtual IR access is issued.
DSP Builder for Intel FPGAs
Unless stated otherwise, the following DSP Builder for Intel® FPGAs issues apply only to the Intel® Quartus® Prime Pro Edition software.
- Single-precision floating-point adders in a DSP Builder design can now use a mixture of hard and soft implementations.
- VFFT_btb and VFFT_Light_btb blocks have been added. These support back-to-back operation of the variable-size FFT, so there is no need to flush the FFT pipeline between different-size FFT iterations.
- A defect in the VFFT_cp_btb and VFFT_Light_cp_btb blocks has been corrected. When the 18.1 versions of these blocks were used with multiple subchannels, the output start-of-packet, size and (for VFFT_cp_btb) end-of-packet signals were not correctly synchronized with the output valid signal.
- The optimization of floating-point scalar products is now slightly less aggressive. With default settings, DSP Builder no longer attempts to infer a chain-in input for scalar products. As a result of this change, complex scalar products now consume slightly more DSP blocks but require fewer logic resources for latency-balancing.
- Fixed initialization of SharedMems of type single precision float.
- Added support for loop blocks to the Advanced C-model feature.
Intel High Level Synthesis Compiler
Unless stated otherwise, the following Intel® HLS Compiler issues apply only to the Intel® Quartus® Prime Pro Edition software.
- The Intel® HLS Compiler now merges identical read access to an array. Previously, you had to explicitly merge identical array accesses.
- Added the HLS_SYNTHESIS macro. Statements in your component guarded by this macro work in x86 emulations but are disabled when compiling your component to an FPGA architecture.
- The HLS/iostream.h header file is deprecated. To use C++ standard output streams in your component, use the standard <iostream> header file and guard the output statements with the new HLS_SYNTHESIS macro.
- Fixed simulation failures that occurred when components or component parameters have names that are not unique or that conflict with reserved RTL keywords.
- Removed the misleading warning Warning:-march has no effect. Using setting from -c compile when using i++ to link object files.
- Fixed issues with #pragma ivdep which might cause a segmentation fault when the pragma is used with array clauses.
- Updated the ac_int_basic_ops tutorial to use -std=c++14.
- Fixed bugs in the ac data types provide with the Intel® HLS Compiler.
- Replaced deprecated system call (fopen) on Windows for YUV2RGB example design.
Intel FPGA SDK for OpenCL
See the section for your edition of the Intel FPGA SDK for OpenCL* to learn about issues
fixed and changes in Intel FPGA SDK for OpenCL* Version 18.1 Update 1:
Changes in Intel FPGA SDK for OpenCL* Pro Edition Version 18.1 Update 1
- Fixed an error that occurred when reading data from a channel directly into the __local address space.
- Fixed an issue preventing some diagnostic messages from printing when you compiled kernel code for the fast emulator platform. In some rare cases, kernel compilations for the fast emulator failed without printing any useful error messages.
- Fixed an issue where all pointer parameters in OpenCL* kernels were incorrectly marked as __restrict.
- Fixed an issue where, in complex scenarios, a channel read in an autorun kernel might have forwarded data too soon.
- Removed cl_khr_3d_image_writes from the list of extensions advertised by the Intel FPGA SDK for OpenCL Runtime. This extension was advertised by mistake in previous releases.
- Fixed a bug that cause a crash when using multiple channels.
- Increased the maximum number of allowable identical abbreviated file names in OpenCL kernels from 1000 to 1000000.
- Set the INTELFPGA_CL macro to the version number of the compiler to enable users to version their code based on compiler version.
- Fixed issues with #pragma ivdep which might cause a segmentation fault when the pragma is used with array clauses.
- For Intel® Stratix® 10 devices, improved the stability of the OpenCL incremental compilation.
- Fixed an incremental compilation bug caused by an internal naming issue.
-
Fixed an
issue in the RTE where the aocl version command
returned the following
error:
aocl: Detailed error: Could not determine the path to SDK internal libraries
Changes in Intel FPGA SDK for OpenCL* Standard Edition Version 18.1 Update 1
- On Linux platforms, separately downloadable installers are now available for
the following board support packages (BSPs). The BSPs also remain packaged with
the
Intel® FPGA SDK for OpenCL™
.
-
Cyclone® V SoC Development Kit
Reference Platform (c5soc)Download one the following packages from the Download Center for FPGAs - Intel® FPGA SDK for OpenCL™ page:
-
Intel FPGA OpenCL Board Support Package for Cyclone V SoC Linux x86-64 RPM
-
Intel FPGA OpenCL Board Support Package for Cyclone V SoC Linux x86-64 TGZ
-
-
Stratix® V Network Reference
Platform (s5_ref)Download one the following packages from the Download Center for FPGAs - Intel® FPGA SDK for OpenCL™ page:
- Intel FPGA OpenCL Board Support Package for Stratix V GX Linux x86-64 RPM
- Intel FPGA OpenCL Board Support Package for Stratix V GX Linux x86-64 TGZ
-
Cyclone® V SoC Development Kit
Reference Platform (c5soc)
- On Windows platforms, the
Cyclone® V SoC
Development Kit Reference Platform (c5soc)
BSP is now available as a separately downloadable BSP installer. The BSP also
remains packaged with the
Intel® FPGA SDK for OpenCL™
.Download the following package from the Download Center for FPGAs - Intel® FPGA SDK for OpenCL™ page:
- Intel FPGA OpenCL Board Support Package for Cyclone V SoC Windows x86-64 ZIP
- On Windows platforms, removed the
Stratix® V Network
Reference Platform board support package (s5_ref) from the
Intel® FPGA SDK for OpenCL™
package.
To use this BSP with Intel® FPGA SDK for OpenCL™ Standard Edition Version 18.1 Update 1, extract the Version 18.1 BSP (hld\board\s5_ref) from the Intel® FPGA SDK for OpenCL™ Standard Edition Version 18.1 download package and compile the BSP with Intel® Quartus® Prime Standard Edition Version 18.1 Update 1.
*OpenCL™ and the OpenCL logo are trademarks of Apple Inc. used by permission of the Khronos Group™.
Issues Addressed in Update 2
To take advantage of these updates, install Intel® Quartus® Prime Design Suite Version 18.1 Update 2 as soon as possible.
If you use the Intel HLS Compiler, this update requires Intel® Quartus® Prime Design Suite Version 18.1 Update 1. For details, see Known Issues and Workarounds for Intel Quartus Prime Pro Edition Version 18.1 Update 2.
Intel Quartus Prime Pro Edition Software
Intel® Quartus® Prime Software
- Includes new versions of certain third-party components with functional and security updates.
Programmer
- Added support for design authentication. For details, contact your Intel representative.
IP and IP Cores
Unless stated otherwise, the following IP and IP core issues apply to only to Intel® Quartus® Prime Pro Edition software.
Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express IP Core
- For Intel® Stratix® 10 H-tile devices, fixed an IP generation issue when an enabled Physical Function (PF) has no Virtual Functions (VFs).
Serial Digital Interface (SDI) II Intel® FPGA IP Core
- For Intel® Stratix® 10 H-tile devices, updated the design examples.
Intel FPGA SDK for OpenCL
Unless stated otherwise, the following Intel® FPGA SDK for OpenCL™ issues apply to only to Intel® Quartus® Prime Pro Edition software.
-
Removed
the precompiled
Intel®
Arria® 10 SoC Linux SD card images.
To create your own OpenCL Linux SD card image, refer to the Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide as updated for the Intel Quartus Prime Design Suite Version 18.1 Update 2.
Software Issues Resolved
| Customer Service Request Numbers Resolved | |||||
|---|---|---|---|---|---|
| 00258070 | 00279317 | 00284801 | 00285483 | 00288834 | 00288935 |
| 00289150 | 00289156 | 00289247 | 00289828 | 00290489 | 00290795 |
| 00290795 | 00299523 | 00325248 | 00325364 | 00325577 | 00325596 |
| 00342569 | 00342920 | 00351062 | 00351151 | 00351169 | 00351423 |
| 00368992 | 00379741 | 00385968 | 00386469 | 00386832 | 00387070 |
| 00387390 | 00387692 | 00387924 | 00388249 | 00388711 | 00388877 |
| 00388932 | 00388953 | 00389869 | 00391472 | 00391472 | 00391946 |
| 00392019 | 00392572 | 00392897 | 00393535 | 00393543 | 00393997 |
| 00394967 | 00395263 | 00395631 | 00395885 | 00396112 | 11284795 |
| 11387341 | 11409998 | 11412747 | 11413470 | 11413677 | 11415210 |
| 11417550 | |||||
For Intel® Quartus® Prime Pro Edition Version 18.1 Update 2, no resolved customer service requests are included in the update.
| Customer Service Request Numbers Resolved | |||||
|---|---|---|---|---|---|
| 00282536 | 00342954 | 00389785 | 00389785 | 00402607 | 00406354 |
| 00407615 | 00408513 | 00409113 | 00416511 | 11172886 | 11214848 |
| 11399886 | 11399890 | ||||
Software Patches Included in Update Releases
| Software Version | Patch | Customer Service Request Number |
|---|---|---|
| Intel® Quartus® Prime V18.1 | 0.23 | 392897 |
| Intel® Quartus® Prime V18.1 | 0.17 | 290795 |
| Intel® Quartus® Prime V18.1 | 0.14 | 388249 |
| Intel® Quartus® Prime V18.1 | 0.13 | 325364 |
| Intel® Quartus® Prime V18.1 | 0.11 | - |
| Intel® Quartus® Prime V18.1 | 0.08 | - |
| Intel® Quartus® Prime V18.1 | 0.07 | - |
| Intel® Quartus® Prime V18.1 | 0.05 | - |
| Intel® Quartus® Prime V18.1 | 0.02 | - |
| Intel® Quartus® Prime V18.1 | 0.01p | - |
| Intel® Quartus® Prime V18.1 | 0.01dp3 | - |
| Intel® Quartus® Prime V18.0.1 | 1.41 | 388249 |
| Intel® Quartus® Prime V18.0.1 | 1.40 | 11412747 |
| Intel® Quartus® Prime V18.0.1 | 1.39 | - |
| Intel® Quartus® Prime V18.0.1 | 1.38 | - |
| Intel® Quartus® Prime V18.0.1 | 1.27 | |
| Intel® Quartus® Prime V18.0.1 | 1.14 | 288834 |
| Intel® FPGA SDK for OpenCL™ V18.1 | 0.16cl | - |
For Intel® Quartus® Prime Design Suite Version 18.1 Update 2, no software patches are included in the update.
| Software Version | Patch | Customer Service Request Number |
|---|---|---|
| Intel® Quartus® Prime V18.1 | 0.11std | 00282536 |
| Intel® Quartus® Prime V18.1 | 0.08std | 00406354 |
| Intel® Quartus® Prime V18.1 | 0.04std | - |
| Intel® Quartus® Prime V18.1 | 0.03std | 00391701 |
Known Issues and Workarounds
Known Issues and Workarounds for Intel® Quartus® Prime Pro Edition Version 18.1 Update 1
| Description | Workaround |
|---|---|
| For the Intel® Stratix® 10 1ST210 E-tile device family, you cannot configure the device from AVST x16 or AVST x32. | Configure the device using AVST x8. |
Known Issues and Workarounds for Intel® Quartus® Prime Pro Edition Version 18.1 Update 2
| Description | Workaround |
|---|---|
| The Intel® High Level Synthesis (HLS) Compiler is not included in Intel® Quartus® Prime Version 18.1 Update 2. | If you use the
Intel® HLS Compiler,
install
Intel®
Quartus® Prime Pro Edition Version 18.1
Update 1 before you install
Intel®
Quartus® Prime
Version 18.1 Update 2. On the Updates tab of the Quartus Prime Pro Edition download page, you might need to click Show Archived Software Updates to access Update 1. |
For information about other known
software issues, visit the Intel® FPGA Knowledge
Base.
Document Revision History for Intel Quartus Prime Design Suite Update Release Notes
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2019.04.15 | 18.1.1 Standard |
|
| 2019.02.18 | 18.1.2 Pro |
|
| 2019.01.03 | 18.1.1 Pro |
In IP and IP Cores, corrected the name of the SDI II
Intel®
FPGA IP Core. Previously, this IP core was listed as Serial Data Interface (SDI) IP Core |
| 2018.12.24 | 18.1.1 Pro |
Initial release with Intel® Quartus® Prime Design Suite Pro Edition Version 18.1 Update 1 information. |