The design constraints, assignments, and logic options that you specify
influence how the
Quartus® Prime Compiler implements your
design. The Compiler attempts to synthesize and place logic in a manner than meets your
In addition, design constraints also have an
impact on how the Timing Analyzer and the Power Analyzer
influence synthesis, placement, and routing.
You can specify
design constraints in the GUI, with scripts, or directly in the files that store the
Quartus® Prime software
preserves the constraints that you specify in the GUI
in the following files:
Quartus® Prime Settings file (<project_directory>/<revision_name>.qsf)—contains
project-wide and instance-level assignments for the current revision of the project,
in Tcl syntax. Each revision of a project has a separate .qsf file.
Design Constraints file
Timing Analyzer uses industry-standard
Design Constraint format and stores
those constraints in .sdc files.
combining the syntax of the .qsf files and the
.sdc files with procedural Tcl, you can automate
iterations over several different settings, changing constraints and recompiling.
software provides tools that help you manually implement your project.
tools can also support design visualization, pre-filled parameters, and window cross
probing, facilitating design exploration and debugging.
When you create or update a constraint in the
Quartus® Prime software, the System tab of the Messages window displays the equivalent Tcl command. Utilize these
commands as references for future scripted design definition and compilation.
Global Constraints and Assignments
Global constraints and project settings affect
Quartus® Prime project and all the applicable logic
in the design.
You often define global constraints in early project
development; for example, when running the New Project Wizard.
Quartus® Prime software stores global constraints in .qsf files, one for each project revision.
Quartus® Prime Tools to Set Global
Node, entity, and instance-level constraints
apply to a subset of the design hierarchy. These constraints take precedence over any
global assignment that affects the same sections of the design hierarchy.
Quartus® Prime Standard Edition Tools to
Set Node, Entity and Instance Level Constraints
Vector input source
Specify Instance-Specific Constraints in Assignment Editor
Quartus® Prime Assignment Editor
(Assignments > Assignment Editor) provides a spreadsheet-like interface for assigning all instance-specific
settings and constraints.
To help you explore your design, the Assignment
Editor allows you to filter assignments by node name or category.
Quartus® Prime Assignment
Use the Assignment Editor to:
Add, edit, or delete assignments for selected nodes
Display information about specific assignments
Enable or disable individual assignments
Add comments to an assignment
Additionally, you can export assignments to a Comma-Separated Value File
Specify I/O Constraints in Pin Planner
Quartus® Prime Pin Planner allows you to assign design elements to I/O pins. You can also plan and
assign IP interface or user nodes not yet defined in the design.
With the Chip Planner you can adjust existing assignments to device resources,
such as pins, logic cells, and LABs in a graphical representation of the device
floorplan. You can also view equations and routing information and demote assignments by
dragging and dropping to Logic Lock (Standard) regions in the
Logic Lock (Standard) Regions
You can perform all your design
assignments using .sdc and .qsf setting files. To integrate these files in
compilation and optimization flows, use Tcl scripts.
Even though .sdc and .qsf files are
written in Tcl syntax, they are not executable by themselves.
When you use
Quartus® Prime Tcl packages, your scripts can open projects, make the assignments, compile the
design, and compare compilation results against known goals and benchmarks. Furthermore,
such a script can automate the iterative design process by modifying constraints and
recompiling the design.
Create a Project and Apply Constraints
The command-line executables include
options for common global project settings and commands. You can use a Tcl script to
apply constraints such as pin locations and timing assignments.
write a Tcl constraint file, or generate one for an existing project by clicking
Project > Generate Tcl File for Project.
The example creates a project with a Tcl script and
applies project constraints using the tutorial design files in the
Quartus® Prime installation
Save the script in a file called setup_proj.tcl and type the commands illustrated in
the example at a command prompt to create the design, apply constraints, compile the
design, and perform fast-corner and slow-corner timing analysis. Timing analysis
results are saved in two files,
filtref_sta_1.rpt and filtref_sta_2.rpt.
Valid locations are pin location names. Some
device families also support edge and I/O bank locations. Edge locations are
EDGE_RIGHT. I/O bank
n is the number of I/O banks
in a device.
Generating Intel Quartus Prime Settings Files
Quartus® Prime software allows you to generate
.qsf files from your revision.
You can embed these
constraints in a scripted compilation flow, and even create sets of
.qsf files for design optimization.
To generate a .qsf file from the
software, click Assignments > Export Assignments.
To organize the .qsf in a human readable form, Project > Organize
Quartus® Prime Settings File.
Organized .qsf File
This example shows how .qsf files characterize a design revision. The set_global_assignment command makes all global constraints and software settings and set_location_assignment constrains each I/O node in the design to a physical pin on the device.
Quartus® Prime software keeps timing constraints in .sdc files, which use Tcl syntax.
embed these constraints in a scripted compilation flow, and even create sets of .sdc files for timing optimization.
The example shows the timing constrains of a small design.
As an alternative to .sdc and .qsf files, you can perform
all design assignments and timing constraints inside the Tcl scripts. In this case, the
script that automates compilation and custom results reporting also contains the design
You can export a design's contents to a procedural, executable Tcl (.tcl) file, and then use the generated script to
restore settings after experimenting with other constraints.
To export your constraints as an executable Tcl script, click
Project > Generate Tcl File for Project.
For more information about special pin assignment features for the
SoC devices, refer to
Instantiating the HPS Component in the
Arria® 10 Hard Processor System Technical Reference Manual.
On FPGA design, I/O planning includes creating
pin-related assignments and validating them against pin placement guidelines. This
process ensures a successful fit in your target device.
When you plan and
assign I/O pins in the initial stages of your project, you design for compatibility with
your target device and PCB characteristics. As a result, your design process goes through
fewer iterations, and you develop an accurate PCB layout sooner.
You can plan your I/O pins even before defining design files. Assign expected
nodes not yet defined in design files, including interface IP core signals, and then
generate a top-level file. The top-level file instantiates the next level of design
hierarchy and includes interface port information like memory, high-speed I/O, device
configuration, and debugging tools.
Assign design elements, I/O standards, interface IP, and other properties to
the device I/O pins by name or by dragging to cells. You can then generate a top-level
design file for I/O validation.
Use I/O assignment validation to fully analyze I/O pins against VCCIO,
VREF, electromigration (current density), Simultaneous Switching Output (SSO), drive
strength, I/O standard, PCI_IO clamp diode, and I/O pin direction compatibility
Quartus® Prime software provides the Pin Planner tool to view, assign, and validate device I/O pin logic and
properties. Alternatively, you can enter I/O assignments in a Tcl script, or directly in
Basic I/O Planning Flow
The following steps describe the basic flow for assigning and
verifying I/O pin assignments:
Click Assignments > Device and select a target device that meets your logic, performance, and
I/O requirements. Consider and specify I/O standards, voltage and power supply
requirements, and available I/O pins.
Click Assignments > Pin Planner.
To setup a
top-level HDL wrapper file that defines early port and interface information for
your design, click Early Pin Planning in the
Click Import IP Core to import any defined IP
core, and then assign signals to the interface IP nodes.
Click Set Up Top-Level File and assign user nodes
to device pins. User nodes become virtual pins in the top-level file and are
not assigned to device pins.
Click Generate Top-Level File. Use top-level file
to validate I/O assignments.
Assign I/O properties to
match your device and PCB characteristics, including assigning logic, I/O standards,
output loading, slew rate, and current strength.
Click Run I/O Assignment Analysis in the Tasks pane to
validate assignments and generate a synthesized design netlist. Correct any problems
Processing > Start Compilation. During
Quartus® Prime software runs I/O
Integrating PCB Design Tools
You can integrate PCB design tools into
your work flow to map pin assignments to symbols in your system circuit schematics and
Quartus® Prime software integrates with
board layout tools by allowing import and export of pin assignment information in
Quartus® Prime Settings Files (.qsf), Pin-Out File (.pin), and FPGA
Xchange-Format File (.fx) files.
Table 4. Integrating PCB Design Tools
PCB Tool Integration
Supported PCB Tool
Define and validate I/O assignments in the Pin
Planner, and then export the assignments to the PCB tool for
Define I/O assignments in your PCB tool, and then
import the assignments into the Pin Planner for validation
The following terms describe Intel device and I/O structures:
Assigning I/O Pins
Use the Pin Planner to visualize, modify, and validate I/O
assignments in a graphical representation of the target device.
increase the accuracy of I/O assignment analysis by reserving specific device pins to
accommodate undefined but expected I/O.
To assign I/O pins in the Pin Planner, follow these steps:
Quartus® Prime project, and then click Assignments > Pin Planner.
Click Processing > Start Analysis & Elaboration to elaborate the design and display All Pins in the device view.
To locate or highlight pins
for assignment, click Pin Finder or a pin
type under Highlight Pins in the Tasks pane.
(Optional) To define a
custom group of nodes for assignment, select one or more nodes in the Groups or All
Pins list, and click Create
Enter assignments of
logic, I/O standards, interface IP, and properties for device I/O pins in the
All Pins spreadsheet, or by dragging
into the package view.
To assign properties
to differential pin pairs, click Show Differential
Pin Pair Connections. A red connection line appears between
positive (p) and negative (n) differential pins.
(Optional) To create board trace model assignments:
Right-click an output or bidirectional pin, and click Board Trace Model. For differential I/O
standards, the board trace model uses a differential pin pair with two
symmetrical board trace models.
Specify board trace parameters on the positive end of the differential
pin pair. The assignment applies to the corresponding value on the
negative end of the differential pin pair.
To run a full I/O
assignment analysis, click Run I/O Assignment
Analysis. The Fitter reports analysis results. Only reserved pins
are analyzed prior to design synthesis.
Assigning to Exclusive Pin Groups
You can designate groups of pins for exclusive assignment. When you
assign pins to an
Exclusive I/O Group, the Fitter does not place the
signals in the same I/O bank with any other exclusive I/O group. For example,
if you have a set of signals assigned exclusively to
group_a, and another set of signals assigned to
group_b, the Fitter ensures placement of each group in
different I/O banks.
Assigning Slew Rate and Drive Strength
You can designate the device pin slew rate and drive strength. These
properties affect the pin’s outgoing signal integrity. Use either the Slew Rate or Slow Slew
Rate assignment to adjust the drive strength of a pin with the Current Strength assignment.
Note: The slew rate and drive strength apply
during I/O assignment analysis.
Assigning Differential Pins
When you assign a differential I/O standard to a single-ended top-level pin in
your design, the Pin Planner automatically recognizes the negative pin as part of the
differential pin pair assignment and creates the negative pin for you. The
Quartus® Prime software writes the location assignment for the
negative pin to the .qsf; however, the I/O standard
assignment is not added to the .qsf for the negative
pin of the differential pair.
The following example shows a design with lvds_in top-level pin, to which you assign a differential I/O standard.
The Pin Planner automatically creates the differential pin, lvds_in(n) to complete the differential pin pair.
Note: If you have a single-ended clock that feeds a
PLL, assign the pin only to the positive clock pin of a differential pair in the target
device. Single-ended pins that feed a PLL and are assigned to the negative clock pin
device cause the design to not fit.
Figure 6. Creating a Differential Pin Pair in the Pin Planner
If your design contains a large bus that exceeds the pins available in a
particular I/O bank, you can use edge location assignments to place the bus. Edge
location assignments improve the circuit board routing ability of large buses, because
they are close together near an edge. The following figure shows Intel device package edges.
Figure 7. Die View and Package View of the Four Edges on an Intel Device
Overriding I/O Placement Rules on Differential Pins
I/O placement rules ensure that noisy signals do not corrupt neighboring
signals. Each device family has predefined I/O placement rules.
I/O placement rules define, for example, the allowed placement of
single-ended I/O with respect to differential pins, or how many output and bidirectional
pins you can place within a VREF group when using voltage referenced input
Use the IO_MAXIMUM_TOGGLE_RATE assignment to override I/O
placement rules on pins, such as system reset pins that do not switch during normal
design activity. Setting a value of 0 MHz for this assignment causes the Fitter to
recognize the pin at a DC state throughout device operation. The Fitter excludes the
assigned pin from placement rule analysis. Do not assign an
IO_MAXIMUM_TOGGLE_RATE of 0 MHz to any actively switching
pin, or your design may not function as you intend.
Entering Pin Assignments with Tcl Commands
You can apply pin assignments with Tcl scripts, by either entering
individual Tcl commands in the Tcl Console, or creating a .tcl
script and the typing the following in the command line:
Applying Tcl Script Assignments
quartus_sh -t <my_tcl_script>.tcl
Scripted Pin Assignment
The following example uses set_location_assignment and set_instance_assignment Tcl commands to assign a pin to a specific
location, I/O standard, and drive strength.
You can use synthesis attributes or low‑level I/O primitives to embed
I/O pin assignments directly in your HDL code. When you analyze and synthesize
the HDL code, the information is converted into the appropriate I/O pin
assignments. You can use either of the following methods to specify pin‑related
assignments with HDL code:
attributes for signal names that are top‑level pins
Using low‑level I/O
primitives, such as ALT_BUF_IN, to specify input, output, and differential
buffers, and for setting parameters or attributes
Using Synthesis Attributes
Quartus® Prime software translates
synthesis attributes into standard assignments during compilation.
assignments appear in the Pin Planner.
Quartus® Prime synthesis
supports the chip_pin, useioff,
and altera_attribute synthesis attributes.
If you modify or delete these assignments in the Pin Planner and then
recompile your design, the Pin Planner changes override the synthesis attributes.
Use the altera_attribute synthesis
attribute to create other pin‑related assignments in your HDL code. The altera_attribute attribute
all types of instance assignments. The following examples use the altera_attribute attribute to embed Fast Input
Register logic option assignments and I/O standard assignments in both a
Verilog HDL and a VHDL design file.
Synthesis Attribute in Verilog HDL
entity my_entity is
my_pin1: in std_logic
architecture rtl of my_entity is
attribute altera_attribute : string;
attribute altera_attribute of my_pin1: signal is "-name FAST_INPUT_REGISTER ON;
-- The architecture body
Use the chip_pin and useioff synthesis attributes to create pin location assignments and to assign
Fast Input Register, Fast Output Register, and Fast Output Enable
Register logic options. The following examples use the chip_pin and useioff attributes to embed
location and Fast Input Register logic option
assignments in Verilog HDL and VHDL design files.
chip_pin Synthesis Attributes in VHDL
entity my_entity is
my_pin1: in std_logic
architecture rtl of my_entity is
attribute useioff : boolean;
attribute useioff of my_pin1 : signal is true;
attribute chip_pin : string;
attribute chip_pin of my_pin1 : signal is "C1";
begin -- The architecture body
You can alternatively enter I/O pin assignments using low-level I/O primitives.
You can assign pin locations, I/O standards, drive strengths, slew rates, and on-chip
termination (OCT) value assignments. You can also use low-level differential I/O
primitives to define both positive and negative pins of a differential pair in the HDL
code for your design.
Primitive-based assignments do not appear in the Pin Planner until after you
perform a full compilation and back-annotate pin assignments (Assignments > Back Annotate Assignments).
Quartus® Prime software supports transfer
of I/O pin assignments across projects, or for analysis in third-party PCB tools. You
can import or export I/O pin assignments in the following ways:
Table 5. Importing and Exporting I/O Pin Assignments
your PCB design tool or spreadsheet into Pin Planner during
early pin planning or after optimization in PCB tool
Quartus® Prime project with
Quartus® Prime project for
optimization in a PCB design tool
Quartus® Prime project for
spreadsheet analysis or use in scripting assignments
Quartus® Prime project for
import into another
project with similar constraints
Assignments > Import Assignments
Assignments > Export Assignments
.qsf, .esf, .acf, .csv,
files retain column and row order and format. Do not modify the row
of column headings if importing the .csv file
Importing and Exporting for PCB Tools
The Pin Planner supports import and export of assignments with PCB
tools. You can export valid assignments as a
.pin file for analysis in other supported PCB
tools. You can also import optimized assignment from supported PCB tools. The
.pin file contains pin name, number, and detailed
I/O Designer requires you to generate and import both an .fx and a .pin file to transfer assignments. However, the
Quartus® Prime software requires only the
.fx to import pin assignments from I/O Designer.
Table 6. Contents of .pin File
File Column Name
The name of the design pin, or whether the pin is GND or
The pin number of the location on the device package
The direction of the pin
The name of the I/O standard to which the pin is configured
The voltage level that is required to be connected to the pin
The I/O bank to which the pin belongs
Y or N indicating if the location assignment for the design pin
was user assigned (Y) or assigned by the Fitter (N)
Click View > Pin Migration Window to verify whether pin assignments are compatible with migration to a different Intel device.
You can migrate compatible pin assignments from one target device to
another. You can migrate to a different density and the same device package. You can
also migrate between device packages with different densities and pin counts.
Quartus® Prime software ignores invalid
assignments and generates an error message during compilation. After evaluating
migration compatibility, modify any incompatible assignments, and then click Export to export the assignments to another project.
Figure 8. Device Migration Compatibility (AC24 does not exist in migration
The migration result for the pin function of highlighted PIN_AC23 is not an NC but a voltage reference VREFB1N2 even though the pin is an NC in the migration device. VREF standards have a higher priority than an NC, thus the migration result displays the voltage reference. Even if you do not use that pin for a port connection in the design, you must use the VREF standard for I/O standards that require it on the actual board for the migration device.
If one of the migration devices has pins intended for connection to VCC or GND and these same pins are I/O pins on a different
device in the migration path, the
Quartus® Prime software
ensures these pins are not used for I/O. Ensure that these pins are connected to the
correct PCB plane.
When migrating between two devices in the same package, pins that are not connected to the smaller die may be intended to connect to VCC or GND on the larger die. To facilitate migration, you can connect these pins to VCC or GND in the original design because the pins are not physically connected to the smaller die.
Quartus® Prime software validates I/O pin
assignments against predefined I/O rules for your target device. You can use the
following tools to validate your I/O pin assignments throughout the pin planning
Table 7. I/O Validation Tools
I/O Validation Tool
Click to Run
I/O Assignment Analysis
Verifies I/O assignment legality of synthesized
design against full set of I/O rules for the target device
Processing > Start I/O Assignment
Advanced I/O Timing
Fully validates I/O assignments against all I/O and
timing checks during compilation
Processing > Start Compilation
I/O Assignment Validation Rules
I/O Assignment Analysis validates your assignments against the following
Table 8. Examples of I/O Rule Checks
I/O bank capacity
Checks the number of pins assigned to an I/O bank against the
number of pins allowed in the I/O bank.
I/O bank VCCIO voltage compatibility
Checks that no more than one VCCIO is required for the pins
assigned to the I/O bank.
I/O bank VREF voltage compatibility
Checks that no more than one VREF is required for the pins
assigned to the I/O bank.
I/O standard and location conflicts
Checks whether the pin location supports the assigned I/O
I/O standard and signal direction conflicts
Checks whether the pin location supports the assigned I/O
standard and direction. For example, certain I/O standards on a particular pin
location can only support output pins.
Differential I/O standards cannot have open drain turned on
Checks that open drain is turned off for all pins with a
differential I/O standard.
I/O standard and drive strength conflicts
Checks whether the drive strength assignments are within the
specifications of the I/O standard.
Drive strength and location conflicts
Checks whether the pin location supports the assigned drive
BUSHOLD and location conflicts
Checks whether the pin location supports BUSHOLD. For example,
dedicated clock pins do not support BUSHOLD.
WEAK_PULLUP and location conflicts
Checks whether the pin location supports WEAK_PULLUP (for
example, dedicated clock pins do not support WEAK_PULLUP).
Checks whether combined drive strength of consecutive pads
exceeds a certain limit. For example, the total current drive for 10
consecutive pads on a
Stratix® II device cannot exceed 200 mA.
PCI_IO clamp diode, location, and I/O standard conflicts
Checks whether the pin location along with the I/O standard
assigned supports PCI_IO clamp diode.
SERDES and I/O pin location compatibility check
Checks that all pins connected to a SERDES in your design are
assigned to dedicated SERDES pin locations.
PLL and I/O pin location compatibility check
Checks whether pins connected to a PLL are assigned to the
dedicated PLL pin locations.
Table 9. Signal Switching Noise Rules
I/O bank cannot have single-ended I/O when DPA exists
Checks that no single-ended I/O pin exists in the same I/O bank
as a DPA.
A PLL I/O bank does not support both a single-ended I/O and a
differential signal simultaneously
Checks that there are no single-ended I/O pins present in the
PLL I/O Bank when a differential signal exists.
Single-ended output is required to be a certain distance away
from a differential I/O pin
Checks whether single-ended output pins are a certain distance
away from a differential I/O pin.
Single-ended output must be a certain distance away from a VREF pad
Checks whether single-ended output pins are a certain distance
away from a VREF pad.
Single-ended input is required to be a certain distance away
from a differential I/O pin
Checks whether single-ended input pins are a certain distance
away from a differential I/O pin.
Too many outputs or bidirectional pins in a VREFGROUP when a
VREF is used
Checks that there are no more than a certain number of outputs
or bidirectional pins in a VREFGROUP when a VREF is used.
Too many outputs in a VREFGROUP
Checks whether too many outputs are in a VREFGROUP.
Checking I/O Pin Assignments in Real-Time
Live I/O check validates I/O assignments against basic I/O buffer rules in real
time. The Pin Planner immediately reports warnings or errors about assignments as you
enter them. The Live I/O Check Status window displays the total number of errors and
warnings. Use this analysis to quickly correct basic errors before proceeding. Run full
I/O assignment analysis when you are ready to validate pin assignments against the
complete set of I/O system rules.
Note: Live I/O check is supported only for
MAX® II, and
Stratix® IV device families.
Live I/O check validates against the following basic I/O buffer rules:
voltage compatibility rules
Output (SSO) rules
I/O property compatibility
rules, such as drive strength compatibility, I/O standard compatibility,
PCI_IO clamp diode compatibility, and I/O direction
Illegal location assignments:
An I/O bank or VREF group with no
The negative pin of a differential
pair if the positive pin of the differential pair is assigned with a node
name with a differential I/O standard
Pin locations that do not support
the I/O standard assigned to the selected node name
For HSTL- and SSTL-type I/O
standards, VREF groups of a different VREF
voltage than the selected node name.
I/O Assignment Analysis
I/O assignment analysis validates I/O assignments against the complete
set of I/O system and board layout rules. Full I/O assignment analysis
validates blocks that directly feed or are fed by resources such as a PLL,
LVDS, or gigabit transceiver blocks. In addition, the checker validates the
legality of proper
VREF pin use, pin locations, and acceptable mixed I/O
Run I/O assignment analysis during early pin planning to validate
initial reserved pin assignments before compilation. Once you define design
files, run I/O assignment analysis to perform more thorough legality checks
with respect to the synthesized netlist. Run I/O assignment analysis whenever
you modify I/O assignments.
The Fitter assigns pins to accommodate your constraints. For example, if you
assign an edge location to a group of LVDS pins, the Fitter assigns pin locations for
each LVDS pin in the specified edge location and then performs legality checks. To
display the Fitter-placed pins, click Show Fitter
Placements in the Pin Planner. To accept these suggested pin locations,
you must back-annotate your pin assignments.
View the I/O Assignment Warnings report to view and resolve all assignment
warnings. For example, a warning that some design pins have undefined drive strength or
slew rate. The Fitter recognizes undefined, single-ended output and bidirectional pins
as non-calibrated OCT. To resolve the warning, assign the Current Strength, Slew Rate or
Slow Slew Rate for the reported pin.
Alternatively, can assign the Termination to the
pin. You cannot assign drive strength or slew rate settings when a pin has an OCT
Early I/O Assignment Analysis Without Design Files
You can perform basic I/O legality checks before defining HDL design files. This technique produces a preliminary board layout. For example, you can specify a target device and enter pin assignments that correspond to PCB characteristics. You can reserve and assign I/O standards to each pin, and then run I/O assignment analysis to ensure that there are no I/O standard conflicts in each I/O bank.
Figure 9. Assigning and Analyzing Pin-Outs without Design Files
You must reserve all pins you intend to use as I/O pins, so that the
Fitter can determine each pin type. After performing I/O assignment analysis,
correct any errors reported by the Fitter and rerun I/O assignment analysis
until all errors are corrected. A complete I/O assignment analysis requires all
I/O Assignment Analysis With Design Files
I/O assignment analysis allows you to perform full I/O legality checks after fully defining HDL design files. When you run I/O assignment analysis on a complete design, the tool verifies all I/O pin assignments against all I/O rules. When you run I/O assignment analysis on a partial design, the tool checks legality only for defined portions of the design. The following figure shows the work flow for analyzing pin-outs with design files.
Figure 10. I/O Assignment Analysis Flow
Even if I/O assignment analysis passes on incomplete design files, you may still encounter errors during full compilation. For example, you can assign a clock to a user I/O pin instead of assigning to a dedicated clock pin, or design the clock to drive a PLL that you have not yet instantiated in the design. This issues occur because I/O assignment analysis does not account for the logic that the pin drives and does not verify that only dedicated clock inputs can drive the a PLL clock port.
To obtain better coverage, analyze as much of the design as possible
over time, especially logic that connects to pins. For example, if your design
includes PLLs or LVDS blocks, define these files prior to full analysis. After
performing I/O assignment analysis, correct any errors reported by the Fitter
and rerun I/O assignment analysis until all errors are corrected.
The following figure shows the compilation time benefit of performing
I/O assignment analysis before running a full compilation.
Figure 11. I/O Assignment Analysis Reduces Compilation Time
Overriding Default I/O Pin Analysis
You can override the default I/O analysis of pins to accommodate I/O
rule exceptions, such as for analyzing VREF or inactive pins.
Each device contains VREF pins, each supporting one or more I/O pins. A VREF pin and its I/O pins comprise a VREF bank. The VREF pins are typically assigned inputs with VREF I/O standards, such as HSTL- and SSTL-type I/O standards. Conversely, VREF outputs do not require the VREF pin. When a voltage-referenced input is present in a VREF bank, only a certain number of outputs can be present in that VREF bank. I/O assignment analysis treats bidirectional signals controlled by different output enables as independent output enables.
To assign the Output Enable
Group option to bidirectional signals to analyze the signals as a
single output enable group, follow these steps:
To access this assignment in the Pin Planner, right-click the All pins list and click Customize Columns.
Under Available columns, add Output Enable Group to Show these columns in this order. The column appears in the All Pins list.
Enter the same integer value for the Output Enable Group assignment for all sets of signals that are driving in the same direction.
The detailed I/O assignment analysis reports include the affected pin
name and a problem description. The Fitter section of the Compilation report
contains information generated during I/O assignment analysis, including the
Warnings—lists warnings generated for each pin
use of various pin types and I/O banks
I/O Rules Section—lists
summary, details, and matrix information about the I/O rules tested
The Status column indicates whether rules
passed, failed, or were not checked. A severity rating indicates the rule’s importance
for effective analysis. “Inapplicable” rules do not apply to the target device family.
Figure 12. I/O Rules Matrix
Verifying I/O Timing
You must verify board-level signal integrity and I/O timing when
assigning I/O pins.
High-speed interface operation requires a quality signal
and low propagation delay at the far end of the board route. Click Tools > Timing Analyzer to confirm timing after making I/O pin assignments.
For example, if you change the slew rates or drive strengths of some I/O pins
with ECOs, you can verify timing without recompiling the design. You must understand I/O
timing and what factors affect I/O timing paths in your design. The accuracy of the
output load specification of the output and bidirectional pins affects the I/O timing
Quartus® Prime software supports three
different methods of I/O timing analysis:
Table 10. I/O Timing Analysis Methods
I/O Timing Analysis
Advanced I/O timing analysis
Analyze I/O timing with your board trace model to
report accurate, “board-aware” simulation models. Configures a
complete board trace model for each I/O standard or pin. Timing Analyzer
applies simulation results of the I/O buffer, package, and board
trace model to generate accurate I/O delays and system level signal
information. Use this information to improve timing and signal
I/O timing analysis
Analyze I/O timing with default or specified
capacitive load without signal integrity analysis. Timing Analyzer reports
tCO to an I/O pin using a default or user-specified value for a
Full board routing simulation
Use Intel-provided or
software-generated IBIS or HSPICE I/O models for simulation in
Note: Advanced I/O timing
analysis is supported only for .28nm and larger device families. For devices that
support advanced I/O timing, it is the default method of I/O timing analysis. For all
other devices, you must use a default or user-specified capacitive load assignment to
determine tCO and power measurements.
For more information about advanced I/O timing support, refer to the
appropriate device handbook for your target device. For more information about
board-level signal integrity and tips on how to improve signal integrity in your
high-speed designs, refer to the Altera Signal Integrity Center page of the Altera
For information about creating IBIS and HSPICE models with the
Quartus® Prime software and integrating those models into
HyperLynx* and HSPICE simulations, refer to the Signal Integrity
Analysis with Third Party Tools chapter.
Advanced I/O timing analysis uses your board trace model and termination
network specification to report accurate output buffer-to-pin timing estimates,
FPGA pin and board trace signal integrity and delay values. Advanced I/O timing
runs automatically for supported devices during compilation.
Board Trace Models
Quartus® Prime software provides board trace model templates for various I/O standards.
The following figure shows the template for a 2.5 V I/O standard. This model consists of near-end and far-end board component parameters.
Near-end board trace modeling includes the elements which are close to the device. Far-end modeling includes the elements which are at the receiver end of the link, closer to the receiving device. Board trace model topology is conceptual and does not necessarily match the actual board trace for every component. For example, near-end model parameters can represent device-end discrete termination and breakout traces. Far-end modeling can represent the bulk of the board trace to discrete external memory components, and the far end termination network. You can analyze the same circuit with near-end modeling of the entire board, including memory component termination, and far-end modeling of the actual memory component.
Figure 13. 2.5-V I/O Standard Board Trace Model
The following figure shows the template for the LVDS I/O standard. The far-end capacitance (Cf) represents the external-device or multiple-device capacitive load. If you have multiple devices on the far-end, you must find the equivalent capacitance at the far-end, taking into account all receiver capacitances. The far-end capacitance can be the sum of all the receiver capacitances.
Quartus® Prime software models of transmission lines do not consider transmission-line resistance (lossless models). You only need to specify distributed inductance (L) and capacitance (C) values on a per-inch basis, which you can obtain from the PCB vendor or manufacturer, the CAD Design tool, or a signal integrity tool, such as the
Figure 14. LVDS Differential Board Trace Model
Defining the Board Trace Model
The board trace model describes a board
trace and termination network as a set of capacitive, resistive, and inductive
Advanced I/O Timing uses the model to simulate the output signal from the
output buffer to the far end of the board trace. You can define the capacitive load, any
termination components, and trace impedances in the board routing for any output pin or
bidirectional pin in output mode. You can configure an overall board trace model for
each I/O standard or for specific pins. Define an overall board trace model for each I/O
standard in your design. Use that model for all pins that use the I/O standard. You can
customize the model for specific pins using the Board Trace
Model window in the Pin Planner.
Click Assignments > Device > Device and Pin Options.
Click Board Trace Model and define board trace model values
for each I/O standard.
Timing and define default I/O timing options at board trace near and
Click Assignments > Pin Planner and assign board trace model values to individual pins.
Specifying Board Trace Model
## setting the near end series resistance model of sel_p output pin to 25 ohms
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R 25 -to se1_p
## Setting the far end capacitance model for sel_p output signal to 6 picofarads
set_instance_assignment -name BOARD_MODEL_FAR_C 6P -to se1_p
Modifying the Board Trace Model
To modify the board trace model, click
View > Board Trace Model in the Pin Planner.
You can modify any of the board trace
model parameters within a graphical representation of the board trace model.
The Board Trace Model window displays the routing and components for
positive and negative signals in a differential signal pair. Only modify the positive
signal of the pair, as the setting automatically applies to the negative signal. Use
standard unit prefixes such as p, n, and k to represent pico, nano, and kilo, respectively. Use the short or open value to
designate a short or open circuit for a parallel component.
Specifying Near-End vs Far-End I/O Timing Analysis
You can select a near-end or far-end point for I/O timing analysis. Near-end
timing analysis extends to the device pin. You can apply the set_output_delay constraint during near-end analysis to account for the
delay across the board.
With far-end I/O timing analysis, the advanced I/O timing analysis extends to
the external device input, at the far-end of the board trace. Whether you choose a
near-end or far-end timing endpoint, the board trace models are taken into account
during timing analysis.
Advanced I/O Timing Analysis Reports
The following reports show advanced I/O timing analysis information:
Table 11. Advanced I/O Timing Reports
I/O Timing Report
Timing Analyzer Report
Reports signal integrity and board delay data.
Board Trace Model Assignments report
Summarizes the board trace model component settings for each
output and bidirectional signal.
Signal Integrity Metrics report
Contains all the signal integrity metrics calculated during
advanced I/O timing analysis based on the board trace model settings for each
output or bidirectional pin. Includes measurements at both the FPGA pin and at
the far-end load of board delay, steady state voltages, and rise and fall
Note: By default, the Timing Analyzer generates the Slow‑Corner Signal
Integrity Metrics report. To generate a Fast-Corner Signal Integrity Metrics
report you must change the delay model by clicking
Tools > Timing
Adjusting I/O Timing and Power with Capacitive Loading
When calculating tCO and power for output and
bidirectional pins, the Timing Analyzer and the Power Analyzer use a bulk capacitive
load. You can adjust the value of the capacitive load per I/O standard to obtain more
precise tCO and power measurements, reflecting the behavior of
the output or bidirectional net on your PCB. The
Quartus® Prime software ignores capacitive load settings on input pins. You can
adjust the capacitive load settings per I/O standard, in picofarads (pF), for your
entire design. During compilation, the Compiler measures power and tCO measurements based on your settings. You can also adjust the capacitive
load on an individual pin with the Output Pin Load
Viewing Routing and Timing Delays
Right-click any node and click
Locate > Locate in Chip Planner
to visualize and adjust I/O timing delays and routing between
user I/O pads and VCC, GND, and VREF pads. The Chip
Planner graphically displays logic placement, Logic Lock (Standard) regions, relative
resource usage, detailed routing information, fan-in and fan-out, register
paths, and high-speed transceiver channels. You can view physical timing
estimates, routing congestion, and clock regions. Use the Chip Planner to
change connections between resources and make post-compilation changes to logic
cell and I/O atom placement. When you select items in the Pin Planner, the
corresponding item is highlighted in Chip Planner.
Analyzing Simultaneous Switching Noise
Processing > Start > Start SSN Analyzer
to estimate the voltage noise for each pin in the design. The
simultaneous switching noise (SSN) analysis accounts for the pin placement, I/O
standard, board trace, output enable group, timing constraint, and PCB
characteristics that you specify. The analysis produces a voltage noise
estimate for each pin in the design. View the SSN results in the Pin Planner
and adjust your I/O assignments to optimize signal integrity.
Quartus® Prime software allows you to access I/O management functions through Tcl commands, rather than with the GUI. For detailed information about scripting command options and Tcl API packages, type the following at a system command prompt to view the Tcl API Help browser:
Valid locations are pin locations, I/O bank locations, or edge
locations. Pin locations include pin names, such as
PIN_A3. I/O bank locations include
IOBANK_1 up to
n is the number of I/O banks in the device.
Use one of the following valid edge location values:
Exclusive I/O Group
The following Tcl command creates an exclusive I/O group assignment: