Ethernet Link Inspector User Guide for Intel Stratix 10 Devices

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UG-20190 | 2019.07.01

Overview of Ethernet Link Inspector for Intel Stratix 10 Devices

The Ethernet Link Inspector is an inspection tool that can continuously monitor an Ethernet link that contains an Ethernet IP, which includes Ethernet lane alignment status, clock data recover (CDR) lock, media access controller (MAC) statistics, Forward Error Correction (FEC) statistics, and others. If needed, the Ethernet Link Inspector can capture an event with the help of Signal Tap Logic Analyzer to further examine the link behavior during Auto Negotiation (AN), Link Training (LT), or any other event during the link operation. The Ethernet Link Inspector also creates a graphical user interface (GUI) to represent the link behavior.

Features

The Ethernet Link Inspector consists of two modules:

Link Monitor
Link Analysis

The following sections describe in detail the features of each module.

Link Monitor

The link monitor module performs real-time status monitoring of an Ethernet IP link.

It continuously reads and displays all of the required status registers related to the Ethernet IP link. The Link Monitor helps to ensure that all of the Ethernet IP link status at various stages are valid. In case of any failure, it narrows down to the type of failure based on the various status bits, which are based in the register bank of an Ethernet IP core. For more information on the register map, refer to respective Ethernet IP user guide.

Examples of the Ethernet link status displayed on the Link Monitor user interface include:

State of Ethernet IP link (Up or Down)
State of AN and LT process (Active or Done)
Number of correct frames received
Number of frame errors
Transmitted and recovered clock frequencies etc.

Because the Link Monitor gives out real time link status through Ethernet IP registers, it needs to have a connection with the device that is powered on and configured with the appropriate design file.

Link Analysis

The Link Analysis module displays a sequence of events on an Ethernet IP link, which occurred in a finite duration of time.

The Link Analysis relies on Signal Tap Logic Analyzer to capture and store database (.csv) of all required signals. Once the Signal Tap Logic Analyzer creates a database, the Link Analysis performs an analysis on the database to extract all the required information and displays them in a user-friendly graphical user interface (GUI).

The features of the Link Analysis include:

Ability to capture and display events that occur during Ethernet IP link bring-up. For example, Auto Negotiation and Link Training.
Ability to capture the link behavior at an intended trigger point and analyze link behavior around that time period.

Supported IP Cores and Devices

Table 1. Ethernet Link Inspector Supported IP Cores for Intel^® Stratix^® 10 L-, H-, and E-tile Devices
Device	IP Core	Data Rate (Gbps)	IP Type	Auto Negotiation and Link Training ¹	FEC ¹	Link Monitor	Link Analysis
Intel^® Stratix^® 10 L-tile	10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP	10	Soft	Yes	Fire code (2112,2080)	Yes	Yes
	25G Ethernet Intel^® FPGA IP	25	Soft	N/A	RS-FEC (528,514)	Yes	N/A
	Low Latency 40G Ethernet Intel^® FPGA IP	40	Soft	Yes	Fire code (2112,2080)	Yes	Yes
	Low Latency 100G Ethernet Intel^® FPGA IP	100	Soft	Yes	RS-FEC (528,514)	Yes	Yes
Intel^® Stratix^® 10 H-tile	10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP	10	Soft	Yes	Fire code (2112,2080)	Yes	Yes
	25G Ethernet Intel^® FPGA IP	25	Soft	N/A	RS-FEC (528,514)	Yes	N/A
	Low Latency 40G Ethernet Intel^® FPGA IP	40	Soft	Yes	Fire code (2112,2080)	Yes	Yes
	Low Latency 100G Ethernet Intel^® FPGA IP	100	Soft	Yes	RS-FEC (528,514)	Yes	Yes
	H-tile Hard IP for Ethernet Intel^® FPGA IP	50	Hard	Yes	N/A	Yes	Yes
	H-tile Hard IP for Ethernet Intel^® FPGA IP	100	Hard	Yes	N/A	Yes	Yes
Intel^® Stratix^® 10 E-tile	E-tile Hard IP for Ethernet Intel^® FPGA IP	10	Hard	Yes	N/A	Yes	N/A
		25	Hard	Yes	RS-FEC (528,514)	Yes	N/A
		100 (25Gx4 - NRZ)	Hard	Yes	RS-FEC (528,514)	Yes	N/A
		100 (50Gx2 - PAM4)	Hard	Yes	RS-FEC (544,514)	Yes	N/A

¹ Feature details here shows support model for the IP and not the Ethernet Link Inspector support.

Setting Up the Ethernet Link Inspector

This section describes how to set up and run the Ethernet Link Inspector for Intel^® Stratix^® 10 devices.

System Requirements and Prerequisites

System Requirements

To run this version of Ethernet Link Inspector for Intel^® Stratix^® 10 devices, your system must meet the following hardware and software requirements:

Windows PC or Linux workstation.
Intel^® Quartus^® Prime Pro Edition software version 19.1 and later.

For earlier versions of the Intel^® Quartus^® Prime Pro Edition software, refer to the relevant user guide listed in the Ethernet Link Inspector User Guide Archives chapter.

Enabling Your Design For the Link Monitor

To enable the use of Link Monitor, your design must instantiate JTAG to Avalon^® Master Bridge. The availability of the JTAG to Avalon^® Master bridge in the Intel^® Stratix^® 10 Ethernet IP cores is shown in the following table.

Table 2. Availability of JTAG to Avalon^® Master Bridge in Intel^® Stratix^® 10 Ethernet IP Cores
Device	IP Core	Data Rate (Gbps)	IP Type	Design Example ²	Standalone IP ³
Intel^® Stratix^® 10 L-Tile	10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP	10	Soft	Yes	Yes
	25G Ethernet Intel^® FPGA IP	25	Soft	Yes	N/A
	Low Latency 40G Ethernet Intel^® FPGA IP	40	Soft	Yes	Yes
	Low Latency 100G Ethernet Intel^® FPGA IP	100	Soft	Yes	Yes
Intel^® Stratix^® 10 H-Tile	10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP	10	Soft	Yes	Yes
	25G Ethernet Intel^® FPGA IP	25	Soft	Yes	N/A
	Low Latency 40G Ethernet Intel^® FPGA IP	40	Soft	Yes	Yes
	Low Latency 100G Ethernet Intel^® FPGA IP	100	Soft	Yes	Yes
	H-Tile Hard IP for Ethernet Intel^® FPGA IP	50	Hard	Yes	Yes
	H-Tile Hard IP for Ethernet Intel^® FPGA IP	100	Hard	Yes	Yes
Intel^® Stratix^® 10 E-Tile	E-Tile Hard IP for Ethernet Intel^® FPGA IP	10	Hard	Yes	Yes
		25	Hard	Yes	Yes
		100 (25Gx4-NRZ)	Hard	Yes	Yes
		100 (50Gx2-PAM4)	Hard	Yes	Yes

² Design examples generated in Intel^® Quartus^® Prime Pro Edition software are instantiated with JTAG to Avalon^® Master Bridge. These design examples also include Ethernet Packet Generators that can be controlled using the Link Monitor.

³ Supported standalone IPs provide an option called Enable JTAG to Avalon^® Master Bridge in the respective IP Parameter Editor GUI in Intel^® Quartus^® Prime Pro Edition software. The selection of this option automatically includes JTAG to Avalon^® Master Bridge during IP generation. This JTAG to Avalon^® Master Bridge do not provide access to Packet Generators, which is originally part of design example. For non-supported standalone IPs, the JTAG to Avalon^® Master Bridge has to be manually instantiated from the IP Catalog. Refer to respective IP design example RTL and user guides for more details on IP connections.

Running the Ethernet Link Inspector

The Link Monitor and Link Analysis of the Ethernet Link Inspector can be used independently for inspecting Ethernet links of the supported IP cores.

You can run the Ethernet Link Inspector using System Console in the Intel^® Quartus^® Prime Pro Edition software. There are two separate Launch buttons to open Link Analysis and Link Monitor of the Ethernet Link Inspector as shown in the following figure.

Running the Link Monitor

Perform the following steps to launch the Link Monitor module.

Example Link Monitor Tab

In the Intel^® Quartus^® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
In the system console, click the Launch button under the Ethernet Link Inspector - Link Monitor section to run the Link Monitor module. The Ethernet Link Inspector - Link Monitor tab appears.

Note: You can open multiple instances of the Link Monitor module simultaneously for different IPs.
In the Ethernet Link Inspector - Link Monitor tab, follow these steps to set the correct JTAG to Avalon^® Master path:
1. Load the Programming File (*.sof) in System Console by clicking File > Load Design for the detailed JTAG to Avalon^® Master path.
2. Select List JTAG Masters to see all available JTAG to Avalon^® Master paths.
3. Select a JTAG to Avalon^® Master path number from the drop-down box and click Set JTAG Master.
  Note: The instance name of the JTAG to Avalon^® Master path is displayed along with the text FULL_HPATH (marked by the blue box in the figure below). Select the JTAG to Avalon^® Master path number that has the instance name of the JTAG to Avalon^® Master path connected to the Ethernet IP.
  
  Figure 1. Example JTAG Master Selection Panel
4. From the Select IP Variant drop-down list, select an IP Variant and click Launch to populate the user interface of the Link Monitor.

Running the Link Analysis

Perform the following steps to launch the Link Analysis module.

Example Link Analysis Tab

In the Intel^® Quartus^® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
In the system console, click the Launch button under the Ethernet Link Inspector - Link Analysis section to run the Link Analysis module. The Ethernet Link Inspector - Link Analysis tab appears.

Note: You can open multiple instances of the Link Analysis module simultaneously for different IPs.
In the Ethernet Link Inspector - Link Analysis tab, select the target IP core from the drop-down box.
Click the Select .csv file button to import the Signal Tap database (.csv) file. Refer to the Creating and Capturing Signal Tap Database and Exporting as CSV File section in this user guide to create the .csv file. In the Status Bar, make sure the directory to the imported database is correct.
Click the Start Analysis button.

Note: If you want the summary of the Ethernet link capture without using the Link Analysis, enter a report name and click Generate Report button to create a report (.csv) file. This feature is supported only for 10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP and Intel^® Stratix^® 10 Low Latency 40G Ethernet Intel^® FPGA IP.

You can now use the Link Analysis to analyze the Signal Tap database.

Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File

Creating a Signal Tap (.stp) File

To create a Signal Tap file, follow these steps:

To create .stp file with the list of expected signals for a specific Ethernet IP core, refer to the document Link_Analysis_STP_RequiredSignals.xlsx provided in the Ethernet_Link_Inspector_Package.zip file.
For design examples, use the Signal Tap files provided in the Ethernet_Link_Inspector_Package.zip file to capture a Signal Tap file.

Capturing a Signal Tap (.stp) File

To capture a Signal Tap file (i.e., link bring up sequence after reset that includes Auto Negotiation and Link Training), follow these steps:

Program the .sof file using the Intel^® Quartus^® Prime Pro Edition software.
Double click on the created .stp file associated with the .sof file to open the Signal Tap Logic Analyzer.
Clear the .stp file so that it does not contain any previous captured data by holding the IP into reset and clicking Run Analysis, followed by Stop Analysis on the Signal Tap Logic Analyzer toolbar.
The IP can be reset by using either of the following two methods:
1. Using the Link Monitor, click once on Assert Full System Reset in the Resets panel under the MAC & PCS tab.
2. Direct access to reset ports or registers.
Using the Link Monitor, maintain the IP reset by clicking once on Assert Full System Reset in the Reset panel under the MAC & PCS tab.
To start the Signal Tap data capture, click Run Analysis in the Signal Tap Logic Analyzer.
Using the Link Monitor, release the IP reset by clicking once on Deassert Full System Reset in the Reset panel under the MAC & PCS tab.
Note: The Signal Tap Logic Analyzer may not stop automatically after releasing reset if the captured data is not enough to completely fill the memory. If the Signal Tap capture does not stop on its own, follow the steps below:
1. Wait 2 to 5 seconds.
2. Click Stop Analysis on the Signal Tap Logic Analyzer toolbar.

Exporting a Signal Tap Database as Comma Separated Value (`.csv`) File

The Signal Tap Logic Analyzer can save Signal Tap database in a .csv format. After the Signal Tap capture is completed, export the database. Once the database is saved, import the database through Link Analysis for further processing.

To export a Signal Tap data as CSV (.csv) database, follow these steps:

In the Signal Tap Logic Analyzer, select Files > Export to export the captured data.
Specify the File Name, Directory, and Export Format (in .csv file format).
Click OK to generate the .csv database of the captured data.

The Link Analysis reads all the data that are being captured and stored by Signal Tap Logic Analyzer. To prevent processing error, it is important that you export and store the Signal Tap waveform database in .csv format, which contains a list of signals that the Link Analysis expects to receive.

Functional Description

This section describes the various parts of the Ethernet Link Inspector user interface and how each part represents the device behavior. The Ethernet Link Inspector consists of two inspection modules: Link Monitor and Link Analysis.

Link Monitor Module

Link Monitor Tabs and Settings

The Link Monitor module of the Ethernet Link Inspector has three tabs. Each tab implements various Control and Status Registers (CSR) of the selected Ethernet IP core. There is also a Continuous Read All Registers option, which continuously polls the status of all the tabs.

Table 3. Link Monitor GUI Tabs
Tab	Description
MAC & PCS	Resets the IP core, reads the MAC configuration and checks the high level PCS status. Resets: Implements the RESET register. MAC Status: Shows the status of TX MAC registers and RX MAC registers. PCS Status: Shows the status of PCS registers. FEC Status: Shows the status of FEC registers.
Statistics	Displays MAC statistics registers for TX and RX traffic. Displays FEC statistics.
PMA	Displays KR/KR4 registers that includes Auto Negotiation and Link Training. Displays PMA parameters such as differential output voltage (VOD), continuous time linear equalizer (CTLE), distributed feedback equalizer (DFE), and etc.
Help	Displays link bring up guidelines

The following figures show the Link Monitor GUI tabs and are related to the 25G E-tile Hard IP for Ethernet Intel^® FPGA IP. The availability of each tab depends on IP selection and its features.

Figure 2. Example MAC & PCS Tab

Figure 3. Example Statistics Tab

Figure 4. Example PMA Tab

Figure 5. Example Help TabThe Read/Write Register section allows you to read and write values from and to the registers. Register address starts with 0x followed by the effective address. The address includes base address, word offset, and channel offset.

Link Analysis Module

Link Analysis module of the Ethernet Link Inspector plots the behavior of an Ethernet IP link based on specific signals captured from Signal Tap Logic Analyzer.

When an Ethernet IP core is configured in a KR/CR configuration (which includes Auto Negotiation and Link Training), the local device can be in either one of the following four operational modes starting from power-up to the device operation of the IP core:

Sequencer Initialize mode (SEQ_Initialize)
Auto Negotiation mode (Auto_Neg)
Link Training mode (Link_Training)
Data mode (Data)

The local device implements various internal states as part of the Sequencer State Machine to represent the four modes above. The local device may use one or more of the internal states to represent any one of the above mode. Refer to Sequencer State Machine for more details.

Sequencer State Machine

The Ethernet IP cores for Intel^® Stratix^® 10 devices implement an internal state machine called Sequencer State Machine (SSM) that represents the Ethernet IP link bring-up. At any point of time, the device should be in one of SSM states.

Figure 6. Flowchart of SSM StatesThis figure shows the various states of SSM and how these states are mapped to the operational modes.

Table 4. SSM State Descriptions
SSM State	Description
SSM_ENABLE	The first state used for Sequencer State Machine (SSM) initialization. This should be the first state of device after a power cycle or a reset. If Auto Negotiation (AN) and Link Training (LT) are enabled, the local device moves to the SSM_RC_AN state after this state is completes.
SSM_RC_AN	Indicates the reconfiguration of PHY for Auto Negotiation operation.
SSM_AN_ABL	After the completion of SSM_RC_AN state, the local device goes into the SSM_AN_ABL state. In this state, the transmitter of the local device is disabled (i.e., no transitions) so that the Ethernet IP link goes down and the Ethernet IP link partner also goes back to Auto Negotiation. Even without any Ethernet IP link partners connected, the local device should complete this state and move to the next state i.e., SSM_AN_CHK. The local device spends an approximate time of 60 to 75 milliseconds (ms) in this state. At the end of this state, the local device starts sending AN Base Page to the remote device.
SSM_AN_CHK	Once the local device starts sending AN base page, it moves to the state SSM_AN_CHK. The rest of the AN happens in this state. The following are major AN events that happen in this state: Waiting for AN base Page from Remote Device Waiting for an ACK from Remote Device Sending an ACK to Remote Device Doing NEXT PAGE communication (if any) Asserting the `an_done` signal Various events during AN are further categorized into a separate state machine called AN Arbiter State Machine. Refer to Auto Neg Tab for more details.
SSM_RC_LT	Indicates the reconfiguration of PHY for LT operation.
SSM_LT_CHK	After completion of SSM_RC_LT, device goes into SSM_LT_CHK state. This state includes the LT packet communication between the two devices, local and remote. At the end of this state, both devices should have completed LT and acknowledge each other upon completion.
SSM_RC_10G ⁴ SSM_RC_DAT ⁵	Indicates that the reconfiguration of PHY for: 10G/10GFEC mode for 10GBASE-KR operation. 40G/40GFEC mode for 40GBASE-KR4 operation. 50G and 100G modes for H-tile Hard and 100GBASE-KR4 Low Latency operation.
SSM_10G_CHK ⁴ SSM_LNK_CHK ⁵	After the completion of the SSM_RC_10G/SSM_RC_DAT state, the local device goes into the SSM_10G_CHK/SSM_LNK_CHK state. In this state, the local device tries to achieve lock on the received Ethernet packets. The following status signals shows the lock status: 10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP core: `rx_data_ready` For Low Latency 40G Intel^® FPGA IP core: `rpcs_deskew_lock` For Intel^® Stratix^® 10 H-Tile Hard 50G and 100G IP cores: `o_rx_am_lock` For Low Latency 100G Intel^® FPGA IP core: `deskew_lock` The local device will move to the next state called SSM_LNK_RDY when the lock conditions are met. The local device can only remain in this state if the total time, starting from SSM_RC_LT, does not exceed 500 ms. If the total time exceeds 500 ms and the lock conditions are still not met, the local device goes back to SSM_ENABLE state and redo the AN and LT.
SSM_LNK_RDY	Indicates that the local device has successfully locked on to the received Ethernet packets and processed them accordingly. The local device is expected to be in this state during the entire exchange of Ethernet packets unless it losses lock (`rx_data_ready` or `rx_is_lockedtodata`). If the local device losses lock, it goes to the next SSM state called SSM_LR_WAIT.
SSM_LR_WAIT	The Ethernet IP link goes into SSM_LR_WAIT state if any of the following lock status signals goes low during SSM_LNK_RDY state: For 10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP core: `rx_data_ready` or `rx_is_lockedtodata` For Low Latency 40G Intel^® FPGA IP core: `rpcs_deskew_locked` or `rx_is_lockedtodata` For Intel^® Stratix^® 10 H-Tile Hard 50G and 100G IP cores: `o_rx_am_lock` or `rx_is_lockedtodata` For Low Latency 100G Intel^® FPGA IP core: `deskew_locked` or `rx_is_lockedtodata` For example, the local device wait for maximum of 1000 clock cycles to check if the lock conditions are met. If lock conditions are not met within 1000 clock cycles, the link goes back into SSM_ENABLE state. If the lock conditions are met any time before the 1000 clock cycles, the link goes back to SSM_LINK_RDY state.

⁴ SSM state for 10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP and Low Latency 40G Ethernet Intel^® FPGA IP cores.

⁵ SSM state for Intel^® Stratix^® 10 H-Tile Hard 50G and 100G IP cores and Low Latency 100G Intel^® FPGA IP core.

Link Analysis Tabs and Settings

The Link Analysis (LINK ANALYSIS) module of the Ethernet Link Inspector has five tabs:

Sequencer State Machine tab
Auto Neg tab
Link Training tab
Data Mode tab
Help tab

Sequencer State Machine Tab

The Sequencer State Machine (SSM) tab shows the flow of sequencer state machine states that the device goes through in the specific Signal Tap capture for the selected Ethernet IP core.

Figure 7. Example of Sequencer State Machine Tab GUI

Note: SSM State names in below image is for 10GBASE-KR PHY Intel^® Stratix^® 10 FPGA IP core. Based on the Ethernet IP, these state names may vary. Refer to Table 4 for details on state names specific to the IP.

Table 5. Sequencer State Machine Tab Parameters
Parameter	Description
Assumed Reference Timer Clock	Shows the assumed value of the clock frequency driving the reference timer. Ensure that the value of this clock is the same as the clock frequency configured in the Platform Designer window of the selected Ethernet IP core. Note: If the assumed value of the clock frequency does not match the clock frequency in Platform Designer window of the selected IP core, the timer values displayed in Link Analysis GUI will be incorrect. For example, the Timer values reported in Start, Stop and Delta columns in the Sequencer State machine tab would be incorrect.
States	Shows the flow of SSM states (from SEQ_Initialize to Data modes) that the device goes through in a specific capture. A successful state completion is highlighted in green whereas a state completion failure is highlighted in red.
Start	Timestamp for start time. Shows the reference timer value (in millisecond) corresponding to a specific state of SSM started.
Stop	Timestamp for stop time. Shows the reference timer value (in millisecond) corresponding to a specific state of SSM finished.
Delta	Timestamp for delta time. Shows the total time spent (in millisecond) on a specific state of SSM.

Auto Neg Tab

The Auto Neg tab may have one or more subtabs based on number of times the device goes into Auto Negotiation (AN) state during the Signal Tap capture in a finite amount of time. Each subtab displays the Ethernet IP link behavior during the occurrence of AN. Each AN occurrence is also prefixed with a number to distinguish between various AN occurrences.

Table 6. Local Device Status Signals
Name	Signal ⁶	Indication	Description
Auto Negotiation (AN) Enable	`an_enable`	LED	Green: Auto Negotiation is enabled. Red: Auto Negotiation is disabled.
Auto Negotiation (AN) Done	`an_done`	LED	Green: Auto Negotiation completed. This LED indication does not mean that the local device has finalized the common technology. Even in case of technology mismatch between the local and remote devices, `an_done` will be asserted. Red: Auto Negotiation is not completed.
Local Auto Negotiation (AN) Technology	[`lcl_tech`] or [`E25_TECH`]	Text	Displays the Auto Negotiation technology broadcasted by the local device.
Final Auto Negotiation (AN) Technology	[`hcd_40g`, `hcd_kr`, `hcd_xaui`, `hcd_gige`] or [`ieee_mode`] or [`e25_mode`]	Text	Displays the converged Auto Negotiation technology by the local device. Shows the corresponding timestamp of technology convergence.

Table 7. Remote Device Status Signals
Name	Signal	Indication	Description
Remote Device Auto Negotiation Technology	[`lp_tech`] or [`lp_e25_mode`]	Text	Displays the Auto Negotiation technology broadcasted by the remote device. Shows the timestamp when the local device receives this broadcasted technology.

AN Communication Packet

The AN Communication Packet section displays the exchange of AN packets between two devices. There are two parts to the AN Communication Packets section:

AN Packets Received—shows the sequence of AN packets (from left to right) received from a remote device.
AN Packets Sent—shows sequence of AN packets (from left to right) sent to a remote device.

Figure 8. AN Communication Packet GUI

Table 8. AN Communication Packet GUI Parameters
Parameter	Description
AN Packets (48 bits)	Shows the Auto Negotiation packets exchanged between local and remote devices in hexadecimal format.
Time (msec)	Shows the SSM state in which AN packets are sent/received along with the timestamp with respect to reference timer
Packet Details (hex)	Shows the breakout for various bits in an AN packet and displays whether an AN packet in base page or next page. Note: The assumption for BASE PAGE or NEXT PAGE only holds true when AN states are captured from the actual start point of Auto Negotiation (i.e., start point of SSM_RC_AN). If the AN states are captured partially in Signal Tap Logic Analyzer, this assumption becomes unreliable.

AN Arbiter State Machine

The AN Arbiter State Machine section displays the AN Arbiter State Machine in the form of time domain waveforms. The AN arbiter state machine represents the entire Ethernet IP link behavior in the AN mode of operation.

Each waveform window represents a timescale for one Sequencer State Machine (SSM) state (i.e., SSM_RC_AN, SSM_AN_ABL or SSM_AN_CHK). The time scale of waveform windows, such as START and STOP time, should match the timestamp of the corresponding SSM state. The waveform windows are also tagged with specific SSM states, as shown in the following figure:

Figure 9. Time Domain Waveforms of the Sequencer State Machine States

Each AN Arbiter SM state is represented as an individual waveform. A logic 1 value on a state waveform at a particular timestamp signifies the current state of the device at that timestamp. Device can possibly be in only one state at a given point of time. To change the magnification level of the waveforms, click the left mouse button and drag the mouse cursor to the bottom right of the waveform windows to zoom in and drag the mouse cursor the top right of the waveform windows to zoom out.

Note: While zooming in and out, the waveform windows may be offset in the vertical scale. This may cause several waveform windows in a row to be misaligned for logic 0 and 1. To remove any misalignments and scale the Y axis of all waveform window to a common scale, click on the Scale Waveforms (Y-axis) button.

Figure 10. Flowchart of AN Arbiter State MachineThis figure shows a flow chart of the AN Arbiter State Machine and the conditions that drives the next state, based on the current state.

Table 9. AN Arbiter State Machine State and Signal Descriptions
Name	Indication	Description
AN_ARB_ENABLE	Waveform	This is the initial state of the AN Arbiter State Machine. This should be enabled (logic 1 value) during SSM_RC_AN state. This state ends after the start of SSM_AN_ABL and the local device moves to the next state i.e., AN_ARB_TX_DIS.
AN_ARB_TX_DIS	Waveform	In this state, the TX output of the local device is disabled for a finite amount of time to allow the remote device to start Auto Negotiation. This causes to link to go down. The duration of this state can be 60 to 75 ms. Device should always complete this state irrespective if there is a remote device available or not.
AN_ARB_ABL_DET	Waveform	In this state, the local device send out the AN Base Page and waits for the AN base page from the remote device. The local device goes into this state at the end of SSM_AN_ABL. The local device waits in this state until the AN Base page is received and the corresponding Acknowledgement (ACK) is sent out to the remote device. The local device moves to next state after sending ACK to the remote device. If the ACK is not received from the remote device at this time, the local device moves to AN_ARB_ACK_DET where it waits for ACK from the remote signal. Else, the local device moves to AN_ARB_COMP_ACK, which indicates the completion of ACK exchange between the two devices.
AN_ARB_ACK_DET	Waveform	In this state, the local device is waiting for ACK from the remote device.
AN_ARB_COMP_ACK	Waveform	When an acknowledgement is sent to as well as received from the remote device, the local device moves to this state called the Ack Complete state.
AN_ARB_AN_GOOD	Waveform	This state indicates that AN has successfully completed on local device and is the final state of AN Arbiter State Machine.
AN_ARB_NXT_PAGE	Waveform	This state shows that the local device is sending NEXT page and waits for NEXT page from the remote device. This state remains until the local device send ACK to the remote device.

Table 10. AN Arbiter State Machine Signal Descriptions
Name	Indication	Description
`an_enable`	Waveform	Displays when AN is enable. This is waveform representation of the AN Enable signal described in Table 6.
`an_done`	Waveform	Displays when AN is completed successfully. This is waveform representation of the AN Done signal described in Table 6.

⁶ Actual signal names in the IP design file.

Link Training Tab

The Link Training Mode tab may have one or more subtabs based on number of times the device go into Link Training (LT) state during the Signal Tap capture in a finite amount of time. Each subtab displays the Ethernet link behavior during the occurrence of LT. Each LT occurrence is also prefixed with a number to distinguish between various LT occurrences.

Table 11. Local Device Status Signals
Name	Signal ⁷	Indication	Description
Link Training Enable	`lt_enable`	LED	Green: LT is enabled. Red: LT is disabled.
Frame Lock	`frame_lock`	LED	Green: Detected and locked from receiving LT packets. Also shows the timestamp of lock. Red: Not locked from receiving LT packets.
RX Trained	`rx_trained`	LED	Green: LT completed. Red: LT not completed.
Local RX Ready	`lcl_rx_ready`	LED	This signal is a delayed version of `rx_trained` signal. Green: LT completed. Red: LT not completed.
Link Training commands sent by Local Device	`rmt_coef_updl`, `rmt_coef_updh`	—	—
Init	—	Label	Indicates the total Initialize commands sent.
Preset	—	Label	Indicates the total Preset commands sent.
Main Incr	—	Label	Indicates the total main-tap increment commands sent.
Main Dec	—	Label	Indicates the total main-tap decrement commands sent.
Post-Tap Incr	—	Label	Indicates the total post-tap increment commands sent.
Post-Tap Dec	—	Label	Indicates the total post-tap decrement commands sent.
Pre-Tap Incr	—	Label	Indicates the total pre-tap increment commands sent.
Pre-Tap Dec	—	Label	Indicates the total pre-tap decrement commands sent.

Table 12. Remote Device Status Signals
Name	Signal ⁸	Indication	Description
Remote RX Ready	`rmt_rx_ready`	LED	Green: LT completed. Red: LT not completed.
Link Training commands sent by Remote Device	`lcl_coefh`, `lcl_coefl`	—	—
Init	—	Label	Indicates the total Initialize commands sent.
Preset	—	Label	Indicates the total Preset commands sent.
Main Incr	—	Label	Indicates the total main-tap increment commands sent.
Main Dec	—	Label	Indicates the total main-tap decrement commands sent.
Post-Tap Incr	—	Label	Indicates the total post-tap increment commands sent.
Post-Tap Dec	—	Label	Indicates the total post-tap increment commands sent.
Pre-Tap Incr	—	Label	Indicates the total pre-tap increment commands sent.
Pre-Tap Dec	—	Label	Indicates the total pre-tap decrement commands sent.

Table 13. Link Training Status Signals
Signal	Indication	Description
`frame_lock`	Waveform	Displays the behavior of `frame_lock` in a time domain. When asserted, it indicates that the local device locked to LT packets. This is a waveform representation of the Frame Lock signal in the Table 11.
`rx_trained`	Waveform	Displays the behavior of `rx_trained` in a time domain. When asserted, it indicates that the local device completed LT. This is a waveform representation of the RX Trained signal in the Table 11.
`lcl_rx_ready`	Waveform	Displays the behavior of `lcl_rx_ready` in a time domain. When asserted, it indicates that the local device completed LT. This is a waveform representation of the Local RX Ready signal in the Table 11.
`rmt_rx_ready`	Waveform	Displays the behavior of `rmt_rx_ready` in a time domain. When asserted, it indicates that the remote device completed LT. This is a waveform representation of the Remote RX Ready signal in the Table 12.

LT Communication Packets

The LT Communication Packets section displays the LT packets exchanged between two devices. The LT Communication packets option has to be enabled to start plotting LT packets. A timestamp header is stored with each packet with respect to the reference timer. The transaction of the LT packet plotting may take a few minutes based on the number of packets that are being exchanged. To determine whether the plotting is completed or still in progress, monitor the status bar.

Figure 11. LT Communication Packet Exchange between Local Device and Remote Device

If the LT Communication Packets option is checked, the following subsections will be displayed on the tab-window of the Link Training:

Commands sent by Remote Device (signals: lcl_coefh, lcl_coefl)
Status to Remote Device (signals: lcl_coef_sts)
Commands sent by Local Device (signals: rmt_coef_updl, rmt_coef_updh)
Status to Local Device (signals: rmt_coef_sts)

For every command sent by the local or remote device, there is an equivalent status being sent back by the receiver end. The status corresponding to every command can be mapped by monitoring their time stamps, as shown in the following figure:

Figure 12. LT Training SequenceThis figure shows the timestamps corresponding to Command1 (C1) -> Status1 (S1) and Command2 (C2) -> Status2 (S2) represents the time taken by taken by either device to respond to the LT commands.

Table 14. Link Training Command Definitions
Command	Description
Post-	Decreases post-tap by 2 and increases main-tap by 1.
Post+	Increases post-tap by 2 and decreases main-tap by 1.
Main-	Decreases main-tap by 1.
Main+	Increases main-tap by 1.
Pre-	Decreases pre-tap by 2 and increases main-tap by 1
Pre+	Increases pre-tap by 2 and decreases main-tap by 1
Hold	Do not change any tap values.
Preset	Sets pre-tap and post-tap to zero and main-tap to maximum, as defined in Clause 72 of the IEEE 802.3 2015 Standard.
Initialize	Sets the coefficients back to initial (start) values configured in the IP core.

The following figure shows the direction in which the digital values of main-tap, post-tap, and pre-tap move based on commands. For more details on these values, refer to the Intel^® Stratix^® 10 L- and H-Tile Transceiver PHY User Guide.

Figure 13. Direction of Main-Tap, Post-Tap, and Pre-Tap Based On Link Training Commands

Table 15. Status Definitions
Status	Description
no upd	No taps updated.
Post-upd	Post-tap updated. This status is valid for both increment and decrement command
Post-max	Post-tap incremented and is at maximum value
Post-min	Post-tap decremented and is at minimum value
Pre-upd	Pre-tap updated. This status is valid for both increment and decrement command
Pre-max	Pre-tap incremented and is at maximum value.
Pre-min	Pre-tap decremented and is at minimum value.
Main-upd	Main-tap updated. This status is valid for both increment and decrement command.
Main-max	Main-tap incremented and is at maximum value.
Main-min	Main-tap decremented and is at minimum value.

Note: If the command or status shows "----", this indicates that the values in the LT packet are invalid.

⁷ All the descriptions in Table 11 are with reference to local device.

⁸ All the descriptions in Table 12 are with reference to remote device.

Data Mode Tab

Data Mode tab may have one or more subtabs based on number of times the device go into Data Mode state during the Signal Tap capture in a finite amount of time. Each subtab displays the Ethernet IP link behavior during the occurrence of Data Mode. Each Data Mode occurrence is also prefixed with a number to distinguish between various Data Mode occurrences.

Table 16. Local Device Status Signals
Name	Signal	Indication	Description
For 10GBASE-KR Intel^® Stratix^® 10 FPGA IP:
RX Block Lock	`rx_block_lock`	LED	Green: Locked from receiving Ethernet packets. Also shows the timestamp of lock. Red: Not locked from receiving Ethernet packets.
RX Data Ready	`rx_data_ready`	LED	Green: Represents successful block lock assertion. Also shows the timestamp. `an_done` will be asserted. Red: Block lock not asserted.
FEC	`pcs_mode_rc`	LED	Green: Local device is using FEC. Red: Local device is not using FEC.
For Intel^® Stratix^® 10 Low Latency 40G Ethernet Intel^® FPGA IP:
PCS Align Lock	`rpcs_align_locked`	LED	Green: All 4 lanes are skew compensated and aligned. Also shows the timestamp of lock. Red: Lanes are not skew compensated and not aligned.
PCS Deskew Lock	`rpcs_deskew_locked`	LED	Green: All 4 lanes are locked for alignment marker. Also shows the timestamp of lock. Red: Lanes are not locked for alignment marker.
FEC	`pcs_mode_rc`	LED	Green: Local device is using FEC. Red: Local device is not using FEC.
PCS Word Lock	`rpcs_word_locked`	LED	This signal is available per channel basis. There are four signals for 40GBASE-KR. Green: Locked from receiving Ethernet packets. Red: Not locked from receiving Ethernet packets.
RX ENH Block Lock	`rx_enh_blk_lock`	LED	This signal is available per channel basis. There are four signals for 40GBASE-KR. Green: FEC is locked from receiving Ethernet packets. Red: FEC is not locked from receiving Ethernet packets.
For Intel^® Stratix^® 10 H-Tile Hard 50G and 100G IPs:
RX Alignment Market Lock	`o_rx_am_lock`	LED	Green: All 4 lanes locked to the alignment marker. Red: Lanes not locked to the alignment marker.
RX Block Lock	`o_rx_block_lock`	LED	Green: All 4 lanes locked to the incoming 64b/66b. Red: Lanes not locked to the incoming 64b/66b.
For Intel^® Stratix^® 10 Low Latency 100G Ethernet Intel^® FPGA IP:
PCS Align Lock	`align_locked`	LED	Green: All 4 lanes are skew compensated and aligned. Also shows the timestamp of lock. Red: Lanes are not skew compensated and not aligned.
PCS Deskew Lock	`deskew_locked`	LED	Green: All 4 lanes are locked for alignment marker. Also shows the timestamp of lock. Red: Lanes are not locked for alignment marker.
FEC	`pcs_mode_rc`	LED	Green: Local device is using FEC. Red: Local device is not using FEC.
PCS Word Lock	`word_locked`	LED	Green: Locked from receiving Ethernet packets. Red: Not locked from receiving Ethernet packets.

Table 17. Data Mode Status Signals
Signal	Indication	Description
For 10GBASE-KR Intel^® Stratix^® 10 FPGA IP:
`rx_block_lock`	Waveform	Displays the behavior of `rx_block_lock` in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the RX Block Lock signal in the Table 16.
`rx_data_ready`	Waveform	Displays the behavior of `rx_data_ready` in time domain. This represents a successful block lock assertion. This is a waveform representation of the RX Data Ready signal in the Table 16.
`rx_hi_ber`	Waveform	Displays if the device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.
For Intel^® Stratix^® 10 Low Latency 40G Ethernet Intel^® FPGA IP:
`rpcs_align_locked`	Waveform	Displays the behavior of `rpcs_align_locked` in time domain. When asserted, it indicates that all 4 lanes are skew compensated and aligned. This is a waveform representation of the PCS Align Lock signal in the Table 16.
`rpcs_deskew_locked`	Waveform	Displays the behavior of `rpcs_deskew_locked` in time domain. When asserted, it indicates that all 4 lanes are locked to alignment markers. This is a waveform representation of the PCS Deskew Lock signal in the Table 16.
`rx_hi_ber`	Waveform	Displays if device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.
`rpcs_word_locked`	Waveform	Displays the behavior of `rpcs_word_locked` in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the PCS Word Lock signal in the Table 16.
`rx_enh_blk_lock`	Waveform	Displays the behavior of `rx_enh_blk_lock` in time domain. When asserted, it indicates that FEC is locked from receiving Ethernet packets. This is a waveform representation of the RX ENH Block Lock signal in the Table 16.
For Intel^® Stratix^® 10 H-Tile Hard 50G and 100G IPs:
`o_rx_hi_ber`	Waveform	Displays if the local device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.
`o_rx_am_lock`	Waveform	Displays the behavior of `o_rx_am_lock` in time domain. When asserted, it indicates that the local device is locked to alignment markers. This is a waveform representation of the RX Alignment Marker Lock signal in the Table 16.
`o_rx_block_lock`	Waveform	Displays the behavior of `o_rx_block_lock` in time domain. When asserted, it indicates that the local device is locked to the 64b/66b blocks from receiving Ethernet packets. This is a waveform representation of the RX Block Lock signal in the Table 16.
For Intel^® Stratix^® 10 Low Latency 100G Ethernet Intel^® FPGA IP:
`align_locked`	Waveform	Displays the behavior of `align_locked` in time domain. When asserted, it indicates that all 4 lanes are skew compensated and aligned. This is a waveform representation of the PCS Align Lock signal in the Table 16.
`deskew_locked`	Waveform	Displays the behavior of `deskew_locked` in time domain. When asserted, it indicates that all 4 lanes are locked to alignment markers. This is a waveform representation of the PCS Deskew Lock signal in the Table 16.
`rx_hi_ber`	Waveform	Displays if device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.
`word_locked`	Waveform	Displays the behavior of `word_locked` in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the PCS Word Lock signal in the Table 16.

Table 18. Device Intrinsic Signals
Note: This table displays the device internal signals used mostly for debugging purpose. Contact Intel^® Premier Support for any questions related to these signals.
Signal	Indication	Description
`rx_is_lockedtodata`	Waveform	Shows if clock data recover (CDR) receiver of the Local Device is locked to the incoming data. This is different than `rx_is_lockedtodata` coming from CDR. This is asserted only when CDR is locked to data for 1 ms.
`rx_is_lockedtoref`	Waveform	Shows if CDR receiver of the Local Device is locked to a reference clock.

Help Tab

The Help tab provides basic guidelines on:

Capturing Ethernet link bring-up sequence.
General recommendations for Signal Tap Logic Analyzer configuration.

Ethernet Link Inspector User Guide Archives

Ethernet Link Inspector is a standalone tool used with the Intel^® Quartus^® Prime Design Suite software version up to v18.1.

From Intel^® Quartus^® Prime Design Suite software version 19.1 or later, the tool is integrated into the Intel^® Quartus^® Prime Design Suite software. ⁹

If an Intel^® Quartus^® Prime version is not listed, the user guide for the previous version applies.

Intel^® Quartus^® Prime Version	STP Package for Intel^® Quartus^® Prime	User Guide
19.1	Intel^® Stratix^® 10 Ethernet Link Inspector STP Package for Intel^® Quartus^® Prime ¹⁰	Ethernet Link Inspector User Guide for Intel^® Stratix^® 10 Devices

Intel^® Quartus^® Prime Version	Ethernet Link Inspector Version	User Guide
18.0	Ethernet Link Inspector Package v4.1	Ethernet Link Inspector User Guide v4.1 for Intel^® Stratix^® 10 Devices
17.1	Ethernet Link Inspector Package v1.1	Ethernet Link Inspector User Guide v1.1 for Intel^® Stratix^® 10 Devices

⁹ Ethernet Link Inspector - Link Monitor for Low Latency 100G Ethernet Intel^® Stratix^® 10 FPGA IP is supported in Intel^® Quartus^® Prime software version 18.1 or later.

¹⁰ Ethernet Link Inspector tool is integrated into the Intel^® Quartus^® Prime software version 19.1 or later.

Document Revision History for the Ethernet Link Inspector User Guide for Intel Stratix 10 Devices

Document Version	Intel^® Quartus^® Prime Version	Changes
2019.07.01	19.2	Updated the Availability of JTAG to Avalon^® Master Bridge in Intel^® Stratix^® 10 Ethernet IP Cores table. Removed the Example of Instance Name of JTAG to Avalon Master Path figure. Updated the Example JTAG Master Selection Panel figure. Updated the Example Help tab figure. Added the Ethernet Link Inspector User Guide Archives section.
2019.04.15	19.1	Updated the document title to Ethernet Link Inspector User Guide for Intel^® Stratix^® 10 Devices. Renamed the topic title Downloading and Running the Ethernet Link Inspector to Running the Ethernet Link Inspector. Added new Topic: Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File. Updated the following Tables: Merged content of Table: Ethernet Link Inspector Supported IP Cores for Intel^® Stratix^® 10 E-tile Devices to Table: Ethernet Link Inspector Supported IP Cores for Intel^® Stratix^® 10 L- and H-tile Devices. Renamed table title from Ethernet Link Inspector Supported IP Cores for Intel^® Stratix^® 10 L- and H-tile Devices to Ethernet Link Inspector Supported IP Cores for Intel^® Stratix^® 10 L-, H-, and E-tile Devices Updated the following topics: Overview of Ethernet Link Inspector for Intel^® Stratix^® 10 Devices System Requirements Enabling Your Design For the Link Monitor Running the Ethernet Link Inspector Running the Link Monitor Running the Link Analysis Link Monitor Tabs and Settings Data Mode Tab

Document Version	Ethernet Link Inspector Version	Changes
2018.12.21	4.1	Updated the document title to Ethernet Link Inspector User Guide v4.1 for Intel Stratix 10 Devices. Updated the following topics: Downloading and Running the Ethernet Link Inspector Running the Link Monitor Link Analysis Tabs and Settings Updated Table: Ethernet Link Inspector Supported IP Cores for Intel^® Stratix^® 10 E-Tile Devices.
2018.12.04	4.0.1	Updated the document title to Ethernet Link Inspector User Guide v4.0.1 for Intel Stratix 10 Devices. Updated the following topics: Overview of Ethernet Link Inspector for Intel Stratix 10 Devices Downloading and Running the Ethernet Link Inspector Running the Link Monitor Link Analysis Tabs and Settings
2018.10.19	4.0	Updated the document title to Ethernet Link Inspector User Guide v4.0 for Intel Stratix 10 Devices. Added support for the following Ethernet IP cores: 25G Ethernet Intel FPGA IP core for Intel Stratix 10 L-, H-, and E-Tile devices 50G H-Tile Hard IP for Ethernet Intel FPGA IP 50G E-Tile Hard IP for Ethernet Intel FPGA IP Updated the following topics: Supported IP Cores and Devices Renamed Table title Ethernet Link Inspector Supported IP Cores for Intel Stratix 10 Devices to Ethernet Link Inspector Supported IP Cores for Intel Stratix 10 L- and H-Tile Devices. Added a new Table: Ethernet Link Inspector Supported IP Cores for Intel Stratix 10 E-Tile Devices. Downloading and Running the Ethernet Link Inspector for Intel^® Stratix^® 10 Devices Updated Table: Command Parameters. Link Monitor Tabs and Settings Renamed Table title Ethernet Link Monitor Toolkit GUI Tabs to Link Monitor GUI Tabs and updated the table. Sequencer State Machine Updated Table: SSM State Descriptions. Link Analysis Tabs and Settings Link Training Tab Updated Table title Data Mode Status Signals to Link Training Status Signals. Data Mode Tab Updated Tables: Local Device Status Signals, Remote Device Status Signals, and Link Training Status Signals. Updated the following Figures: Removed Figures: Example MAC & PHY Tab, Statistics Counters Tab, and KR/KR4. Added new Figures: Example MAC & PCS Tab, Example Statistics Counters Tab, and Example KR4 Tab. Updated Figures: Flowchart of SSM States and Flowchart of AN Arbiter State Machine. Restructured the Running the Link Analysis and Running the Link Monitor content in the Downloading and Running the Ethernet Link Inspector section into individual topics. Made minor editorial updates to the document.
2018.08.10	3.0	Updated the document title to Ethernet Link Inspector User Guide v3.0 for Intel Stratix 10 Devices. Updated Table: Ethernet Link Inspector Supported IP Cores for Intel Stratix 10 Devices to add a new variant support for E-Tile Hard IP for Ethernet Intel FPGA IP for 100G PAM4. Updated topics: Downloading and Running the Ethernet Link Inspector for Intel^® Stratix^® 10 Devices Link Analysis Tabs and Settings Removed Table: Ethernet IP Core Support for Ethernet Link Monitor Toolkit GUI Tabs. Made minor editorial updates.
2018.07.06	2.0	Initial release.