Ethernet Link Inspector User Guide for Intel Stratix 10 Devices
Overview of Ethernet Link Inspector for Intel Stratix 10 Devices
The Ethernet Link Inspector is an inspection tool that can continuously monitor an Ethernet link that contains an Ethernet IP, which includes Ethernet lane alignment status, clock data recover (CDR) lock, media access controller (MAC) statistics, Forward Error Correction (FEC) statistics, and others. If needed, the Ethernet Link Inspector can capture an event with the help of Signal Tap Logic Analyzer to further examine the link behavior during Auto Negotiation (AN), Link Training (LT), or any other event during the link operation. The Ethernet Link Inspector also creates a graphical user interface (GUI) to represent the link behavior.
Features
- Link Monitor
- Link Analysis
The following sections describe in detail the features of each module.
Link Monitor
It continuously reads and displays all of the required status registers related to the Ethernet IP link. The Link Monitor helps to ensure that all of the Ethernet IP link status at various stages are valid. In case of any failure, it narrows down to the type of failure based on the various status bits, which are based in the register bank of an Ethernet IP core. For more information on the register map, refer to respective Ethernet IP user guide.
Examples of the Ethernet link status displayed on the Link Monitor user interface include:
- State of Ethernet IP link (Up or Down)
- State of AN and LT process (Active or Done)
- Number of correct frames received
- Number of frame errors
- Transmitted and recovered clock frequencies etc.
Because the Link Monitor gives out real time link status through Ethernet IP registers, it needs to have a connection with the device that is powered on and configured with the appropriate design file.
Link Analysis
The Link Analysis relies on Signal Tap Logic Analyzer to capture and store database (.csv) of all required signals. Once the Signal Tap Logic Analyzer creates a database, the Link Analysis performs an analysis on the database to extract all the required information and displays them in a user-friendly graphical user interface (GUI).
- Ability to capture and display events that occur during Ethernet IP link bring-up. For example, Auto Negotiation and Link Training.
- Ability to capture the link behavior at an intended trigger point and analyze link behavior around that time period.
Supported IP Cores and Devices
Device | IP Core | Data Rate (Gbps) | IP Type | Auto Negotiation and Link Training 1 | FEC 1 | Link Monitor | Link Analysis |
---|---|---|---|---|---|---|---|
Intel® Stratix® 10 L-tile | 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP | 10 | Soft | Yes | Fire code (2112,2080) |
Yes | Yes |
25G Ethernet Intel® FPGA IP | 25 | Soft | N/A | RS-FEC (528,514) |
Yes | N/A | |
Low Latency 40G Ethernet Intel® FPGA IP | 40 | Soft | Yes | Fire code (2112,2080) |
Yes | Yes | |
Low Latency 100G Ethernet Intel® FPGA IP | 100 | Soft | Yes | RS-FEC (528,514) |
Yes | Yes | |
Intel® Stratix® 10 H-tile | 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP | 10 | Soft | Yes | Fire code (2112,2080) |
Yes | Yes |
25G Ethernet Intel® FPGA IP | 25 | Soft | N/A | RS-FEC (528,514) |
Yes | N/A | |
Low Latency 40G Ethernet Intel® FPGA IP | 40 | Soft | Yes | Fire code (2112,2080) |
Yes | Yes | |
Low Latency 100G Ethernet Intel® FPGA IP | 100 | Soft | Yes | RS-FEC (528,514) |
Yes | Yes | |
H-tile Hard IP for Ethernet Intel® FPGA IP | 50 | Hard | Yes | N/A | Yes | Yes | |
100 | Hard | Yes | N/A | Yes | Yes | ||
Intel® Stratix® 10 E-tile | E-tile Hard IP for Ethernet Intel® FPGA IP | 10 | Hard | Yes | N/A | Yes | N/A |
25 | Hard | Yes | RS-FEC (528,514) |
Yes | N/A | ||
100 (25Gx4 - NRZ) |
Hard | Yes | RS-FEC (528,514) |
Yes | N/A | ||
100 (50Gx2 - PAM4) |
Hard | Yes | RS-FEC (544,514) |
Yes | N/A |
Setting Up the Ethernet Link Inspector
System Requirements and Prerequisites
System Requirements
- Windows PC or Linux workstation.
- Intel® Quartus® Prime Pro Edition software version 19.1 and later.
For earlier versions of the Intel® Quartus® Prime Pro Edition software, refer to the relevant user guide listed in the Ethernet Link Inspector User Guide Archives chapter.
Enabling Your Design For the Link Monitor
To enable the use of Link Monitor, your design must instantiate JTAG to Avalon® Master Bridge. The availability of the JTAG to Avalon® Master bridge in the Intel® Stratix® 10 Ethernet IP cores is shown in the following table.
Device | IP Core | Data Rate (Gbps) | IP Type | Design Example 2 | Standalone IP 3 |
---|---|---|---|---|---|
Intel® Stratix® 10 L-Tile | 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP | 10 | Soft | Yes | Yes |
25G Ethernet Intel® FPGA IP | 25 | Soft | Yes | N/A | |
Low Latency 40G Ethernet Intel® FPGA IP | 40 | Soft | Yes | Yes | |
Low Latency 100G Ethernet Intel® FPGA IP | 100 | Soft | Yes | Yes | |
Intel® Stratix® 10 H-Tile | 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP | 10 | Soft | Yes | Yes |
25G Ethernet Intel® FPGA IP | 25 | Soft | Yes | N/A | |
Low Latency 40G Ethernet Intel® FPGA IP | 40 | Soft | Yes | Yes | |
Low Latency 100G Ethernet Intel® FPGA IP | 100 | Soft | Yes | Yes | |
H-Tile Hard IP for Ethernet Intel® FPGA IP | 50 | Hard | Yes | Yes | |
100 | Hard | Yes | Yes | ||
Intel® Stratix® 10 E-Tile | E-Tile Hard IP for Ethernet Intel® FPGA IP | 10 | Hard | Yes | Yes |
25 | Hard | Yes | Yes | ||
100 (25Gx4-NRZ) |
Hard | Yes | Yes | ||
100 (50Gx2-PAM4) |
Hard | Yes | Yes |
Running the Ethernet Link Inspector
You can run the Ethernet Link Inspector using System Console in the Intel® Quartus® Prime Pro Edition software. There are two separate Launch buttons to open Link Analysis and Link Monitor of the Ethernet Link Inspector as shown in the following figure.

Running the Link Monitor

- In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
-
In the system console, click the Launch button under the Ethernet Link Inspector - Link Monitor section to run the Link Monitor module. The Ethernet Link Inspector - Link Monitor tab appears.
Note: You can open multiple instances of the Link Monitor module simultaneously for different IPs.
-
In the Ethernet Link Inspector - Link Monitor tab, follow these steps to set the correct JTAG to
Avalon®
Master path:
- Load the Programming File (*.sof) in System Console by clicking File > Load Design for the detailed JTAG to Avalon® Master path.
- Select List JTAG Masters to see all available JTAG to Avalon® Master paths.
- Select a JTAG to
Avalon®
Master path
number from the drop-down box and click Set JTAG
Master. Note: The instance name of the JTAG to Avalon® Master path is displayed along with the text FULL_HPATH (marked by the blue box in the figure below). Select the JTAG to Avalon® Master path number that has the instance name of the JTAG to Avalon® Master path connected to the Ethernet IP.Figure 1. Example JTAG Master Selection Panel
- From the Select IP Variant drop-down list, select an IP Variant and click Launch to populate the user interface of the Link Monitor.
Running the Link Analysis

- In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
-
In the system console, click the Launch button under the Ethernet Link Inspector - Link Analysis section to run the Link Analysis module. The Ethernet Link Inspector - Link Analysis tab appears.
Note: You can open multiple instances of the Link Analysis module simultaneously for different IPs.
- In the Ethernet Link Inspector - Link Analysis tab, select the target IP core from the drop-down box.
- Click the Select .csv file button to import the Signal Tap database (.csv) file. Refer to the Creating and Capturing Signal Tap Database and Exporting as CSV File section in this user guide to create the .csv file. In the Status Bar, make sure the directory to the imported database is correct.
-
Click the Start Analysis button.
Note: If you want the summary of the Ethernet link capture without using the Link Analysis, enter a report name and click Generate Report button to create a report (.csv) file. This feature is supported only for 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP and Intel® Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP.
Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File
Creating a Signal Tap (.stp) File
- To create .stp file with the list of expected signals for a specific Ethernet IP core, refer to the document Link_Analysis_STP_RequiredSignals.xlsx provided in the Ethernet_Link_Inspector_Package.zip file.
- For design examples, use the Signal Tap files provided in the Ethernet_Link_Inspector_Package.zip file to capture a Signal Tap file.
Capturing a Signal Tap (.stp) File
- Program the .sof file using the Intel® Quartus® Prime Pro Edition software.
- Double click on the created .stp file associated with the .sof file to open the Signal Tap Logic Analyzer.
- Clear the .stp file so that it does not contain any previous captured data by holding the IP into reset and clicking Run Analysis, followed by Stop Analysis on the Signal Tap Logic Analyzer toolbar.The IP can be reset by using either of the following two methods:
- Using the Link Monitor, click once on Assert Full System Reset in the Resets panel under the MAC & PCS tab.
- Direct access to reset ports or registers.
- Using the Link Monitor, maintain the IP reset by clicking once on Assert Full System Reset in the Reset panel under the MAC & PCS tab.
- To start the Signal Tap data capture, click Run Analysis in the Signal Tap Logic Analyzer.
- Using the Link Monitor, release the IP reset by clicking once on Deassert Full System Reset in the Reset panel under the MAC & PCS tab.Note: The Signal Tap Logic Analyzer may not stop automatically after releasing reset if the captured data is not enough to completely fill the memory. If the Signal Tap capture does not stop on its own, follow the steps below:
- Wait 2 to 5 seconds.
- Click Stop Analysis on the Signal Tap Logic Analyzer toolbar.
Exporting a Signal Tap Database as Comma Separated Value (.csv) File
The Signal Tap Logic Analyzer can save Signal Tap database in a .csv format. After the Signal Tap capture is completed, export the database. Once the database is saved, import the database through Link Analysis for further processing.
- In the Signal Tap Logic Analyzer, select Files > Export to export the captured data.
- Specify the File Name, Directory, and Export Format (in .csv file format).
- Click OK to generate the .csv database of the captured data.
The Link Analysis reads all the data that are being captured and stored by Signal Tap Logic Analyzer. To prevent processing error, it is important that you export and store the Signal Tap waveform database in .csv format, which contains a list of signals that the Link Analysis expects to receive.
Functional Description
This section describes the various parts of the Ethernet Link Inspector user interface and how each part represents the device behavior. The Ethernet Link Inspector consists of two inspection modules: Link Monitor and Link Analysis.
Link Monitor Module
Link Monitor Tabs and Settings
The Link Monitor module of the Ethernet Link Inspector has three tabs. Each tab implements various Control and Status Registers (CSR) of the selected Ethernet IP core. There is also a Continuous Read All Registers option, which continuously polls the status of all the tabs.
Tab | Description |
---|---|
MAC & PCS |
Resets the IP core, reads the MAC configuration and checks the high level PCS status.
|
Statistics |
|
PMA |
|
Help | Displays link bring up guidelines |
The following figures show the Link Monitor GUI tabs and are related to the 25G E-tile Hard IP for Ethernet Intel® FPGA IP. The availability of each tab depends on IP selection and its features.




Link Analysis Module
When an Ethernet IP core is configured in a KR/CR configuration (which includes Auto Negotiation and Link Training), the local device can be in either one of the following four operational modes starting from power-up to the device operation of the IP core:
- Sequencer Initialize mode (SEQ_Initialize)
- Auto Negotiation mode (Auto_Neg)
- Link Training mode (Link_Training)
- Data mode (Data)
The local device implements various internal states as part of the Sequencer State Machine to represent the four modes above. The local device may use one or more of the internal states to represent any one of the above mode. Refer to Sequencer State Machine for more details.
Sequencer State Machine
The Ethernet IP cores for Intel® Stratix® 10 devices implement an internal state machine called Sequencer State Machine (SSM) that represents the Ethernet IP link bring-up. At any point of time, the device should be in one of SSM states.
SSM State | Description |
---|---|
SSM_ENABLE |
The first state used for Sequencer State Machine (SSM) initialization. This should be the first state of device after a power cycle or a reset. If Auto Negotiation (AN) and Link Training (LT) are enabled, the local device moves to the SSM_RC_AN state after this state is completes. |
SSM_RC_AN | Indicates the reconfiguration of PHY for Auto Negotiation operation. |
SSM_AN_ABL | After the completion of SSM_RC_AN state, the local device goes into the SSM_AN_ABL state. In this state, the transmitter of the local device is disabled (i.e., no transitions) so that the Ethernet IP link goes down and the Ethernet IP link partner also goes back to Auto Negotiation. Even without any Ethernet IP link partners connected, the local device should complete this state and move to the next state i.e., SSM_AN_CHK. The local device spends an approximate time of 60 to 75 milliseconds (ms) in this state. At the end of this state, the local device starts sending AN Base Page to the remote device. |
SSM_AN_CHK |
Once the local device starts sending AN base page, it moves to the state SSM_AN_CHK. The rest of the AN happens in this state. The following are major AN events that happen in this state:
Various events during AN are further categorized into a separate state machine called AN Arbiter State Machine. Refer to Auto Neg Tab for more details. |
SSM_RC_LT | Indicates the reconfiguration of PHY for LT operation. |
SSM_LT_CHK |
After completion of SSM_RC_LT, device goes into SSM_LT_CHK state. This state includes the LT packet communication between the two devices, local and remote. At the end of this state, both devices should have completed LT and acknowledge each other upon completion. |
SSM_RC_10G
4
SSM_RC_DAT 5 |
Indicates that the reconfiguration of PHY for:
|
SSM_10G_CHK 4
SSM_LNK_CHK 5 |
After the completion of the SSM_RC_10G/SSM_RC_DAT state, the local device goes into the SSM_10G_CHK/SSM_LNK_CHK state. In this state, the local device tries to achieve lock on the received Ethernet packets. The following status signals shows the lock status:
The local device will move to the next state called SSM_LNK_RDY when the lock conditions are met. The local device can only remain in this state if the total time, starting from SSM_RC_LT, does not exceed 500 ms. If the total time exceeds 500 ms and the lock conditions are still not met, the local device goes back to SSM_ENABLE state and redo the AN and LT. |
SSM_LNK_RDY | Indicates that the local device has successfully locked on to the received Ethernet packets and processed them accordingly. The local device is expected to be in this state during the entire exchange of Ethernet packets unless it losses lock (rx_data_ready or rx_is_lockedtodata). If the local device losses lock, it goes to the next SSM state called SSM_LR_WAIT. |
SSM_LR_WAIT |
The Ethernet IP link goes into SSM_LR_WAIT state if any of the following lock status signals goes low during SSM_LNK_RDY state:
For example, the local device wait for maximum of 1000 clock cycles to check if the lock conditions are met. If lock conditions are not met within 1000 clock cycles, the link goes back into SSM_ENABLE state. If the lock conditions are met any time before the 1000 clock cycles, the link goes back to SSM_LINK_RDY state. |
Link Analysis Tabs and Settings
- Sequencer State Machine tab
- Auto Neg tab
- Link Training tab
- Data Mode tab
- Help tab
Sequencer State Machine Tab

Parameter | Description |
---|---|
Assumed Reference Timer Clock | Shows the assumed value of the clock frequency driving the reference
timer. Ensure that the value of this clock is the same as the clock
frequency configured in the Platform Designer window of the selected Ethernet IP core. Note: If the assumed value of the clock frequency
does not match the clock frequency in Platform Designer window of the
selected IP core, the timer values displayed in Link
Analysis GUI will be incorrect. For example, the Timer
values reported in Start, Stop and Delta columns in the
Sequencer State machine tab would be incorrect.
|
States | Shows the flow of SSM states (from SEQ_Initialize to Data modes) that the device goes through in a specific capture. A successful state completion is highlighted in green whereas a state completion failure is highlighted in red. |
Start | Timestamp for start time. Shows the reference timer value (in millisecond) corresponding to a specific state of SSM started. |
Stop | Timestamp for stop time. Shows the reference timer value (in millisecond) corresponding to a specific state of SSM finished. |
Delta | Timestamp for delta time. Shows the total time spent (in millisecond) on a specific state of SSM. |
Auto Neg Tab
The Auto Neg tab may have one or more subtabs based on number of times the device goes into Auto Negotiation (AN) state during the Signal Tap capture in a finite amount of time. Each subtab displays the Ethernet IP link behavior during the occurrence of AN. Each AN occurrence is also prefixed with a number to distinguish between various AN occurrences.
Name | Signal 6 | Indication | Description |
---|---|---|---|
Auto Negotiation (AN) Enable | an_enable | LED |
|
Auto Negotiation (AN) Done | an_done | LED |
|
Local Auto Negotiation (AN) Technology | [lcl_tech] or [E25_TECH] | Text | Displays the Auto Negotiation technology broadcasted by the local device. |
Final Auto Negotiation (AN) Technology | [hcd_40g, hcd_kr, hcd_xaui, hcd_gige] or [ieee_mode] or [e25_mode] | Text |
|
Name | Signal | Indication | Description |
---|---|---|---|
Remote Device Auto Negotiation Technology | [lp_tech] or [lp_e25_mode] | Text |
|
AN Communication Packet
- AN Packets Received—shows the sequence of AN packets (from left to right) received from a remote device.
- AN Packets Sent—shows sequence of AN packets (from left to right) sent to a remote device.

Parameter | Description |
---|---|
AN Packets (48 bits) | Shows the Auto Negotiation packets exchanged between local and remote devices in hexadecimal format. |
Time (msec) | Shows the SSM state in which AN packets are sent/received along with the timestamp with respect to reference timer |
Packet Details (hex) | Shows the breakout for various bits in an AN
packet and displays whether an AN packet in base page or next
page. Note: The assumption for BASE PAGE or NEXT
PAGE only holds true when AN states are captured from the actual
start point of Auto Negotiation (i.e., start point of
SSM_RC_AN). If the AN states are captured partially in Signal Tap Logic Analyzer, this
assumption becomes unreliable.
|
AN Arbiter State Machine
The AN Arbiter State Machine section displays the AN Arbiter State Machine in the form of time domain waveforms. The AN arbiter state machine represents the entire Ethernet IP link behavior in the AN mode of operation.

Each AN Arbiter SM state is represented as an individual waveform. A logic 1 value on a state waveform at a particular timestamp signifies the current state of the device at that timestamp. Device can possibly be in only one state at a given point of time. To change the magnification level of the waveforms, click the left mouse button and drag the mouse cursor to the bottom right of the waveform windows to zoom in and drag the mouse cursor the top right of the waveform windows to zoom out.
Name | Indication | Description |
---|---|---|
AN_ARB_ENABLE | Waveform | This is the initial state of the AN Arbiter State Machine. This should be enabled (logic 1 value) during SSM_RC_AN state. This state ends after the start of SSM_AN_ABL and the local device moves to the next state i.e., AN_ARB_TX_DIS. |
AN_ARB_TX_DIS | Waveform | In this state, the TX output of the local device is disabled for a finite amount of time to allow the remote device to start Auto Negotiation. This causes to link to go down. The duration of this state can be 60 to 75 ms. Device should always complete this state irrespective if there is a remote device available or not. |
AN_ARB_ABL_DET | Waveform |
In this state, the local device send out the AN Base Page and waits for the AN base page from the remote device. The local device goes into this state at the end of SSM_AN_ABL. The local device waits in this state until the AN Base page is received and the corresponding Acknowledgement (ACK) is sent out to the remote device. The local device moves to next state after sending ACK to the remote device. If the ACK is not received from the remote device at this time, the local device moves to AN_ARB_ACK_DET where it waits for ACK from the remote signal. Else, the local device moves to AN_ARB_COMP_ACK, which indicates the completion of ACK exchange between the two devices. |
AN_ARB_ACK_DET | Waveform | In this state, the local device is waiting for ACK from the remote device. |
AN_ARB_COMP_ACK | Waveform | When an acknowledgement is sent to as well as received from the remote device, the local device moves to this state called the Ack Complete state. |
AN_ARB_AN_GOOD | Waveform | This state indicates that AN has successfully completed on local device and is the final state of AN Arbiter State Machine. |
AN_ARB_NXT_PAGE | Waveform | This state shows that the local device is sending NEXT page and waits for NEXT page from the remote device. This state remains until the local device send ACK to the remote device. |
Name | Indication | Description |
---|---|---|
an_enable | Waveform | Displays when AN is enable. This is waveform representation of the AN Enable signal described in Table 6. |
an_done | Waveform | Displays when AN is completed successfully. This is waveform representation of the AN Done signal described in Table 6. |
Link Training Tab
The Link Training Mode tab may have one or more subtabs based on number of times the device go into Link Training (LT) state during the Signal Tap capture in a finite amount of time. Each subtab displays the Ethernet link behavior during the occurrence of LT. Each LT occurrence is also prefixed with a number to distinguish between various LT occurrences.
Name | Signal 7 | Indication | Description |
---|---|---|---|
Link Training Enable | lt_enable | LED |
|
Frame Lock | frame_lock | LED |
|
RX Trained | rx_trained | LED |
|
Local RX Ready | lcl_rx_ready | LED | This signal is a delayed version of rx_trained signal.
|
Link Training commands sent by Local Device | rmt_coef_updl, rmt_coef_updh | — | — |
Init | — | Label | Indicates the total Initialize commands sent. |
Preset | — | Label | Indicates the total Preset commands sent. |
Main Incr | — | Label | Indicates the total main-tap increment commands sent. |
Main Dec | — | Label | Indicates the total main-tap decrement commands sent. |
Post-Tap Incr | — | Label | Indicates the total post-tap increment commands sent. |
Post-Tap Dec | — | Label | Indicates the total post-tap decrement commands sent. |
Pre-Tap Incr | — | Label | Indicates the total pre-tap increment commands sent. |
Pre-Tap Dec | — | Label | Indicates the total pre-tap decrement commands sent. |
Name | Signal 8 | Indication | Description |
---|---|---|---|
Remote RX Ready | rmt_rx_ready | LED |
|
Link Training commands sent by Remote Device | lcl_coefh, lcl_coefl | — | — |
Init | — | Label | Indicates the total Initialize commands sent. |
Preset | — | Label | Indicates the total Preset commands sent. |
Main Incr | — | Label | Indicates the total main-tap increment commands sent. |
Main Dec | — | Label | Indicates the total main-tap decrement commands sent. |
Post-Tap Incr | — | Label | Indicates the total post-tap increment commands sent. |
Post-Tap Dec | — | Label | Indicates the total post-tap increment commands sent. |
Pre-Tap Incr | — | Label | Indicates the total pre-tap increment commands sent. |
Pre-Tap Dec | — | Label | Indicates the total pre-tap decrement commands sent. |
Signal | Indication | Description |
---|---|---|
frame_lock | Waveform | Displays the behavior of frame_lock in a time domain. When asserted, it indicates that the local device locked to LT packets. This is a waveform representation of the Frame Lock signal in the Table 11. |
rx_trained | Waveform | Displays the behavior of rx_trained in a time domain. When asserted, it indicates that the local device completed LT. This is a waveform representation of the RX Trained signal in the Table 11. |
lcl_rx_ready | Waveform | Displays the behavior of lcl_rx_ready in a time domain. When asserted, it indicates that the local device completed LT. This is a waveform representation of the Local RX Ready signal in the Table 11. |
rmt_rx_ready | Waveform | Displays the behavior of rmt_rx_ready in a time domain. When asserted, it indicates that the remote device completed LT. This is a waveform representation of the Remote RX Ready signal in the Table 12. |
LT Communication Packets
The LT Communication Packets section displays the LT packets exchanged between two devices. The LT Communication packets option has to be enabled to start plotting LT packets. A timestamp header is stored with each packet with respect to the reference timer. The transaction of the LT packet plotting may take a few minutes based on the number of packets that are being exchanged. To determine whether the plotting is completed or still in progress, monitor the status bar.
- Commands sent by Remote Device (signals: lcl_coefh, lcl_coefl)
- Status to Remote Device (signals: lcl_coef_sts)
- Commands sent by Local Device (signals: rmt_coef_updl, rmt_coef_updh)
- Status to Local Device (signals: rmt_coef_sts)
For every command sent by the local or remote device, there is an equivalent status being sent back by the receiver end. The status corresponding to every command can be mapped by monitoring their time stamps, as shown in the following figure:

Command | Description |
---|---|
Post- | Decreases post-tap by 2 and increases main-tap by 1. |
Post+ | Increases post-tap by 2 and decreases main-tap by 1. |
Main- | Decreases main-tap by 1. |
Main+ | Increases main-tap by 1. |
Pre- | Decreases pre-tap by 2 and increases main-tap by 1 |
Pre+ | Increases pre-tap by 2 and decreases main-tap by 1 |
Hold | Do not change any tap values. |
Preset | Sets pre-tap and post-tap to zero and main-tap to maximum, as defined in Clause 72 of the IEEE 802.3 2015 Standard. |
Initialize | Sets the coefficients back to initial (start) values configured in the IP core. |
The following figure shows the direction in which the digital values of main-tap, post-tap, and pre-tap move based on commands. For more details on these values, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.
Status | Description |
---|---|
no upd | No taps updated. |
Post-upd | Post-tap updated. This status is valid for both increment and decrement command |
Post-max | Post-tap incremented and is at maximum value |
Post-min | Post-tap decremented and is at minimum value |
Pre-upd | Pre-tap updated. This status is valid for both increment and decrement command |
Pre-max | Pre-tap incremented and is at maximum value. |
Pre-min | Pre-tap decremented and is at minimum value. |
Main-upd | Main-tap updated. This status is valid for both increment and decrement command. |
Main-max | Main-tap incremented and is at maximum value. |
Main-min | Main-tap decremented and is at minimum value. |
Data Mode Tab
Data Mode tab may have one or more subtabs based on number of times the device go into Data Mode state during the Signal Tap capture in a finite amount of time. Each subtab displays the Ethernet IP link behavior during the occurrence of Data Mode. Each Data Mode occurrence is also prefixed with a number to distinguish between various Data Mode occurrences.
Name | Signal | Indication | Description |
---|---|---|---|
For 10GBASE-KR Intel® Stratix® 10 FPGA IP: | |||
RX Block Lock | rx_block_lock | LED |
|
RX Data Ready | rx_data_ready | LED |
|
FEC | pcs_mode_rc | LED |
|
For Intel® Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP: | |||
PCS Align Lock | rpcs_align_locked | LED |
|
PCS Deskew Lock | rpcs_deskew_locked | LED |
|
FEC | pcs_mode_rc | LED |
|
PCS Word Lock | rpcs_word_locked | LED | This signal is available per channel basis.
There are four signals for 40GBASE-KR.
|
RX ENH Block Lock | rx_enh_blk_lock | LED | This signal is available per channel basis.
There are four signals for 40GBASE-KR.
|
For Intel® Stratix® 10 H-Tile Hard 50G and 100G IPs: | |||
RX Alignment Market Lock | o_rx_am_lock | LED |
|
RX Block Lock | o_rx_block_lock | LED |
|
For Intel® Stratix® 10 Low Latency 100G Ethernet Intel® FPGA IP: | |||
PCS Align Lock | align_locked | LED |
|
PCS Deskew Lock | deskew_locked | LED |
|
FEC | pcs_mode_rc | LED |
|
PCS Word Lock | word_locked | LED |
|
Signal | Indication | Description |
---|---|---|
For 10GBASE-KR Intel® Stratix® 10 FPGA IP: | ||
rx_block_lock | Waveform | Displays the behavior of rx_block_lock in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the RX Block Lock signal in the Table 16. |
rx_data_ready | Waveform | Displays the behavior of rx_data_ready in time domain. This represents a successful block lock assertion. This is a waveform representation of the RX Data Ready signal in the Table 16. |
rx_hi_ber | Waveform |
Displays if the device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard. |
For Intel® Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP: | ||
rpcs_align_locked | Waveform | Displays the behavior of rpcs_align_locked in time domain. When asserted, it indicates that all 4 lanes are skew compensated and aligned. This is a waveform representation of the PCS Align Lock signal in the Table 16. |
rpcs_deskew_locked | Waveform | Displays the behavior of rpcs_deskew_locked in time domain. When asserted, it indicates that all 4 lanes are locked to alignment markers. This is a waveform representation of the PCS Deskew Lock signal in the Table 16. |
rx_hi_ber | Waveform |
Displays if device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard. |
rpcs_word_locked | Waveform | Displays the behavior of rpcs_word_locked in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the PCS Word Lock signal in the Table 16. |
rx_enh_blk_lock | Waveform | Displays the behavior of rx_enh_blk_lock in time domain. When asserted, it indicates that FEC is locked from receiving Ethernet packets. This is a waveform representation of the RX ENH Block Lock signal in the Table 16. |
For Intel® Stratix® 10 H-Tile Hard 50G and 100G IPs: | ||
o_rx_hi_ber | Waveform | Displays if the local device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard. |
o_rx_am_lock | Waveform | Displays the behavior of o_rx_am_lock in time domain. When asserted, it indicates that the local device is locked to alignment markers. This is a waveform representation of the RX Alignment Marker Lock signal in the Table 16. |
o_rx_block_lock | Waveform | Displays the behavior of o_rx_block_lock in time domain. When asserted, it indicates that the local device is locked to the 64b/66b blocks from receiving Ethernet packets. This is a waveform representation of the RX Block Lock signal in the Table 16. |
For Intel® Stratix® 10 Low Latency 100G Ethernet Intel® FPGA IP: | ||
align_locked | Waveform |
Displays the behavior of align_locked in time domain. When asserted, it indicates that all 4 lanes are skew compensated and aligned. This is a waveform representation of the PCS Align Lock signal in the Table 16. |
deskew_locked | Waveform | Displays the behavior of deskew_locked in time domain. When asserted, it indicates that all 4 lanes are locked to alignment markers. This is a waveform representation of the PCS Deskew Lock signal in the Table 16. |
rx_hi_ber | Waveform | Displays if device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard. |
word_locked | Waveform | Displays the behavior of word_locked in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the PCS Word Lock signal in the Table 16. |
Signal | Indication | Description |
---|---|---|
rx_is_lockedtodata | Waveform | Shows if clock data recover (CDR) receiver of the Local Device is locked to the incoming data. This is different than rx_is_lockedtodata coming from CDR. This is asserted only when CDR is locked to data for 1 ms. |
rx_is_lockedtoref | Waveform | Shows if CDR receiver of the Local Device is locked to a reference clock. |
Help Tab
- Capturing Ethernet link bring-up sequence.
- General recommendations for Signal Tap Logic Analyzer configuration.
Ethernet Link Inspector User Guide Archives
From Intel® Quartus® Prime Design Suite software version 19.1 or later, the tool is integrated into the Intel® Quartus® Prime Design Suite software. 9
Intel® Quartus® Prime Version | STP Package for Intel® Quartus® Prime | User Guide |
---|---|---|
19.1 | Intel® Stratix® 10 Ethernet Link Inspector STP Package for Intel® Quartus® Prime 10 | Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices |
Intel® Quartus® Prime Version | Ethernet Link Inspector Version | User Guide |
---|---|---|
18.0 | Ethernet Link Inspector Package v4.1 | Ethernet Link Inspector User Guide v4.1 for Intel® Stratix® 10 Devices |
17.1 | Ethernet Link Inspector Package v1.1 | Ethernet Link Inspector User Guide v1.1 for Intel® Stratix® 10 Devices |
Document Revision History for the Ethernet Link Inspector User Guide for Intel Stratix 10 Devices
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.07.01 | 19.2 |
|
2019.04.15 | 19.1 |
|
Document Version | Ethernet Link Inspector Version | Changes |
---|---|---|
2018.12.21 | 4.1 |
|
2018.12.04 | 4.0.1 |
|
2018.10.19 | 4.0 |
|
2018.08.10 | 3.0 |
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2018.07.06 | 2.0 | Initial release. |