1. JESD204C Intel FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Stratix 10 E-tile Devices
Intel® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP).
Intel® FPGA IP has been hardware-tested with a number
of selected JESD204C compliant analog-to-digital converter (ADC) devices.
This report highlights the interoperability of the JESD204C
Intel® FPGA IP with the AD9081 ADC converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results of the ADC to FPGA JESD204C RX IP. The FPGA JESD204C TX IP data path to AD9081 DAC is not checked out.
Stratix® 10 TX SI Development Kit (Production
Rev B Edition) is used with the ADI AD9081 daughter card module installed to the FMC+
connector of the development board.
The AD9081 EVM derives power from the S10 board through the FMC+ connector.
The E-tile transceiver reference clock of the FPGA is also supplied by the Silicon Labs Si5341 programmable clock generator present in the
Stratix® 10 development kit.
The Si5341 programmable clock generator provides a reference clock to the HMC7044
programmable clock generator present in the AD9081 EVM through FPGA (to convert differential
clock from Si5431 to single ended clock for HMC7044) and SMA to SMP cable.
The HMC7044 programmable clock generator provides the AD9081 device reference clock. The phase-locked loop (PLL) present in the AD9081 device generates the desired ADC sampling clock from the device reference clock.
The PLL reference clock of the JESD204C
Intel® FPGA IP is supplied by the HMC7044 programmable clock generator through the FMC+ connector.
For Subclass 1, the HMC7044 clock generator generates the SYSREF signal for the AD9081 device and for the JESD204C
Intel® FPGA IP through the FMC+ connector.
The rx_dl_signal signal is connected in between the output of the FPGA and the ADC 0 input of AD9081 through a voltage divider circuit with the SMA to SMA cables to measure the deterministic latency.
Intel® recommends the SYSREF to be provided by the clock generator that
sources the JESD204C
Intel® FPGA IP device clock and sampling
clock to ADC.
Figure 1. Hardware Setup
The following system-level diagram shows how the different modules are connected in this design.
Figure 2. System Diagram
In this setup, where LMF = 841, the data rate of transceiver lanes is 24.75 Gbps. The SYSREF and clocking scheme for FPGA and ADC is explained below and illustrated in Figure 2.
The Si5341 out8 generates 375 MHz clock to E-Tile transceiver reference clock. The 122.88 MHz differential output clock generated by the Si5341 out2 is fed to FPGA and taken out of FPGA as a single ended clock connected to CLK OUT SMA port J33 in the development kit for the HMC7044 EXT_HMCREF SMP port in AD9081 EVM through a cable. The HMC7044 takes the 122.88 MHz reference clock and generates 375 MHz for the device clock CLKIN of AD9081 and a periodic SYSREF signal of 11.71875 MHz for the SYSREF input of AD9081. The HMC7044 also generates 375 MHz for the FPGA core PLL reference clock and a periodic SYSREF signal of 11.71875 MHz for JESD204C
Intel® FPGA IP through the FMC+ connector.
Intel® FPGA IP is instantiated in duplex mode but only the receiver path is used. For FCLK_MULP = 2, WIDTH_MULP = 8, S = 1 the core PLL generates 187.5 MHz link clock and 375 MHz frame clock.
The rx_dl_signal signal from CLK OUT SMA port J31 to ADC0/None SMA port is for the deterministic latency measurement.
1.3. Hardware Checkout Methodology
The following section describes the test objectives, procedure, and the
passing criteria. The test covers the following areas:
Receiver data link layer
Receiver transport layer
Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer
This test area covers the test cases for sync header alignment (SHA)
and extended multiblock alignment (EMBA).
On link start up, after the receiver reset, the JESD204C
Intel® FPGA IP starts looking for the sync header stream that
is transmitted by the device. The Signal Tap logic
analyzer tool monitors the receiver data link layer operation.
22.214.171.124. Sync Header Alignment (SHA)
Table 1. Sync Header Alignment Test Cases
Check if Sync Header Lock is asserted after the
completion of reset sequence.
The following signals in<ip_variant_name>_base.v are tapped:
The rxlink_clk is used as the sampling
clock for the Signal Tap.
The j204c_rx_dev_lane_align is asserted after the
assertion of j204c_rx_emb_lock and next LEMC event.
signal is deasserted if there is no error.
1.3.2. Receiver Transport Layer (TL)
To check the data integrity of the payload data stream through the receiver
Intel® FPGA IP and transport layer, the
ADC is configured to ramp/PRBS test pattern. The ADC is also set to operate with the
same configuration as set in the JESD204C
Intel® FPGA IP. The ramp/PRBS checker in the FPGA fabric checks the ramp/PRBS data integrity for
one minute. The RX JESD204C
Intel® FPGA IP register
rx_err is polled continuously for zero value
for one minute.
The figure below shows the conceptual test setup for data integrity
Figure 3. Data Integrity Check Using Ramp/PRBS15 Checker
Table 3. Transport Layer Test Cases
Check the transport layer mapping of the data
channel using ramp test pattern.
The following signals in <ip_variant_name>_base.v are tapped:
3 S is the number
of transmitted samples per converter per
4 WIDTH_MULP is the
data width multiplier between the application layer and
5 N is the number
of conversion bits per converter.
6 CS is the number
of control bits per conversion samples.
1.3.3. Deterministic Latency - Subclass 1 (DL)
Deterministic Latency Measurement Block Diagram
shows the conceptual test setup for deterministic latency measurement. The HMC7044 is
configured to provide a periodic SYSREF to both AD9081 and JESD204C
Intel® FPGA IP in FPGA with the required extended multiblock period.
The deterministic latency measurement block
the deterministic latency by measuring the number of frame clock counts
between the assertion of the rx_dl_signal signal and logic OR
of the MSB bit of all sample at the output of the RX JESD204C
Intel® FPGA IP after the link is established
the assertion of j204c_rx_avst_valid.
Note: The voltage
is using the resistor divider circuit in the rx_dl_signal signal
path to match
the voltage level of the FPGA output and AD9081 ADC input.
The deterministic latency measurement block in System
has a counter to measure the link clock count.
The link clock count value should only drift within 1-2 link clocks for at least
10 power cycle test.
1.4. JESD204C Intel FPGA IP and ADC Configurations
Intel® FPGA IP parameters (L, M,
and F) in this hardware checkout are natively supported by the AD9081 device. The transceiver
data rate, sampling clock, and other JESD204C parameters comply with the AD9081 operating
The hardware checkout testing implements the JESD204C
Intel® FPGA IP with the following parameter configuration.
Global setting for all configuration:
CF = 0
CS = 0
Subclass = 1
SH_CONFIG = CRC-12
FPGA Management Clock (MHz) = 100
Note: The other configurations are
retained at default values.
7 The device clock frequency of the E-tile transceiver is the same as the core PLL of the JESD204C
Intel® FPGA IP.
8 The frame clock and link clock are derived from the device clock by using an internal core PLL.
1.5. Test Results
The following table contains the possible results and their
Table 6. Results Definition
The Device Under Test (DUT) was observed to exhibit
PASS with comments
The DUT was observed to exhibit conformant behavior.
However, an additional explanation of the situation is included
(example: due to time limitations, only a portion of the testing was
The DUT was observed to exhibit non-conformant
The DUT was observed to exhibit behavior that is not
Refer to comments
From the observations, a valid pass or fail could not
be determined. An additional explanation of the situation is
The following table shows the results for test cases SHA.1, SHA.2,
EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2 with different values of L, M, F, data rate,
sampling clock, link clock, and SYSREF frequencies.
Table 7. Result for Test Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and
9 The frame
clock and link clock are derived from the core clock using an
1.6. Test Result Comments
In each test case, the RX JESD204C
Intel® FPGA IP successfully establishes the sync header alignment, extended multiblock alignment, and until user data phase.
No data integrity issue is observed by the ramp checker for JESD configurations at different lanes rates covering all physical lanes, also no cyclic redundancy check (CRC) and command parity error is observed.
In the deterministic latency measurement, consistent RBD count and total latency between the AD9081 ADC input and the JESD
Intel® FPGA IP transport layer output are observed across multiple power cycles or resets.
To avoid lane de-skew error and achieve deterministic latency, the LEMC or RBD offset need to be programmed in the JESD204C RX IP for a few JESD configurations. The modes as stated in the table below.
Default. Compile-time specific.
Default. Compile-time specific.
1.7. Document Revision History for AN 927: JESD204C Intel FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Stratix 10 E-Tile Devices
Quartus® Prime Pro Edition software version
19.4.0 Build 64 is used for compilation of designs.
The ADC supports over 100 JESD204C operating modes, all of which are also supported by the JESD204C
Intel® FPGA IP. The 13 ADC modes that are tested represent a set of popular JESD204C parameters to demonstrate broad interoperability across all modes supported by the ADC.