This document demonstrates how to debug an
Arria® 10 Partial Reconfiguration design with the Signal Tap Logic Analyzer.
This application note extends the Partial Reconfiguration (PR) work presented on
AN 797: Partially Reconfiguring a Design on
Arria® 10 GX FPGA Development Board to a verification environment.
The Signal Tap Logic Analyzer captures and displays real-time signal behavior
in an FPGA design, allowing to examine the behavior of internal signals during normal
device operation without the need for extra I/O pins or external lab
Partial Reconfiguration is
an advanced design flow that allows you to reconfigure a portion of the FPGA
dynamically, while the remaining FPGA design continues to function. You can define
multiple personas to occupy the same design region, without impacting operation in
PR support in the Signal Tap Logic Analyzer
data acquisition in static and PR regions. Moreover, you can debug multiple personas present in a PR region and
multiple PR regions.
Debugging a PR design requires planning. Before compiling, you must
decide whether you want to tap signals in the static region, which PR region you
want to debug, and which personas in the PR region you want to debug.
To ensure visibility, the debugging fabric must extend to all the
regions that you want to tap. The
software performs this extension with debug bridge components: the SLD JTAG Bridge
Intel® FPGA IP and the SLD JTAG Bridge Host
Intel® FPGA IP.
To incorporate these components to the design, for each PR region in the design that
you want to debug:
Instantiate the SLD JTAG Bridge
in the static region.
Instantiate the SLD JTAG Bridge
in the PR region of the default persona.
Instantiate the SLD JTAG Bridge
that you want to debug.
Figure 1. Debug Fabric in PR Design with Signal TapThe figure shows in solid outline the entities that you
instantiate manually, and in dashed outline the entities that the Compiler
SLD JTAG Bridge Index
The index is an attribute of the SLD JTAG Bridge Agent that uniquely
identifies bridge agents present in the design. You can find information regarding
the bridge index in the synthesis report (<base
revision>.syn.rpt), by looking under JTAG
Bridge Agent Instance Information. The bridge index for the root partition
is always None.
Figure 2. JTAG Bridge Agent Instance Information in Synthesis Report
To perform this tutorial, you need the following software and
Quartus® Prime Pro Edition software version 18.1
or later. The software includes the Signal Tap Logic Analyzer and the Programmer.
Arria® 10GX FPGA development kit, or a design board with JTAG
connection to the device under test.
Intel® FPGA Download Cable, for communication between the
device and the
Quartus® Prime software.
Tutorial Design Description
The design for this tutorial consists of one 32-bit counter. At the board
level, the design connects the clock to a 50MHz source, and connects the output to four LEDs
on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs
to blink at a specific frequency.
Figure 3. Flat Reference Design without PR Partitioning
Downloading the Tutorial Design
The partial reconfiguration tutorial files are available in:
In the web page, click Clone or
download, and then click Download
Unzip the fpga-partial-reconfig-master.zip file.
Navigate to the tutorials/a10_pcie_devkit_blinking_led_stp
sub-folder to access the design.
Tutorial Design Files
The design folder contains two subfolders: The start folder contains the files that you need to
follow this tutorial, and the finish folder
contains the complete set of files you create using this application note. Reference
these files at any point during the walkthrough.
Table 1. Description of Tutorial Design Files in start Folder
Contains the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.
This module also instantiates the SLD JTAG Bridge Agent for debugging purposes.
Top-level 32-bit counter that controls LED directly. The registered output of the counter controls LED, and powers LED and LED via the blinking_led module.
Defines the timing constraints for the project.
This module acts as the PR partition. The module receives the registered output of top_counter module, which controls LED and LED.This module also instantiates the SLD JTAG Bridge Agent for debugging the default persona.
Quartus® Prime project file that contains a list of all the revisions in the project.
Quartus® Prime settings file that contains assignments and settings for the base revision of the project.
Contains assignments and settings for the blinking_led_default implementation revision of the project.
Contains assignments and settings for the blinking_led_slow implementation revision of the project.
Contains assignments and settings for the blinking led empty of the project.
Slower version of the PR logic. On this version, the led blinks at a slower rate than the default PR persona.
The module receives the registered output of top_counter module, which controls LEDand LED. This module also instantiates the SLD JTAG Bridge Agent for debugging the default persona.
Empty version of the PR logic. This module holds the outputs at a constant.
The module receives the registered output of top_counter module, which controls LED and LED. This module also instantiates the SLD JTAG Bridge Agent for debugging the default persona.
Arria® 10 Partial Reconfiguration Controller IP. This
Intel® FPGA IP enables PR over a JTAG connection.
The following Figure shows the list of files in the finish folder:
Figure 4. Tutorial Design Files in finish Folder
This tutorial describes preparing the blinking_led design for debug
with the Signal Tap Logic Analyzer.
Note:This Application Note only covers adding
Signal Tap debugging capabilities to a PR design. For
information about turning a non-PR design to PR, refer toAN 797: Partially Reconfiguring a Design on
Arria® 10 GX FPGA Development Board
To tap signals
in a PR design, you extend the debug fabric to the PR regions when creating the base
revision, and then define debug components for the implementation
This step extends the debug fabric to the PR
regions that you want to debug.
To accomplish this goal, you must
instantiate the SLD JTAG Bridge Agent in the static region and the SLD JTAG Bridge Host in
the default persona of the PR region.
Preparing the Static Region
In the IP Catalog (Tools > IP Catalog), type SLD JTAG Bridge Agent, and
double-click the SLD JTAG Bridge Agent
Intel® FPGA IP.
In the Create IP
Variant dialog box, type sld_agent as the file name, and then click Create.
Figure 5. Create IP Variant Dialog Box
In the parameter editor, use the default parameterization for
sld_agent. Click Generate
HDL..., and then click Generate.
Figure 6. SLD JTAG Bridge Agent
Intel® FPGA IP
The parameter editor generates the sld_agent.ip IP variation file and adds the file to the
Close the parameter editor.
Verify whether the sld_agent IP variant
appears in the IP Components tab of the
Figure 7. sld_agent IP Variant in Project Navigator
If the IP variant does not appear in the Project Navigator, click Project > Add/Remove Files in Project, find the sld_agent.ip file, and add to the project.
In the top.sv file,
instantiate the sld_agent IP in the base
revision by uncommenting the following lines:
You specify the acquisition parameters in the Signal Configuration pane of the Signal Tap
Figure 15. Signal Configuration Pane
Add Acquisition Clock
Specify the reference clock that Signal Tap uses during acquisition.
Perform the following steps in the Signal
Next to Clock, click
… to open the Node Finder.
Set the following search parameters:
Figure 16. Search Parameters to Find the Clock
Figure 17. Select Clock in Node Finder
Select clock, click
>, and then click OK.
Add Storage Parameters
Storage parameters define the number of samples the Signal Tap Logic Analyzer captures and stores, how to organize this samples, and the location of the sample with respect to the trigger activation.
In Sample Depth, select 128.
In Storage Qualifier, set Type as
In Trigger Position, select Center Trigger
Figure 18. Acquisition Settings for Tutorial
Step 6: Setting Trigger Conditions
These steps direct the Signal Tap
Logic Analyzer to record data only after u_blinking_led|led_three_on
or u_blinking_led|led_two_on does a rising edge
In the Setup tab of the Signal Tap
Logic Analyzer window, turn on the box under the Trigger
Open the drop-down menu and select Basic OR.
For u_blinking_led|led_three_on and
u_blinking_led|led_two_on, turn on Trigger
Enable and select Rising Edge as the
For all the other signals, turn off Trigger
Figure 19. Trigger Conditions
Defining trigger conditions completes the Signal Tap instance configuration. Now you can compile the design.
Step 7: Generating Programming Files
The design is now ready for compilation. The
Quartus® Prime Compiler generates files that you then program into the FPGA. This Partial Reconfiguration design requires generating .sof and .rbf files.
Ensure the blinking_led.qsf contains the following assignments:
set_global_assignment -name GENERATE_PR_RBF_FILE ON
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
These assignments allow the assembler to automatically generate the required PR bitstreams.
Quartus® Prime GUI, click Processing > Start Compilation to compile the base revision.