Macro:

#define DEBUG_AC_INT_WARNING

If you use this macro, declare it in your code before you declare #include HLS/ac_int.h.

Compiler command line option:

-D DEBUG_AC_INT_WARNING

Enables runtime tracking of ac_int datatypes during x86 emulation (the -march=x86-64 option, which the default option, of the i++ command).

This tool uses additional resources for tracking the overflow and empty constructors, and emits a warning for each detected overflow.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_int_overflow

Macro:

#define DEBUG_AC_INT_ERROR

If you use this macro, declare it in your code before you declare #include HLS/ac_int.h.

Compiler command line option:

-D DEBUG_AC_INT_ERROR

Enables runtime tracking of ac_int datatypes during x86 emulation of your component (the -march=x86-64 option, which the default option, of the i++ command).

This tool uses additional resources to track the overflow and empty constructors, and emits a message for the first overflow that is detected and then exits the component with an error.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_int_overflow

Changing a stable argument during component execution results in undefined behavior; each use of the stable argument might be the old value or the new value, but with no guarantee of consistency. The same variable in the same invocation can appear with multiple values.

Stable arguments can be used with conduits, mm_master interfaces, and slave_registers.

component int dut(
   hls_stable_argument int a,
   hls_stable_argument int b) {
 return a * b;}

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/interfaces/stable_arguments

This can have an adverse effect on the f_MAX of your component because using this pragma to get a lower loop II combines pipeline stages together and creates logic with a long propagation delay.

Using this pragma with a larger loop II inserts more pipeline stages and can give you a better component f_MAX value.

#pragma ii 2
for (int i = 0; i < 8; i++) {
 // Loop body
}

It can accept an optional argument that specifies the name of the array. If array is not specified, all component memory dependencies are ignored. If there are loop-carried dependencies, your generated RTL produces incorrect results.

The safelen parameter specifies the dependency distance. The dependency distance is the number of iterations between successive load/stores that depend on each other. It is safe to not include safelen is only when the dependence distance is infinite (that is, there are no real dependencies).

#pragma ivdep safelen(2)
for (int i = 0; i < 8; i++) {
 // Loop body
}

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/loop_memory_dependency

#pragma loop_coalesce 2
for (int i = 0; i < 8; i++) {
 for (int j = 0; j < 8; j++) {
 // Loop body 
 } 
}

#pragma unroll 8
for (int i = 0; i < 8; i++) {
 // Loop body
}

To learn more, review the tutorial: <quartus_installdir>/hls/examples/best_practices/resource_sharing_filter

This pragma is useful mainly when component memory is duplicated to improve the throughput of the loop. This is mentioned in the details pane for the loop in the Loop Analysis pane of the high level design report (report.html).

This can occur only when the scope of a component memory (through its declaration or access pattern) is limited to this loop. Adding this pragma can be used to reduce the area that the loop consumes at the cost of some throughput.

// Without this pragma,
// multiple copies 
// of the array "arr"
#pragma max_concurrency 1
for (int i = 0; i < 8; i++) {
 int arr[1024];
 // Loop body
}

extern "C" int myComponent(int a, int b)

Using the component function attribute is preferred over using the --component command option to indicate functions that you want the compiler to synthesize.

In Pro Edition, the compiler always promotes integers for standard types. Use the ac_int datatypes if you want smaller (or larger) datatypes.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/integer_promotion

If you do not specify this option, --simulator modelsim is assumed.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/single_vs_double_precision_math

To learn more, review the design: <quartus_installdir>/hls/examples/QRD

Provides arbitrary width integer support.

Provides arbitrary precision fixed point support.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_fixed_constructor

Provides arbitrary precision fixed point math functions.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_fixed_math_library

This macro ensures that statements in a component work in x86 emulations but are disabled in the component when compiling to an FPGA architecture.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/usability/enqueue_call

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/usability/enqueue_call

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/usability/enqueue_call

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init

component int foo(int val) {
 // function definition
}

component void bar (int val) {
 // function definition
}
int main() {
   // ……. 
   int input = 0;
   int res[5];
   ihc_hls_enqueue(&res, &foo, input);
   ihc_hls_enqueue_noret(&bar, input);
   input = 1;
   ihc_hls_enqueue(&res, &foo, input);
   ihc_hls_enqueue_noret(&bar, input);
   ihc_hls_component_run_all(&foo);
   ihc_hls_component_run_all(&bar);
} 

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/swap_vs_copy

To learn more, review the design: <quartus_installdir>/hls/examples/QRD

That is, the memory is clocked at the same operating frequency as the operating frequency of your component.

To learn more, review the design: <quartus_installdir>/hls/examples/QRD

That is, the memory is clocked at twice the operating frequency of your component.

To learn more, review the design: <quartus_installdir>/hls/tutorials/component_memories/bank_bits

If you do not specify the hls_bankwidth(N) attribute along with this attribute, then b ₀ , b ₁ , ..., b _n are mapped to array index bits 0 to n-1 in the memory bank implementation.

To learn more, review the design: <quartus_installdir>/hls/tutorials/component_memories/bank_bits

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/depth_wise_merge

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/width_wise_merge

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/ static_var_init

This can have an adverse effect on the f_MAX of your component because using this pragma to get a lower loop II combines pipeline stages together and creates logic with a long propagation delay.

Using this pragma with a larger loop II inserts more pipeline stages and can give you a better component f_MAX value.

#pragma ii 2
for (int i = 0; i < 8; i++) {
 // Loop body
}

It can accept an optional argument that specifies the name of the array. If array is not specified, all component memory dependencies are ignored. If there are loop-carried dependencies, your generated RTL produces incorrect results.

The safelen parameter specifies the dependency distance. The dependency distance is the number of iterations between successive load/stores that depend on each other. It is safe to not include safelen is only when the dependence distance is infinite (that is, there are no real dependencies).

#pragma ivdep safelen(2)
for (int i = 0; i < 8; i++) {
 // Loop body
}

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/loop_memory_dependency

#pragma loop_coalesce 2
for (int i = 0; i < 8; i++) {
 for (int j = 0; j < 8; j++) {
 // Loop body 
 } 
}

#pragma unroll 8
for (int i = 0; i < 8; i++) {
 // Loop body
}

To learn more, review the tutorial: <quartus_installdir>/hls/examples/best_practices/resource_sharing_filter

This pragma is useful mainly when component memory is duplicated to improve the throughput of the loop. This is mentioned in the details pane for the loop in the Loop Analysis pane of the high level design report (report.html).

This can occur only when the scope of a component memory (through its declaration or access pattern) is limited to this loop. Adding this pragma can be used to reduce the area that the loop consumes at the cost of some throughput.

// Without this pragma,
// multiple copies 
// of the array "arr"
#pragma max_concurrency 1
for (int i = 0; i < 8; i++) {
 int arr[1024];
 // Loop body
}

You can use this attribute to request more copies of the local memory so that the component can run multiple invocations in parallel.

hls_max_concurrency(2)
void foo(ihc::stream_in<int> &data_in,
      ihc::stream_out<int> &data_out) {
 int arr[N];
 for (int i = 0; i < N; i++) {
 arr[i] = data_in.read();
 }
 // Operate on the data and modify in place
 for (int i = 0; i < N; i++) {
 data_out.write(arr[i]);
 }
}

To learn more, review the design example: <quartus_installdir>/hls/examples/inter_decim_filter

(component call and return)

The component return is also implemented as an interface that includes the component done and stall signals.

(passed by value)

(passed by reference)

By default, the base address is treated as a scalar parameter so it is implemented as a conduit that is synchronized to the component invocation interface.

A memory mapped interface is also exposed on the component.

This is the default component invocation interface.

Top-level module ports:

Function call—start, busy

Function return—done, stall

component hls_avalon_streaming_component void foo(/*component arguments*/)

These component must take either slave, stream, or stable arguments. If you do not specify these types of arguments, the compiler generates an error message when you compile this component.

Top-level module ports: Avalon-MM slave interface and irq_done signal

component hls_avalon_slave_component void foo(/*component arguments*/)

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/interfaces/mm_slaves

Use this protocol when the component datapath relies only on explicit streams for data input and output.

IP verification does not support components with this component invocation protocol.

Top-level module ports: None

component hls_always_run_component void foo(/*component arguments*/)

This feature can be used with the hls_avalon_streaming_component, hls_avalon_slave_component, and hls_always_run_component arguments. This attribute can be used to specify that the downstream component is stall free.

component hls_stall_free_return component int dut(int a, int b)
 { return a * b;}

This is the default interface for scalar arguments.

Changes to the value of this argument made by the component data path will not be reflected on this register.

component void foo( 
  hls_avalon_slave_register_argument int b)

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/interfaces/mm_slaves

If the compiler performs static coalescing optimizations, the slave interface's data width will be the coalesced width. This attribute applies only to a pointer argument.

component void foo(
   hls_avalon_slave_memory_argument(128*sizeof(int)) int *a)

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/interfaces/mm_slaves

Changing a stable argument during component execution results in undefined behavior; each use of the stable argument might be the old value or the new value, but with no guarantee of consistency. The same variable in the same invocation can appear with multiple values.

Stable arguments can be used with conduits, mm_master interfaces, and slave_registers.

component int dut(
   hls_stable_argument int a,
   hls_stable_argument int b) {
 return a * b;}

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/interfaces/stable_arguments

The width of the stream data bus is equal to a width of sizeof(datatype).

The testbench must populate this buffer (stream) fully before the component can start to read from the buffer.

This parameter is available only on input streams.

Data is broken down according to how you set the ihc::firstSymbolInHighOrderBits declaration. By default, data is broken down in little endian order.

Data is always broken down in little endian order.

Exposes the empty out-of-band signal on the stream interface.

Use this declaration only with streams that read more than one data symbol per clock cycle.

The empty signal indicates the number of symbols on the data bus that do not represent valid data during the final stream read of a packet.

You can control whether the empty symbols are in the low-order bits or high-order bits with the ihc::firstSymbolInHighOrderBits declaration.

This is equivalent to changing the stream read calls to tryRead and assuming that success is always true.

If set to false, buffer and readyLatency must be 0.

 // Blocking read
void foo (ihc::stream_in<int> &a) {
 int x = a.read(); 

}
 // Non-blocking read
void foo_nb (ihc::stream_in<int> &a) {
 bool success = false;
 int x = a.tryRead(success);

 if (success) {
 // x is valid
 }
}

int main() {
 ihc::stream_in<int> a;
 ihc::stream_in<int> b;
 for (int i = 0; i < 10; i++) {
  a.write(i);
  b.write(i);
 }
 foo(a);
 foo_nb(b);
}

Available only if usesPackets<true> is set.

Blocking read with out-of-band startofpacket, endofpacket, and empty signals.

If you use tryRead, your x86-64 results for your component might not match your FPGA results because emulation does not model the hardware behavior of blocking and non-blocking reads.

Available only if usesPackets<true> is set.

Non-blocking read with out-of-band startofpacket, endofpacket, and emptysignals.

Available only if usesPackets<true> is set.

Blocking write call with out-of-band startofpacket, endofpacket, and empty signals.

Conceptually, you can view this parameter as an almost ready latency on the input FIFO buffer for the data that associates with the stream.

Data is broken down according to how you set the ihc::firstSymbolInHighOrderBits declaration. By default, data is broken down in little endian order.

Data is always broken down in little endian order.

Exposes the empty out-of-band signal on the stream interface.

Use this declaration only with streams that write more than one data symbol per clock cycle.

The empty signal indicates the number of symbols on the data bus that do not represent valid data during the final stream write of a packet.

You can control whether the empty symbols are in the low-order bits or high-order bits with the ihc::firstSymbolInHighOrderBits declaration.

If set to false, readyLatency must be 0.

// Blocking write
void foo (ihc::stream_out<int> &a) {
  static int count = 0;
  for(int idx = 0; idx < 5; idx ++){
    a.write(count++); // Blocking write
  }
}

// Non-blocking write
void foo_nb (ihc::stream_out<int> &a) {
  static int count = 0;
  for(int idx = 0; idx < 5; idx ++){
    bool success = a.tryWrite(count++); // Non-blocking write
    if (success) {
      // write was successful
    }
  }
}

int main() {
  ihc::stream_out<int> a;
  foo(a); // or foo_nb(a);
  
  // copy output to an array
  int outputData[5];
  for (int i = 0; i < 5; i++) {
    outputData[idx] = a.read();
  }
}

Available only if usesPackets<true> is set.

Blocking write with out-of-band startofpacket, endofpacket, and empty signals.

Available only if usesPackets<true> is set.

Non-blocking write with out-of-band startofpacket, endofpacket, and empty signals. The return value represents whether the write was successful.

Available only if usesPackets<true> is set.

Blocking read call to be used from the testbench to read back the data from the component with out-of-band startofpacket, endofpacket, and empty signals.

Avalon^® Memory-Mapped (MM) Master interface argument: Multiple template arguments are supported.

The template arguments are listed below.

Any combination can be used as long as it describes a valid hardware configuration.

component int dut(
 ihc::mm_master<int, 
   ihc::aspace<2>, ihc::latency<3>,
   ihc::awidth<10>, ihc::dwidth<32>
  > &a)

This value affects only the width of the Avalon^® MM Master interface. The size of the conduit of the base address pointer is always set to 64-bits.

For fixed latency interfaces, this value must be set to 1.

For more details, review information about burst signals and the burstcount signal role in "Avalon Memory-Mapped Interface Signal Roles" in Avalon Interface Specifications.

The Intel^® HLS Compiler uses this information to determine how many simultaneous loads and stores this pointer can permit.

For example, if you have a bus with 4 32-bit integers on it, you should use ihc::dwidth<128> (bits) and ihc::align<16> (bytes). This means that up to 16 contiguous bytes (or 4 32-bit integers) can be loaded or stored as a coalesced memory word per clock cycle.

Adds the waitrequest signal that is asserted by the slave when it is unable to respond to a read or write request. For more information about the waitrequest signal, see "Avalon Memory-Mapped Interface Signal Roles" in Avalon Interface Specifications.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_fixed_constructor

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_fixed_math_library

Macro:

#define DEBUG_AC_INT_WARNING

If you use this macro, declare it in your code before you declare #include HLS/ac_int.h.

Compiler command line option:

-D DEBUG_AC_INT_WARNING

Enables runtime tracking of ac_int datatypes during x86 emulation (the -march=x86-64 option, which the default option, of the i++ command).

This tool uses additional resources for tracking the overflow and empty constructors, and emits a warning for each detected overflow.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_int_overflow

Macro:

#define DEBUG_AC_INT_ERROR

If you use this macro, declare it in your code before you declare #include HLS/ac_int.h.

Compiler command line option:

-D DEBUG_AC_INT_ERROR

Enables runtime tracking of ac_int datatypes during x86 emulation of your component (the -march=x86-64 option, which the default option, of the i++ command).

This tool uses additional resources to track the overflow and empty constructors, and emits a message for the first overflow that is detected and then exits the component with an error.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/ac_datatypes/ac_int_overflow