Intel High Level Synthesis Compiler: Getting Started Guide

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UG-20036 | 2018.09.24

Intel High Level Synthesis (HLS) Compiler Getting Started Guide

The Intel^® High Level Synthesis (HLS) Compiler is part of Intel^® Quartus^® Prime design software. The Intel^® HLS Compiler synthesizes a C++ function into an RTL implementation that is optimized for Intel^® FPGA products. The compiler is sometimes referred to as the i++ compiler, reflecting the name of the compiler command.

The Intel^® High Level Synthesis Compiler Getting Started Guide describes the procedures to set up the Intel^® HLS Compiler and to run an HLS design example.

The features and devices supported by the Intel^® HLS Compiler depend on what edition of Intel^® Quartus^® Prime you have. The following icons indicate content in this publication that applies only to the Intel^® HLS Compiler provided with a certain edition of Intel^® Quartus^® Prime:

: Indicates that a feature or content applies only to the Intel^® HLS Compiler provided with Intel^® Quartus^® Prime Pro Edition.
: Indicates that a feature or content applies only to the Intel^® HLS Compiler provided with Intel^® Quartus^® Prime Standard Edition.

In this publication, <quartus_installdir> refers to the location where you installed Intel^® Quartus^® Prime Design Suite. The Intel^® High Level Synthesis (HLS) Compiler is installed as part of your Intel^® Quartus^® Prime Design Suite installation.

The default Intel^® Quartus^® Prime Design Suite installation location depends on your operating system and your Intel^® Quartus^® Prime edition:

Windows: C:\intelFPGA_pro\
Linux: /home/<username>/intelFPGA_pro/

Windows: C:\intelFPGA_standard\
Linux: /home/<username>/intelFPGA_standard/

Intel High Level Synthesis Compiler Prerequisites

The Intel^® HLS Compiler is installed as part of the Intel^® Quartus^® Prime software installation, but it requires additional software to use.

For detailed instructions about installing Intel^® Quartus^® Prime software, including system requirements, prerequisites, and licensing requirements, see Intel^® FPGA Software Installation and Licensing .

The Intel^® HLS Compiler requires the following additional software:

C++ Compiler

For Linux, install one of the following versions of the GCC compiler and C++ libraries, depending on your edition of Intel^® Quartus^® Prime software:

GCC compiler and C++ Libraries version 5.4.0
You must install these libraries manually. See Installing the Intel^® HLS Compiler on Linux Systems for instructions.
GCC compiler and C++ Libraries version 4.4.7
These libraries are included in the version of Linux supported by the Intel^® HLS Compiler.

Important: The Intel^® HLS Compiler software does not support versions of the GCC compiler other than those specified for the edition of the software.

For Windows, install one of the following versions of the Microsoft Visual Studio Professional, depending on your edition of Intel^® Quartus^® Prime software:

Microsoft Visual Studio 2015 Professional
Microsoft Visual Studio 2010 Professional

Important: The Intel^® HLS Compiler software does not support versions of Microsoft Visual Studio other than those specified for the edition of the software.

Mentor Graphics* ModelSim* Software

You can install the ModelSim* software from the Intel^® Quartus^® Prime software installer. The available options are:

ModelSim* - Intel^® FPGA Edition
ModelSim* - Intel^® FPGA Starter Edition

Alternatively, you can use your own licensed version of Mentor Graphics* ModelSim* software.

On Linux systems, ModelSim* software requires the Red Hat development tools packages. Additionally, any 32-bit versions of ModelSim* software (including those provided with Intel^® Quartus^® Prime) require additional 32-bit libraries. The commands to install these requirements are provided in Installing the Intel^® HLS Compiler on Linux Systems.

For information about all the ModelSim* software versions that the Intel^® software supports, refer to the EDA Interface Information section in the Software and Device Support Release Notes for your edition of Intel^® Quartus^® Prime

Installing the Intel HLS Compiler on Linux Systems

You must have administration privileges to install the Intel^® HLS Compiler.

To install the Intel^® HLS Compiler on Linux Systems:

Confirm that your operating system version is supported by the Intel^® HLS Compiler:

Option	Description
	Red Hat Enterprise Linux 6.x, or a community equivalent Red Hat Enterprise Linux 7.x, or a community equivalent
	Red Hat Enterprise Linux 6.x, or a community equivalent

Install Intel^® Quartus^® Prime (including ModelSim* , if needed).

For detailed instructions about installing Intel^® Quartus^® Prime software, including system requirements, prerequisites, and licensing requirements, refer to Intel^® FPGA Software Installation and Licensing .
Refresh your Linux repositories with the sudo yum update command.
Install one of the following versions depending on your edition of the Intel^® Quartus^® Prime software:
- GCC compiler and C++ Libraries version 5.4.0
  To download the required tools and source files, and compile GCC compiler and C++ Libraries version 5.4.0, run the following commands:
```
sudo yum groupinstall "Development Tools" "Additional Development"

cd <quartus_installdir>¹/hls/

./install_gcc
```
  The install_gcc command runs a script that downloads and compiles GCC compiler and C++ Libraries version 5.4.0 in the /home/<username>/build/gcc folder. The script installs this version of the GCC compiler alongside the Intel^® HLS Compiler so that the Intel^® HLS Compiler can access the required libraries without any further action on your part.
  
  If you want to maintain your own GCC installation, run the script with the -i flag to specify a different GCC installation directory. However, if you specify a different GCC installation directory, you must always specify the --gcc-toolchain option every time you run the Intel^® HLS Compiler i++ command. For details about the --gcc-toolchain option, see Intel^® HLS Compiler Command Options in Intel^® HLS Compiler Reference Manual.
  
  For more options of the install_gcc command, use the command help option: ./install_gcc -h.
- GCC compiler and C++ Libraries version 4.4.7
  You can install GCC compiler and C++ Libraries version 4.4.7 with the following command:
```
sudo yum groupinstall "Development Tools"
```
If you want the Intel^® HLS Compiler to simulate your components with the 32-bit Mentor Graphics* ModelSim* software provided with Intel^® Quartus^® Prime, install the required additional 32-bit libraries with the following command:
```
sudo yum install -y glibc.i686 glibc-devel.i686 libX11.i686 \
				libXext.i686 libXft.i686 libgcc.i686 libgcc.x86_64 \
				libstdc++.i686 libstdc++-devel.i686 ncurses-devel.i686 \
				qt.i686 qt-x11.i686
```

After completing these steps, the Intel^® HLS Compiler is installed on your system. Before you can compile your component with the Intel^® HLS Compiler i++ command, you must initialize your Intel^® HLS Compiler environment for the i++ command to run successfully. For details, see Initializing the Intel HLS Compiler Environment.

¹ Where <quartus_installdir> is the directory where you installed the Intel^® Quartus^® Prime Design Suite. For example, C:\intelFPGA_pro\18.1.

Installing the Intel HLS Compiler on Microsoft* Windows* Systems

To install the Intel^® HLS Compiler on Microsoft^* Windows^* Systems:

Confirm that your operating system version is supported by the Intel^® HLS Compiler (Microsoft* Windows* 7 SP1, 8.1 or 10).
Install one of the following software products, depending on your edition of the Intel^® Quartus^® Prime software:
- Microsoft Visual Studio 2015 Professional
- Microsoft Visual Studio 2010 Professional
Important: The Intel^® HLS Compiler software does not support versions of Microsoft Visual Studio other than those specified for the edition of the software.
If you have multiple versions of Visual Studio, Microsoft recommends installing Visual Studio versions in the order in which the versions were released. For example, install Visual Studio 2010 before installing Visual Studio 2015. For details, see Install Visual Studio Versions Side-by-Side in the MSDN Library.
Install Intel^® Quartus^® Prime (including ModelSim* , if needed).

For detailed instructions about installing Intel^® Quartus^® Prime software, including system requirements, prerequisites, and licensing requirements, refer to the Intel^® FPGA Software Installation and Licensing .

Initializing the Intel HLS Compiler Environment

Before you can compile your component with the Intel^® HLS Compiler i++ command, a number of environment variables must be set for the i++ command to run successfully.

The Intel^® HLS Compiler environment initialization script applies only to the environment variable settings in your current terminal or command prompt session. You must initialize the Intel^® HLS Compiler environment each time that you start a terminal or command prompt session to develop your design.

To initialize your current terminal or command prompt session so that you can run the Intel^® HLS Compiler:

On Linux systems, initialize your environment as follows:
1. In your terminal session, change directories to the hls directory in your Intel^® Quartus^® Prime installation directory.
  For example, /home/<username>/intelFPGA_pro/18.1/hls
2. Run the following command from the hls directory to set the environment variables for the i++ command in the current terminal session:
  
  source init_hls.sh
  
  The command prints out the modified environment variable settings.
The environment initialization script shows the environment variables that it set, and you can now run the i++ command from this terminal session.
On Windows systems, initialize your environment as follows:
1. In your command prompt session, change directories to the hls directory in your Intel^® Quartus^® Prime installation directory.
  For example, C:\intelFPGA_pro\18.1\hls
2. Run the following command from the hls directory to set the environment variables for the i++ command in the current terminal session:
  
  init_hls.bat
  
  The command prints out the modified environment variable settings.
The environment initialization script shows the environment variables that it set, and you can now run the i++ command from this command prompt session.

Tip: To set the environment variables permanently, follow your operating system's standard procedure for making persistent changes to environment variable settings. Review the output of the environment initialization script to determine the environment variables to set permanently.

High Level Synthesis (HLS) Design Examples and Tutorials

The Intel^® High Level Synthesis (HLS) Compiler includes design examples and tutorials to provide you with example components and demonstrate ways to model or code your components to get the best results from the Intel^® HLS Compiler for your design.

High Level Synthesis Design Examples

The high level synthesis (HLS) design examples give you a quick way to see how various algorithms can be effectively implemented to get the best results from the Intel^® HLS Compiler.

You can find the HLS design examples in the following location:

<quartus_installdir>/hls/examples/<design_example_name>

Where <quartus_installdir> is the directory where you installed the Intel^® Quartus^® Prime Design Suite. For example, /home/<username>/intelFPGA_pro/18.1 or C:\intelFPGA_pro\18.1 .

For instructions on running the examples, see the following sections:

Running a High Level Synthesis (HLS) Design Example (Linux)
Running a High Level Synthesis (HLS) Design Example (Windows)

Table 1. HLS design examples
Focus area	Name	Description
Linear algebra	QRD	Uses the Modified Gram-Schmidt algorithm for QR factorization of a matrix.
Signal processing	interp_decim_filter	Implements a simple and efficient interpolation/decimation filter.
Simple design	`counter`	Implements a simple and efficient 32-bit counter component.
Video processing	YUV2RGB	Implements a basic YUV422 to RGB888 color space conversion.
Video processing	image_downsample	Implements an image downsampling algorithm to scale an image to a smaller size using bilinear interpolation.

HLS Design Tutorials

The HLS design tutorials show you important HLS-specific programming concepts as well demonstrating good coding practices.

You can find the HLS design tutorials in the following location:

<quartus_installdir>/hls/examples/tutorials/<tutorial_name>

Where <quartus_installdir> is the directory where you installed the Intel^® Quartus^® Prime Design Suite. For example, /home/<username>/intelFPGA_pro/18.1 or C:\intelFPGA_pro\18.1 .

Each tutorial has a README file that gives you details about what the tutorial covers and instructions on how to run the tutorial.

Table 2. HLS design tutorials
Focus area	Name	Description
Arbitrary precision types	ac_fixed_constructor	Demonstrates the use of the `ac_fixed` constructor where you can get a better QoR by using minor variations in coding style.
	ac_fixed_math_library	Demonstrates the use of the Intel^® HLS Compiler `ac_fixed_math` fixed point math library functions.
	ac_int_basic_ops	Demonstrates the operators available for the `ac_int` class.
	ac_int_overflow	Demonstrates the usage of the `DEBUG_AC_INT_WARNING` and `DEBUG_AC_INT_ERROR` keywords to help detect overflow during emulation runtime.
Component memories	bank_bits	Demonstrates how to control component internal memory architecture for parallel memory access by enforcing which address bits are used for banking.
	depth_wise_merge	Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a depth equal to the sum of the depths of the two original memories.
	static_var_init	Demonstrates the `hls_init_on_power` and hls_init_on_reset flags for static variables and their impact on area and latency.
	width_wise_merge	Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a width equal to the sum of the widths of the two original memories.
Interfaces	overview	Demonstrates the effects on quality-of-results (QoR) of choosing different component interfaces even when the component algorithm remains the same.
	explicit_streams_buffer	Demonstrates how to use explicit stream_in and stream_out interfaces in the component and testbench.
	explicit_streams_packets_empty	Demonstrates how to use the usesPackets, usesEmpty, and firstSymbolInHighOrderBits stream template parameters.
	explicit_streams_packets_ready_valid	Demonstrates how to use the usesPackets, usesValid, and usesReady stream template parameters.
	explicit_streams_ready_latency	Demonstrates how to achieve a better loop initiation interval (II) with stream write using the `readyLatency` stream template parameter.
	mm_master_testbench_operators	Demonstrates how to invoke a component at different indicies of an Avalon Memory Mapped (MM) Master (`mm_master` class) interface.
	mm_slaves	Demonstrates how to create Avalon-MM Slave interfaces (slave registers and slave memories).
	multiple_stream_call_sites	Demonstrates the benefits of using multiple stream call sites.
	pointer_mm_master	Demonstrates how to create Avalon-MM Master interfaces and control their parameters.
	stable_arguments	Demonstrates how to use the `stable` attribute for unchanging arguments to improve resource utilization.
Best practices	ac_datatypes	Demonstrates the effect of using `ac_int` datatype instead of `int` datatype.
	const_global	Demonstrates the performance and resource utilization improvements of using `const` qualified global variables.
	floating_point_ops	Demonstrates the impact of `--fpc` and `--fp-relaxed` flags in i++ on floating point operations.
	integer_promotion	Demonstrates how integer promotion rules can influence the behavior of a C or C++ program.
	loop_coalesce	Demonstrates the performance and resource utilization improvements of using `loop_coalesce` pragma on nested loops. While the `#pragma loop_coalesce` is provided with both Standard and Pro edition, the design tutorial is provided only with Pro edition.
	loop_memory_dependency	Demonstrates breaking loop carried dependencies using the `ivdep` pragma.
	parameter_aliasing	Demonstrates the use of the __restrict keyword on component arguments. Demonstrates the use of the restrict keyword on component arguments.
	random_number_generator	Demonstrates how to use the random number generator library.
	resource_sharing_filter	Demonstrates the following versions of a 32-tap finite impulse response (FIR) filter design: optimized-for-throughput variant optimized-for-area variant
	shift_register	Demonstrates the recommended coding style for implementing shift registers.
	single_vs_double_precision_math	Demonstrates the effect of using single precision literals and functions instead of double precision literals and functions.
	struct_interface	Demonstrates how to use `ac_int` to implement interfaces with no padding bits.
	swap_vs_copy	Demonstrates the impact of using deep copying with registers on the performance and resource utilization of a component design.
Usability	compiler_interoperability	(Linux only) Demonstrates how to use testbench code compiled with GCC along with code compiled by the i++ command.
	enqueue_call	Demonstrates how to run components asynchronously and exercise their pipeline performance in the test bench using enqueue functionality.
	platform_designer_2xclock qsys_2xclock	Demonstrates the recommended clock and reset generation for a component with a `clock2x` input.
	platform_designer_stitching qsys_stitching	Demonstrates how to combine multiple components to function as a single cohesive design.

Running a High Level Synthesis (HLS) Design Example (Linux)

To run an HLS design example on Linux systems:

Start a terminal session and initialize the Intel^® HLS Compiler environment.
For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Environment.
Navigate to the <quartus_installdir>/hls/examples/<design_example_name> directory, where <quartus_installdir> is the directory where you installed Intel^® Quartus^® Prime software.
For example, /home/<username>/intelFPGA_pro/18.1 .
Run the make test-x86-64 command. This command compiles the C++ source code to an x86-64 binary executable. Then, run the generated executable on your CPU.
Expected outcome after you run the make test-x86-64 command:
- The console displays the command it uses to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files>.
- The HLS compiler creates an executable file (for example, test-x86-64) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
```
$ make test-x86-64
i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp  --fpc --fp-relaxed -march=x86-64 -o test-x86-64
+----------------------------------------+
| Run ./test-x86-64 to execute the test. |
+----------------------------------------+
```

Run the make test-fpga command. The command compiles the C++ source code to a hardware executable and then runs a simulation of the generated HDL.

Expected outcome after you run the make test-fpga command:

The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
The console displays the output of the executable to signify a successful execution.

$ make test-fpga
i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp  -v --fpc --fp-relaxed -march=Arria10 -o test-fpga
Target FPGA part name:   10AX115U1F45I1SG
Target FPGA family name: Arria 10
Target FPGA speed grade: -2
Analyzing MGS.cpp for testbench generation
Creating x86-64 testbench 
Analyzing MGS.cpp for hardware generation
Analyzing QRD_Testbench.cpp for testbench generation
Creating x86-64 testbench 
Analyzing QRD_Testbench.cpp for hardware generation
Analyzing TestbenchHelpers.cpp for testbench generation
Creating x86-64 testbench 
Analyzing TestbenchHelpers.cpp for hardware generation
Optimizing component(s) and generating Verilog files
Generating cosimulation support
Generating simulation files for components: qrd
HLS simulation directory: /data/username/HLS_Trainings/examples/QRD/test-fpga.prj/verification.
Linking x86 objects
+--------------------------------------+
| Run ./test-fpga to execute the test. |
+--------------------------------------+

Running a High Level Synthesis (HLS) Design Example (Windows)

To run an HLS design example on Windows systems:

Start a terminal session and initialize the Intel^® HLS Compiler environment.
For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Environment.
Navigate to the <quartus_installdir>\hls\examples\<design_example_name> directory, where <quartus_installdir> is the directory where you installed Intel^® Quartus^® Prime software.
For example, C:\intelFPGA_pro\18.1 .
Run the build.bat test-x86-64. This command compiles the C++ source code to an x86-64 binary executable. Then, run the generated executable on your CPU.
Expected outcome after you run the build.bat test-x86-64 command:
- The console displays the command it uses to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files>.
- The HLS compiler creates an executable file (for example, test-x86-64) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
```
C:\intelFPGA_pro\18.1\hls\examples\QRD>build.bat test-x86-64
i++ --fpc --fp-relaxed -march=x86-64 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-x86-64.exe
Run test-x86-64.exe to execute the test.
```
Run the build.bat test-fpga command. The command compiles the C++ source code to a hardware executable and then runs a simulation of the generated HDL.
Expected outcome after you run the build.bat test-fpga command:
- The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
- The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
```
C:\intelFPGA_pro\18.1\hls\examples\QRD>build.bat test-fpga
i++ --fpc --fp-relaxed -march=Arria10 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-fpga.exe
Run test-fpga.exe to execute the test.
```

Troubleshooting the Setup of the Intel HLS Compiler

This section provides information that can help you troubleshoot problems you might encounter when setting up the HLS compiler.

Intel HLS Compiler Licensing Issues

The Intel^® High Level Synthesis (HLS) Compiler is licensed as part of your Intel^® Quartus^® Prime license. However, the Intel^® HLS Compiler depends on ModelSim* software. If you use a version of ModelSim* software other than ModelSim* - Intel^® FPGA Edition or ModelSim* - Intel^® FPGA Starter Edition, ensure that your version of ModelSim* software is licensed correctly.

In some cases, you might encounter problems with the licensing for ModelSim* software.

ModelSim Licensing Error Messages

The HLS compiler issues error messages if it cannot locate the license for the installed version of ModelSim software.

If the HLS compiler fails to locate the ModelSim software license, it issues the following error message when you compile your design to the FPGA architecture:

$ i++ -march="<FPGA_family_or_part_number>" program.cpp 
HLS Elaborate cosim testbench. FAILED.
See ./a.prj/a.log for details.
Error: Missing simulator license. Either:
1) Ensure you have a valid ModelSim license
2) Use the --simulator none flag to skip the verification flow

Common causes for these errors include:

Missing, expired, or invalid licenses
Incorrect license server name in the license.dat file
Unspecified or incorrectly-specified license location

Note: The running speed of the HLS compiler might decrease if the compiler has to search the network for missing or corrupted licenses. If this problem occurs, correct the license file or license location accordingly.

LM_LICENSE_FILE Environment Variable

Intel^® and third-party software use the LM_LICENSE_FILE environment variable to specify the locations of license files or license servers. For example, both the Intel^® Quartus^® Prime software and the ModelSim^® software use the LM_LICENSE_FILE variable to specify the locations of their licenses.

Note: The time it takes for your development machine to communicate with the license server directly affects compilation time. If your LM_LICENSE_FILE environment variable setting includes paths to many license servers, or if the license server is hosted in a distant locale, you will notice a significant increase in compilation time.

On Linux or UNIX systems, insert a colon (:) after each license file or license server location that you append to the LM_LICENSE_FILE environment variable.

On Windows systems, insert a semicolon (;) after each license file or license server location that you append to the LM_LICENSE FILE environment variable.

Note: When modifying the LM_LICENSE_FILE setting to include the locations of your software licenses, do not remove any existing license locations appended to the variable.

ModelSim Software License-Specific Considerations

When setting up the ModelSim^® software license, you need to append the license location to the LM_LICENSE_FILE environment variable. However, you can also append the location of the ModelSim software license to the MGLS_LICENSE_FILE environment variable.

For Mentor Graphics^® applications, including the ModelSim software, you can specify the paths to license files and license servers in five different locations. If you specify paths to license files or license servers in multiple locations, the following search order is used to find the first valid path:

MGLS_LICENSE_FILE environment variable you set in the user environment
MGLS_LICENSE_FILE environment variable you set in the registry
LM_LICENSE_FILE environment variable you set in the environment
LM_LICENSE_FILE environment variable you set in the registry
<path to FLEXlm>\license.dat, where <path to FLEXlm> is the default location of the FLEXlm license file.

When you install a Mentor Graphics product license on a computer, the MGLS_LICENSE_FILE environment variable settings take precedence over the LM_LICENSE_FILE environment variable settings. If you set both environment variables, set LM_LICENSE_FILE to point to the ModelSim license server and set MGLS_LICENSE_FILE to only point to the license server for other Mentor Graphics applications. If you only use the MGLS_LICENSE_FILE environment variable, ensure that the ModelSim license server and the license servers for other Mentor Graphics applications are on the same machine.

Document Revision History for Intel HLS Compiler Getting Started Guide

Document Version	Intel^® Quartus^® Prime Version	Changes
2018.09.24	18.1	The Intel^® HLS Compiler has a new front end. For a summary of the changes introduced by this new front end, see Improved Intel HLS Compiler Front End in the Intel High Level Synthesis Compiler Release Notes. The Intel^® HLS Compiler provided with Intel^® Quartus^® Prime Pro Edition has new prerequisites. Review Intel High Level Synthesis Compiler Prerequisites to learn more. The installation instructions for Linux systems have changed. See Installing the Intel HLS Compiler on Linux Systems for details. The best_practices/parameter_aliasing tutorial description in High Level Synthesis (HLS) Design Examples and Tutorials changed to cover the __restrict keyword. The restrict keyword is no longer supported in the Intel^® HLS Compiler Pro Edition. Removed the best_practices/integer_promotion tutorial. Integer promotion is now done by default when use the Intel^® HLS Compiler Pro Edition.
2018.05.07	18.0	Starting with Intel^® Quartus^® Prime Version 18.0, the features and devices supported by the Intel^® HLS Compiler depend on what edition of Intel^® Quartus^® Prime you have. Intel^® HLS Compiler publications now use icons to indicate content and features that apply only to a specific edition as follows: Indicates that a feature or content applies only to the Intel^® HLS Compiler provided with Intel^® Quartus^® Prime Pro Edition. Indicates that a feature or content applies only to the Intel^® HLS Compiler provided with Intel^® Quartus^® Prime Standard Edition. Added the following tutorials to the list of tutorials in High Level Synthesis (HLS) Design Examples and Tutorials: interfaces/explicit_streams_packets_empty interfaces/explicit_streams_ready_latency best_practices/ac_datatypes best_practices/loop_coalesce best_practices/random_number_generator Renamed the following tutorials to reflect some Intel^® Quartus^® Prime component name changes: usability/qsys_2xclock is now usability/platform_designer_2xclock usability/qsys_stitching is now usability/platform_designer_stitching
2017.12.22	17.1.1	Added the interfaces/overview tutorial to the list of tutorials in High Level Synthesis (HLS) Design Examples and Tutorials.
2017.12.08	17.0	Updated the Mentor Graphics* ModelSim* software requirements to include the required Red Hat development tools packages.
2017.11.06	17.0	The Intel^® High Level Synthesis (HLS) Compiler is now part of Intel^® Quartus^® Prime Design Suite, resulting in the following changes: Revised to document to reflect that you now get the Intel^® HLS Compiler by installing Intel^® Quartus^® Prime software. Removed most licensing information. Licensing the Intel^® HLS Compiler is now covered by your Intel^® Quartus^® Prime Design Suite licensing. Some third-party software required by the HLS compiler might continue to require additional licensing. Removed information about overriding compilers. Revised prerequisites to reflect only additional prerequisites required by the HLS compiler. Revised path information to reflect the new file system locations of the Intel^® HLS Compiler files. Renamed the following tutorials: The `explicit_streams` tutorial is now called `explicit_streams_buffer`. The `explicit_streams_2` tutorial is now called `explicit_streams_packets_ready_valid`.
2017.06.23	—	Minor changes and corrections.
2017.06.09	—	Updated High Level Synthesis (HLS) Design Examples and Tutorials with information about new examples. Revised Overriding the Default GCC Compiler for Intel HLS Compiler.
2017.03.14	—	Removed bit operations (3DES) from list of supplied design examples.
2017.03.01	—	Added installation of required packages and libraries needed for Linux.
2017.02.03	—	Changed success message in Quick Start sections to `PASSED`. Added HLS Design Examples and Tutorials section. Moved Running an HLS Design Example on Linux and Running an HLS Design Example on Windows to HLS Design Examples and Tutorials.
2016.11.30	—	In HLS Compiler Prerequisites, updated software requirements to note that the HLS compiler supports all ModelSim software editions that the Intel^® Quartus^® Prime software supports. In HLS Compiler Quick Start, added a note that you must run the init_hls script each time you start a shell or terminal to develop your design. In HLS Compiler Quick Start, separated the Linux and Windows instructions. In Running an HLS Design Example, separated the Linux and Windows instructions. For Linux, run the make command; for Windows, run the build.bat command. Changed the `test_x86-64` command option to `test-x86-64`. Changed the `test_fpga` command option to `test-fpga`. Removed the instruction to run the `make test_qii` command for Linux and the `build.bat test_qii` command for Windows because it is no longer necessary. In HLS Licensing Error Messages, updated the error message you will see if the HLS compiler fails to locate the ModelSim software license.
2016.09.12	—	Initial release.