Intel High Level Synthesis Compiler: Getting Started Guide
Intel High Level Synthesis (HLS) Compiler Getting Started Guide
The Intel® High Level Synthesis Compiler Getting Started Guide describes the procedures to set up the Intel® HLS Compiler and to run an HLS design example.
- Indicates that a feature or content applies only to Intel® HLS Compiler Pro Edition.
- Indicates that a feature or content applies only to Intel® HLS Compiler Standard Edition.
In this publication, <quartus_installdir> refers to the location where you installed Intel® Quartus® Prime Design Suite. The Intel® High Level Synthesis (HLS) Compiler is installed as part of your Intel® Quartus® Prime Design Suite installation.
-
- Windows
- C:\intelFPGA_pro\19.1
- Linux
- /home/<username>/intelFPGA_pro/19.1
-
- Windows
- C:\intelFPGA_standard\19.1
- Linux
- /home/<username>/intelFPGA_standard/19.1
Intel High Level Synthesis Compiler Prerequisites
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, see Intel® FPGA Software Installation and Licensing .
The Intel® HLS Compiler requires the following software in addition to Intel® Quartus® Prime:
C++ Compiler
-
GCC compiler and C++
Libraries version 5.4.0
You must install these libraries manually. See Installing the Intel® HLS Compiler on Linux Systems for instructions.
-
GCC
compiler and C++ Libraries version
4.4.7
These libraries are included in the version of Linux supported by the Intel® HLS Compiler.
- Microsoft Visual Studio 2015 Professional
- Microsoft Visual Studio 2015 Community
- Microsoft Visual Studio 2010 Professional
Mentor Graphics* ModelSim* Software
- ModelSim* - Intel® FPGA Edition
- ModelSim* - Intel® FPGA Starter Edition
On Linux systems, ModelSim* software requires the Red Hat development tools packages. Additionally, any 32-bit versions of ModelSim* software (including those provided with Intel® Quartus® Prime) require additional 32-bit libraries. The commands to install these requirements are provided in Installing the Intel® HLS Compiler on Linux Systems.
For information about all the ModelSim* software versions that the Intel® software supports, refer to the EDA Interface Information section in the Software and Device Support Release Notes for your edition of Intel® Quartus® Prime
Intel HLS Compiler Backwards Compatibility
The Intel® HLS Compiler Version 19.1 is compatible with Intel® Quartus® Prime Version 19.1, Version 18.1.1, Version 18.0.1, and Version 17.1.1. This backwards compatibility lets you to take advantage of improvements in the RTL generated by the Intel® HLS Compiler without changing the other parts of your current FPGA development environment.
- Backup the existing <quartus_installdir>/hls directory. For example, rename <quartus_installdir>/hls to <quartus_installdir>/hls_old.
- Download Intel® HLS Compiler standalone installation package from the Individual Files tab of the Intel® Quartus® Prime Download Center for your edition of Intel® Quartus® Prime.
- Run the Intel® HLS Compiler standalone installer, and specify your <quartus_installdir> directory when prompted.
You can revert to your previous version of the Intel® HLS Compiler by renaming your backup directory. Whatever version of the the Intel® HLS Compiler that in a directory called <quartus_installdir>/hls is the active version of the Intel® HLS Compiler.
Downloading the Intel HLS Compiler
Download the Intel® HLS Compiler from the Intel® Quartus® Prime Download Center. Download the Intel® HLS Compiler as part of your Intel® Quartus® Prime installation package. You can also download a separate Intel® HLS Compiler-only installation package.
Download the Intel® HLS Compiler-only installation package when you want to add the Intel® HLS Compiler to an existing Intel® Quartus® Prime installation. The Intel® HLS Compiler Version 19.1 is compatible with Intel® Quartus® Prime Version 19.1, Version 18.1.1, Version 18.0.1, and Version 17.1.1.
- Download a complete installation package from the Combined Files tab.
- Download a Quartus Prime installation package from the Individual Files tab and download the Intel® HLS Compiler installation package from the Additional Software tab. Place both installation packages in the same directory.
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, refer to Intel® FPGA Software Installation and Licensing .
The Intel® HLS Compiler standalone installation package requires that you have an existing Intel® Quartus® Prime Pro Edition installation as a target for the Intel® HLS Compiler installation.
Installing the Intel HLS Compiler on Linux Systems
You must have administrator privileges to install the Intel® HLS Compiler.
To install the Intel® HLS Compiler on Linux Systems:
-
Confirm that your operating system version is supported by the
Intel® HLS Compiler:
Option Description - Red Hat Enterprise Linux 6.x, or a community equivalent
- Red Hat Enterprise Linux 7.x, or a community equivalent
- Red Hat Enterprise Linux 6.x, or a community equivalent
-
Depending on your current system and what installation package
or packages you have downloaded, you might have to complete some additional
steps to prepare your installation:
- Installing complete
Intel®
Quartus® Prime installation package (from the Combined Files tab):
No additional steps are needed before running the installation package.
-
Installing separately downloaded
Intel®
Quartus® Prime (from Individual Files tab) and
Intel® HLS Compiler (from Additional
Software tab) installation packages:
Ensure that you have both installation packages in the same directory. The Intel® Quartus® Prime installer detects the Intel® HLS Compiler installation package and installs both software packages for you.
-
Updating the
Intel® HLS Compiler in an existing
Intel®
Quartus® Prime Pro Edition installation:
- Ensure that you have Intel® Quartus® Prime Pro Edition already installed.
- Take note of the path to your
Intel®
Quartus® Prime installation.
You need this path information to complete the Intel® HLS Compiler installation wizard.
- Rename the HLS directory in your current
Intel®
Quartus® Prime version to keep that version
as a backup.
For example, if you are installing Intel® HLS Compiler Version 19.1 into an Intel® Quartus® Prime Pro Edition Version 18.1.1 installation, rename /home/<username>/intelFPGA_pro/18.1/hls to /home/<username>/intelFPGA_pro/18.1/hls_old.
- Installing complete
Intel®
Quartus® Prime installation package (from the Combined Files tab):
-
Install the package that you downloaded in Downloading the Intel HLS Compiler.
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, refer to Intel® FPGA Software Installation and Licensing .
- Update your Linux repositories with the sudo yum update command.
-
Install one of the following versions depending on your
edition of the
Intel®
Quartus® Prime software:
-
GCC compiler and C++
Libraries version 5.4.0
To download the required tools and source files, and compile GCC compiler and C++ Libraries version 5.4.0, run the following commands:
sudo yum groupinstall "Development Tools" "Additional Development" cd <quartus_installdir>1/hls/ ./install_gcc
The install_gcc command runs a script that downloads and compiles GCC compiler and C++ Libraries version 5.4.0 in the /home/<username>/build/gcc folder. The script installs this version of the GCC compiler alongside the Intel® HLS Compiler so that the Intel® HLS Compiler can access the required libraries without any further action on your part.
If you want to maintain your own GCC installation, run the script with the -i flag to specify a different GCC installation directory. However, if you specify a different GCC installation directory, you must specify the --gcc-toolchain option every time you run the Intel® HLS Compiler i++ command. For details about the --gcc-toolchain option, see Intel® HLS Compiler Command Options in Intel® HLS Compiler Reference Manual.
For more options of the install_gcc command, use the command help option: ./install_gcc -h.
-
GCC
compiler and C++ Libraries version
4.4.7
You can install GCC compiler and C++ Libraries version 4.4.7 with the following command:
sudo yum groupinstall "Development Tools"
-
GCC compiler and C++
Libraries version 5.4.0
-
If you want the
Intel® HLS Compiler to simulate your components with the 32-bit
Mentor Graphics*
ModelSim*
software provided with
Intel®
Quartus® Prime, install the required additional 32-bit
libraries with the following command:
sudo yum install -y glibc.i686 glibc-devel.i686 libX11.i686 \ libXext.i686 libXft.i686 libgcc.i686 libgcc.x86_64 \ libstdc++.i686 libstdc++-devel.i686 ncurses-devel.i686 \ qt.i686 qt-x11.i686
-
If you use the
Mentor Graphics*
ModelSim*
software provided with
Intel®
Quartus® Prime, add the path to
ModelSim*
to your PATH
environment variable
For example:
export PATH=$PATH:<quartus_installdir>/modelsim_ase/bin
- Optional:
If you plan to use Platform Designer to
integrate your component with a system, add the path to Platform Designer to your PATH
environment variable.
For example:
export PATH=$PATH:<quartus_installdir>/qsys/bin
After completing these steps, the Intel® HLS Compiler is installed on your system. Before you can compile your component with the Intel® HLS Compiler i++ command, you must initialize your Intel® HLS Compiler environment for the i++ command to run successfully. For details, see Initializing the Intel HLS Compiler Environment.
Installing the Intel HLS Compiler on Microsoft* Windows* Systems
To install the Intel® HLS Compiler on Microsoft* Windows* Systems:
- Confirm that your operating system version is supported by the Intel® HLS Compiler (Microsoft* Windows* 7 SP1, 8.1 or 10).
-
Install one of the following software products, depending on
your edition of the
Intel®
Quartus® Prime software:
- Microsoft Visual Studio 2015 Professional
- Microsoft Visual Studio 2015 Community
- Microsoft Visual Studio 2010 Professional
Important: The Intel® HLS Compiler software does not support versions of Microsoft Visual Studio other than those specified for the edition of the software.If you have multiple versions of Visual Studio, Microsoft recommends installing Visual Studio versions in the order in which the versions were released. For example, install Visual Studio 2010 before installing Visual Studio 2015. For details, see Install Visual Studio Versions Side-by-Side in the MSDN Library. -
Depending on your current system and what installation package
or packages you have downloaded, you might have to complete some additional
steps to prepare your installation:
- Installing complete
Intel®
Quartus® Prime installation package (from the Combined Files tab):
No additional steps are needed before running the installation package.
-
Installing separately downloaded
Intel®
Quartus® Prime (from Individual Files tab) and
Intel® HLS Compiler (from Additional
Software tab) installation packages:
Ensure that you have both installation packages in the same directory. The Intel® Quartus® Prime installer detects the Intel® HLS Compiler installation package and installs both software packages for you.
-
Updating the
Intel® HLS Compiler in your
Intel®
Quartus® Prime Pro Edition installation:
- Ensure that you have Intel® Quartus® Prime Pro Edition already installed.
- Take note of the path to your
Intel®
Quartus® Prime installation.
You need this path information to complete the Intel® HLS Compiler installation wizard.
- Rename the HLS directory in your current
Intel®
Quartus® Prime version to keep that version
as a backup.
For example, if you are installing Intel® HLS Compiler Version 19.1 into an Intel® Quartus® Prime Pro Edition Version 18.1.1 installation, rename C:\intelFPGA_pro\18.1\hls to C:\intelFPGA_pro\18.1\hls_old.
- Installing complete
Intel®
Quartus® Prime installation package (from the Combined Files tab):
-
Install the package that you downloaded in Downloading the Intel HLS Compiler.
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, refer to the Intel® FPGA Software Installation and Licensing .
-
If you use the
Mentor Graphics*
ModelSim*
software provided with
Intel®
Quartus® Prime, add the path to
ModelSim*
to your PATH
environment variable.
For example:
set PATH=%PATH%:<quartus_installdir>\modelsim_ase\win32aloem
- Optional:
If you plan to use Platform Designer to
integrate your component with a system, add the path to Platform Designer to your PATH
environment variable.
For example:
set PATH=%PATH%:<quartus_installdir>\qsys\bin
After completing these steps, the Intel® HLS Compiler is installed on your system. Before you can compile your component with the Intel® HLS Compiler i++ command, you must initialize your Intel® HLS Compiler environment for the i++ command to run successfully. For details, see Initializing the Intel HLS Compiler Environment.
Initializing the Intel HLS Compiler Environment
The Intel® HLS Compiler environment initialization script applies only to the environment variable settings in your current terminal or command prompt session. You must initialize the Intel® HLS Compiler environment each time that you start a terminal or command prompt session to develop your design.
To initialize your current terminal or command prompt session so that you can run the Intel® HLS Compiler:
-
On Linux systems, initialize your environment as follows:
-
In your terminal session, change directories to the
hls directory in your
Intel®
Quartus® Prime installation directory.
For example, /home/<username>/intelFPGA_pro/19.1/hls
-
Run the following command from the hls directory to set the environment
variables for the i++ command in the
current terminal session:
source init_hls.sh
The command prints out the modified environment variable settings.
The environment initialization script shows the environment variables that it set, and you can now run the i++ command from this terminal session. -
In your terminal session, change directories to the
hls directory in your
Intel®
Quartus® Prime installation directory.
-
On Windows systems, initialize your environment as
follows:
-
Start a Visual Studio x64 native tools developer
command prompt session.
For example, C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\bin\amd64\vcvars64.bat.
-
In
your x64 Native Tools command prompt session, change
directories to the hls directory in
your
Intel®
Quartus® Prime installation
directory.
For example, C:\intelFPGA_pro\19.1\hls
-
Run the following command from the hls directory to set the environment
variables for the i++ command in the
current terminal session:
init_hls.bat
The command prints out the modified environment variable settings.
The environment initialization script shows the environment variables that it set, and you can now run the i++ command from this command prompt session. -
Start a Visual Studio x64 native tools developer
command prompt session.
High Level Synthesis (HLS) Design Examples and Tutorials
The Intel® High Level Synthesis (HLS) Compiler includes design examples and tutorials to provide you with example components and demonstrate ways to model or code your components to get the best results from the Intel® HLS Compiler for your design.
High Level Synthesis Design Examples
The high level synthesis (HLS) design examples give you a quick way to see how various algorithms can be effectively implemented to get the best results from the Intel® HLS Compiler.
<quartus_installdir>/hls/examples/<design_example_name>
Where <quartus_installdir> is the directory where you installed the Intel® Quartus® Prime Design Suite. For example, /home/<username>/intelFPGA_pro/19.1 or C:\intelFPGA_pro\19.1 .
| Focus area | Name | Description |
|---|---|---|
| Linear algebra | QRD | Uses the Modified Gram-Schmidt algorithm for QR factorization of a matrix. |
| Signal processing | interp_decim_filter | Implements a simple and efficient interpolation/decimation filter. |
| Simple design | counter | Implements a simple and efficient 32-bit counter component. |
| Video processing | YUV2RGB | Implements a basic YUV422 to RGB888 color space conversion. |
| Video processing | image_downsample | Implements an image downsampling algorithm to scale an image to a smaller size using bilinear interpolation. |
HLS Design Tutorials
The HLS design tutorials show you important HLS-specific programming concepts as well demonstrating good coding practices.
<quartus_installdir>/hls/examples/tutorials/<tutorial_name>
Where <quartus_installdir> is the directory where you installed the Intel® Quartus® Prime Design Suite. For example, /home/<username>/intelFPGA_pro/19.1 or C:\intelFPGA_pro\19.1 .
Each tutorial has a README file that gives you details about what the tutorial covers and instructions on how to run the tutorial.
| Name | Description |
|---|---|
| ac_fixed_constructor | Demonstrates the use of the ac_fixed constructor where you can get a better QoR by using minor variations in coding style. |
| ac_fixed_math_library | Demonstrates the use of the Intel® HLS Compiler ac_fixed_math fixed point math library functions. |
| ac_int_basic_ops | Demonstrates the operators available for the ac_int class. |
| ac_int_overflow | Demonstrates the usage of the DEBUG_AC_INT_WARNING and DEBUG_AC_INT_ERROR keywords to help detect overflow during emulation runtime. |
| Name | Description |
|---|---|
| bank_bits | Demonstrates how to control component internal memory architecture for parallel memory access by enforcing which address bits are used for banking. |
| depth_wise_merge | Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a depth equal to the sum of the depths of the two original memories. |
| mm_slave | |
| rom | |
| static_var_init | Demonstrates the hls_init_on_power and hls_init_on_reset flags for static variables and their impact on area and latency. |
| struct_member_attributes | Demonstrates how you can apply memory attributes to member variables of a struct and how attributes interact when you apply them simultaneously to struct member variables and to a struct instantiation. |
| width_wise_merge | Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a width equal to the sum of the widths of the two original memories. |
| Name | Description |
|---|---|
| overview | Demonstrates the effects on quality-of-results (QoR) of choosing different component interfaces even when the component algorithm remains the same. |
| explicit_streams_buffer |
Demonstrates how to use explicit stream_in and stream_out interfaces in the component and testbench. |
| explicit_streams_packets_empty | Demonstrates how to use the usesPackets, usesEmpty, and firstSymbolInHighOrderBits stream template parameters. |
| explicit_streams_packets_ready_valid | Demonstrates how to use the usesPackets, usesValid, and usesReady stream template parameters. |
| explicit_streams_ready_latency | Demonstrates how to achieve a better loop initiation interval (II) with stream write using the readyLatency stream template parameter. |
| mm_master_testbench_operators | Demonstrates how to invoke a component at different indicies of an Avalon Memory Mapped (MM) Master (mm_master class) interface. |
| mm_slaves | Demonstrates how to create Avalon-MM Slave interfaces (slave registers and slave memories). |
| multiple_stream_call_sites | Demonstrates the benefits of using multiple stream call sites. |
| pointer_mm_master | Demonstrates how to create Avalon-MM Master interfaces and control their parameters. |
| stable_arguments | Demonstrates how to use the stable attribute for unchanging arguments to improve resource utilization. |
| Name | Description |
|---|---|
| ac_datatypes | Demonstrates the effect of using ac_int datatype instead of int datatype. |
| const_global | Demonstrates the performance and resource utilization improvements of using const qualified global variables. |
| divergent_loops | Demonstrates a source-level optimization for designs with divergent loops |
| floating_point_ops | Demonstrates the impact of --fpc and --fp-relaxed flags in i++ on floating point operations. |
| hyper_optimized_handshaking | Demonstrates how to use the --hyper-optimized-handshaking option of the Intel HLS Compiler i++ command. |
| integer_promotion | Demonstrates how integer promotion rules can influence the behavior of a C or C++ program. |
| loop_coalesce | Demonstrates the performance and resource
utilization improvements of using loop_coalesce pragma on nested loops. While the #pragma loop_coalesce is provided with both Standard and Pro edition, the design tutorial is provided only with Pro edition. |
| loop_memory_dependency | Demonstrates breaking loop carried dependencies using the ivdep pragma. |
| parameter_aliasing |
Demonstrates the use of the __restrict keyword on component arguments. Demonstrates the use of the restrict keyword on component arguments. |
| random_number_generator | Demonstrates how to use the random number generator library. |
| resource_sharing_filter | Demonstrates the following versions of a
32-tap finite impulse response (FIR) filter design:
|
| set_component_target_fmax | Demonstrate how to use the hls_scheduler_target_fmax_mhz component attribute and how it interacts with the ii loop pragma.. |
| shift_register | Demonstrates the recommended coding style for implementing shift registers. |
| sincos_func | Demonstrates the effects of using sinpi or cospi functions in your component instead of sin or cos functions. |
| single_vs_double_precision_math | Demonstrates the effect of using single precision literals and functions instead of double precision literals and functions. |
| struct_interface | Demonstrates how to use ac_int to implement interfaces with no padding bits. |
| swap_vs_copy | Demonstrates the impact of using deep copying with registers on the performance and resource utilization of a component design. |
| Name | Description |
|---|---|
| compiler_interoperability | (Linux only) Demonstrates how to use testbench code compiled with GCC along with code compiled by the i++ command. |
| enqueue_call | Demonstrates how to run components asynchronously and exercise their pipeline performance in the test bench using enqueue functionality. |
|
platform_designer_2xclock qsys_2xclock |
Demonstrates the recommended clock and reset generation for a component with a clock2x input. |
|
platform_designer_stitching qsys_stitching |
Demonstrates how to combine multiple components to function as a single cohesive design. |
| Name | Description |
|---|---|
| parallel_loop | Demonstrates how you can run sequential loops in a pipelined manner by using a system of HLS tasks in your component. |
| resource_sharing | Demonstrates how you can share expensive compute blocks in your component to save area usage. |
| balancing_pipeline_latency | Demonstrates how to improve the throughput of a component that uses a system of tasks by buffering streams. |
| balancing_loop_delay | Demonstrates how to improve the throughput of a component that uses a system of tasks by buffering streams. |
| internal_stream | Demonstrates how to use "internal streams" in HLS tasks with the ihc::stream object. |
| task_reuse | Demonstrates how to invoke multiple copies of the same task function. |
| Name | Description |
|---|---|
| basic_rtl_library_flow |
Demonstrates the process of developing an RTL library and using it in an HLS component. |
| rtl_struct_mapping | Demonstrates how to obtain a mapping from C++ struct fields to bit-slices of RTL module interface signals. |
Running a High Level Synthesis (HLS) Design Example (Linux)
To run an HLS design example on Linux systems:
-
Start a terminal session and initialize the
Intel® HLS Compiler environment.
For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Environment.
-
Navigate to the
<quartus_installdir>/hls/examples/<design_example_name>
directory, where <quartus_installdir>
is the directory where you installed
Intel®
Quartus® Prime
software.
For example, /home/<username>/intelFPGA_pro/19.1 .
-
Run the make test-x86-64
command. This command compiles the C++ source code to an x86-64 binary
executable. Then, run the generated executable on your CPU.
Expected outcome after you run the make test-x86-64 command:
- The console displays the command used to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files> .
- The HLS compiler creates an executable file (for example, test-x86-64) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
$ make test-x86-64 i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp --fpc --fp-relaxed -march=x86-64 -o test-x86-64 +----------------------------------------+ | Run ./test-x86-64 to execute the test. | +----------------------------------------+
-
Run the make test-fpga
command. The command compiles the C++ source code to a hardware executable and
then runs a simulation of the generated HDL.
Expected outcome after you run the make test-fpga command:
- The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
- The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
$ make test-fpga i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -v --fpc --fp-relaxed -march=Arria10 -o test-fpga Target FPGA part name: 10AX115U1F45I1SG Target FPGA family name: Arria 10 Target FPGA speed grade: -2 Analyzing MGS.cpp for testbench generation Creating x86-64 testbench Analyzing MGS.cpp for hardware generation Analyzing QRD_Testbench.cpp for testbench generation Creating x86-64 testbench Analyzing QRD_Testbench.cpp for hardware generation Analyzing TestbenchHelpers.cpp for testbench generation Creating x86-64 testbench Analyzing TestbenchHelpers.cpp for hardware generation Optimizing component(s) and generating Verilog files Generating cosimulation support Generating simulation files for components: qrd HLS simulation directory: /data/username/HLS_Trainings/examples/QRD/test-fpga.prj/verification. Linking x86 objects +--------------------------------------+ | Run ./test-fpga to execute the test. | +--------------------------------------+
Running a High Level Synthesis (HLS) Design Example (Windows)
To run an HLS design example on Windows systems:
-
Start a terminal session and initialize the
Intel® HLS Compiler environment.
For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Environment.
-
Navigate to the
<quartus_installdir>\hls\examples\<design_example_name>
directory, where <quartus_installdir>
is the directory where you installed
Intel®
Quartus® Prime
software.
For example, C:\intelFPGA_pro\19.1 .
-
Run the build.bat
test-x86-64. This command compiles the C++ source code to an
x86-64 binary executable. Then, run the generated executable on your CPU.
Expected outcome after you run the build.bat test-x86-64 command:
- The console displays the command it uses to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files> .
- The HLS compiler creates an executable file (for example, test-x86-64.exe) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
C:\intelFPGA_pro\19.1\hls\examples\QRD>build.bat test-x86-64 i++ --fpc --fp-relaxed -march=x86-64 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-x86-64.exe Run test-x86-64.exe to execute the test. -
Run the build.bat
test-fpga command. The command compiles the C++ source code to a
hardware executable and then runs a simulation of the generated HDL.
Expected outcome after you run the build.bat test-fpga command:
- The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
- The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
C:\intelFPGA_pro\19.1\hls\examples\QRD>build.bat test-fpga i++ --fpc --fp-relaxed -march=Arria10 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-fpga.exe Run test-fpga.exe to execute the test.
Troubleshooting the Setup of the Intel HLS Compiler
Intel HLS Compiler Licensing Issues
In some cases, you might encounter problems with the licensing for ModelSim* software.
ModelSim Licensing Error Messages
If the HLS compiler fails to locate the ModelSim software license, it issues the following error message when you compile your design to the FPGA architecture:
$ i++ -march="<FPGA_family_or_part_number>" program.cpp HLS Elaborate cosim testbench. FAILED. See ./a.prj/a.log for details. Error: Missing simulator license. Either: 1) Ensure you have a valid ModelSim license 2) Use the --simulator none flag to skip the verification flow
Common causes for these errors include:
- Missing, expired, or invalid licenses
- Incorrect license server name in the license.dat file
- Unspecified or incorrectly-specified license location
LM_LICENSE_FILE Environment Variable
On Linux or UNIX systems, insert a colon (:) after each license file or license server location that you append to the LM_LICENSE_FILE environment variable.
On Windows systems, insert a semicolon (;) after each license file or license server location that you append to the LM_LICENSE FILE environment variable.
ModelSim Software License-Specific Considerations
For Mentor Graphics® applications, including the ModelSim software, you can specify the paths to license files and license servers in five different locations. If you specify paths to license files or license servers in multiple locations, the following search order is used to find the first valid path:
- MGLS_LICENSE_FILE environment variable you set in the user environment
- MGLS_LICENSE_FILE environment variable you set in the registry
- LM_LICENSE_FILE environment variable you set in the environment
- LM_LICENSE_FILE environment variable you set in the registry
- <path to FLEXlm>\license.dat, where <path to FLEXlm> is the default location of the FLEXlm license file.
When you install a Mentor Graphics product license on a computer, the MGLS_LICENSE_FILE environment variable settings take precedence over the LM_LICENSE_FILE environment variable settings. If you set both environment variables, set LM_LICENSE_FILE to point to the ModelSim license server and set MGLS_LICENSE_FILE to only point to the license server for other Mentor Graphics applications. If you only use the MGLS_LICENSE_FILE environment variable, ensure that the ModelSim license server and the license servers for other Mentor Graphics applications are on the same machine.
Document Revision History for Intel HLS Compiler Getting Started Guide
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2019.04.01 | 19.1 |
|
| 2018.12.24 | 18.1 |
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| 2018.09.24 | 18.1 |
|
| 2018.05.07 | 18.0 |
|
| 2017.12.22 | 17.1.1 |
|
| 2017.12.08 | 17.0 |
|
| 2017.11.06 | 17.0 |
|
| 2017.06.23 | — |
|
| 2017.06.09 | — |
|
| 2017.03.14 | — |
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| 2017.03.01 | — |
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| 2017.02.03 | — |
|
| 2016.11.30 | — |
|
| 2016.09.12 | — |
|