Intel High Level Synthesis Compiler Pro Edition: Getting Started Guide
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 20.3 |
1. Intel High Level Synthesis (HLS) Compiler Pro Edition Getting Started Guide
The Intel® High Level Synthesis Compiler Pro Edition Getting Started Guide describes the procedures to set up the Intel® HLS Compiler and to run an HLS design example.
In this publication, <quartus_installdir> refers to the location where you installed Intel® Quartus® Prime Design Suite.
- Windows
- C:\intelFPGA_pro\20.3
- Linux
- /home/<username>/intelFPGA_pro/20.3
About the Intel® HLS Compiler Pro Edition Documentation Library
| Title and Description | |
|---|---|
|
Release
Notes
Provide late-breaking information about the Intel® HLS Compiler. |
Link |
|
Getting Started
Guide
Get up and running with the Intel® HLS Compiler by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the Intel® HLS Compiler. |
Link |
|
User Guide
Provides instructions on synthesizing, verifying, and simulating intellectual property (IP) that you design for Intel FPGA products. Go through the entire development flow of your component from creating your component and testbench up to integrating your component IP into a larger system with the Intel Quartus Prime software. |
Link |
|
Reference
Manual
Provides reference information about the features supported by the Intel HLS Compiler. Find details on Intel® HLS Compiler command options, header files, pragmas, attributes, macros, declarations, arguments, and template libraries. |
Link |
|
Best Practices
Guide
Provides techniques and practices that you can apply to improve the FPGA area utilization and performance of your HLS component. Typically, you apply these best practices after you verify the functional correctness of your component. |
Link |
|
Quick
Reference
Provides a brief summary of Intel HLS Compiler declarations and attributes on a single two-sided page. |
Link |
1.1. Intel High Level Synthesis Compiler Pro Edition Prerequisites
For detailed instructions about installing Intel® Quartus® Prime Pro Edition software, including system requirements, prerequisites, and licensing requirements, see Intel® FPGA Software Installation and Licensing .
The Intel® HLS Compiler requires the following software in addition to Intel® Quartus® Prime:
C++ Compiler
On Linux, Intel® HLS Compiler requires GCC 9.1.0 including the GNU C++ library and binary utilities (binutils).
This version of GCC is provided as part of your Intel® HLS Compiler installation. After installing the Intel® HLS Compiler, GCC 9.1.0 is available in <quartus_installdir>/gcc.
- Microsoft* Visual Studio* 2017 Professional
- Microsoft* Visual Studio* 2017 Community
Mentor Graphics* ModelSim* Software
- ModelSim* - Intel® FPGA Edition
- ModelSim* - Intel® FPGA Starter Edition
On Red Hat* Linux systems, ModelSim* software requires the Red Hat* development tools packages. Additionally, any 32-bit versions of ModelSim* software (including those provided with Intel® Quartus® Prime) require additional 32-bit libraries. The commands to install these requirements are provided in Installing the Intel® HLS Compiler on Linux Systems.
On SUSE* Linux systems, you must use your own licensed version of Mentor Graphics* ModelSim* software.
For information about all the ModelSim* software versions that the Intel® software supports, refer to the EDA Interface Information section in the Software and Device Support Release Notes for your edition of Intel® Quartus® Prime Pro Edition
1.1.1. Intel HLS Compiler Pro Edition Backwards Compatibility
The Intel® HLS Compiler Pro Edition Version 20.3 is compatible with Intel® Quartus® Prime Pro Edition Version 20.3, Version 20.2, Version 20.1, and Version 17.1.1. This backwards compatibility lets you to take advantage of improvements in the RTL generated by the Intel® HLS Compiler without changing the other parts of your current FPGA development environment.
- Backup the existing <quartus_installdir> 1/hls directory. For example, rename <quartus_installdir>/hls to <quartus_installdir>/hls_old.
- Download the Intel® HLS Compiler Pro Edition standalone installation package from the Individual Files tab of the Intel® Quartus® Prime Download Center for your edition of Intel® Quartus® Prime.
- Run the Intel® HLS Compiler standalone installer, and specify your <quartus_installdir> directory when prompted.
You can revert to your previous version of the Intel® HLS Compiler by renaming your backup directory. Whatever version of the the Intel® HLS Compiler that in a directory called <quartus_installdir>/hls is the active version of the Intel® HLS Compiler.
1.2. Downloading the Intel HLS Compiler Pro Edition
The Intel® HLS Compiler Pro Edition is installed as part of your Intel® Quartus® Prime Pro Edition installation package or from a separate standalone installer.
Download the Intel® HLS Compiler Pro Edition standalone installer when you want to add the Intel® HLS Compiler to an existing Intel® Quartus® Prime Pro Edition installation. The Intel® HLS Compiler Pro Edition Version 20.3 is compatible with Intel® Quartus® Prime Pro Edition Version 20.3, Version 20.2, Version 20.1, and Version 17.1.1.
- Download a complete installation package from the Combined Files tab.
- Download a Quartus Prime installation package from the Individual Files tab and download the Intel® HLS Compiler installation package from the Additional Software tab. Place both installation packages in the same directory.
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, refer to Intel® FPGA Software Installation and Licensing .
The Intel® HLS Compiler standalone installation package requires you to have an existing Intel® Quartus® Prime Pro Edition installation as a target for the Intel® HLS Compiler installation.
1.3. Installing the Intel HLS Compiler Pro Edition on Linux Systems
You must have administrator privileges to install the Intel® HLS Compiler Pro Edition prerequisites. However, the Intel® HLS Compiler and Intel® Quartus® Prime do not require administrator privileges to install.
To install the Intel® HLS Compiler on Linux Systems:
-
Confirm that your operating system version is supported by the
Intel® HLS Compiler:
- CentOS* 7
- Red Hat* Enterprise Linux* 7
- SUSE* Linux Enterprise Server 12
-
Depending on your current system and what installation package
or packages you have downloaded, you might have to complete some additional
steps to prepare your installation:
- If you are installing the complete
Intel®
Quartus® Prime installation package (from the
Combined Files tab of the
Quartus Prime download page at the Download Center for FPGAs):
No additional steps are needed before running the installation package.
- If you are installing separately downloaded
Intel®
Quartus® Prime (from
Individual Files tab of the Quartus Prime download page at
the Download Center for FPGAs) and
Intel® HLS Compiler (from Additional
Software tab of the Quartus Prime download page at the
Download Center for FPGAs) installation packages:
Ensure that you have both installation packages in the same directory. The Intel® Quartus® Prime installer detects the Intel® HLS Compiler installation package and installs both software packages for you.
- If you are updating the
Intel® HLS Compiler in an existing
Intel®
Quartus® Prime Pro Edition installation:
- Ensure that you have Intel® Quartus® Prime Pro Edition already installed.
- Take note of the path to your
Intel®
Quartus® Prime installation.
You need this path information to complete the Intel® HLS Compiler installation wizard.
- Rename the HLS directory in your current
Intel®
Quartus® Prime version to keep that version
as a backup.
For example, if you are installing Intel® HLS Compiler Version 20.3 into an Intel® Quartus® Prime Pro Edition Version 20.2 installation, rename /home/<username>/intelFPGA_pro/20.2/hls to /home/<username>/intelFPGA_pro/20.2/hls_old.
- If you are installing the complete
Intel®
Quartus® Prime installation package (from the
Combined Files tab of the
Quartus Prime download page at the Download Center for FPGAs):
-
Install the package that you downloaded in Downloading the Intel HLS Compiler Pro Edition.
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, refer to Intel® FPGA Software Installation and Licensing .
-
Update your Linux repositories with the
following command:
sudo yum update
-
(CentOS* and Red Hat* Linux Only) If you want the
Intel® HLS Compiler to simulate your components with
the 32-bit
Mentor Graphics*
ModelSim*
software provided with
Intel®
Quartus® Prime (
ModelSim* - Intel® FPGA Edition), install the required additional 32-bit
libraries with the following command:
-
CentOS* 7 and Red Hat*
Enterprise Linux*
7
$ sudo yum install -y glibc.i686 glibc-devel.i686 libX11.i686 \ libXext.i686 libXft.i686 libgcc.i686 libgcc.x86_64 \ libstdc++.i686 libstdc++-devel.i686 ncurses-devel.i686 \ qt.i686 -
SUSE* Linux
Enterprise Server 12
ModelSim - Intel FPGA Edition is not supported on SUSE* Linux. Use your own licensed version of Mentor Graphics* ModelSim* software.
-
CentOS* 7 and Red Hat*
Enterprise Linux*
7
-
(CentOS* and Red Hat* Linux Only) If you use the
Mentor Graphics*
ModelSim*
software provided with
Intel®
Quartus® Prime, add the path to
ModelSim*
to your PATH
environment variable
For example:
$ export PATH=$PATH:<quartus_installdir>/modelsim_ase/bin
- Optional:
If you plan to use Platform Designer to
integrate your component with a system, add the path to Platform Designer to your PATH
environment variable.
For example:
$ export PATH=$PATH:<quartus_installdir>/qsys/bin
After completing these steps, the Intel® HLS Compiler is installed on your system. Before you can compile your component with the Intel® HLS Compiler i++ command, you must initialize your Intel® HLS Compiler environment for the i++ command to run successfully. For details, see Initializing the Intel HLS Compiler Pro Edition Environment.
1.4. Installing the Intel HLS Compiler Pro Edition on Microsoft Windows Systems
To install the Intel® HLS Compiler on Microsoft* Windows* Systems:
-
Confirm that your operating system version is supported by the
Intel® HLS Compiler:
- Microsoft* Windows* 10
- Microsoft* Windows Server* 2016
-
Install one of the following software products:
- Microsoft* Visual Studio* 2017 Professional
- Microsoft* Visual Studio* 2017 Community
Important: The Intel® HLS Compiler software does not support versions of Microsoft* Visual Studio* other than those specified for the edition of the software.If you have multiple versions of Visual Studio*, Microsoft recommends installing Visual Studio* versions in the order in which the versions were released. For example, install Visual Studio* 2010 before installing Visual Studio* 2015. For details, see Install Visual Studio* Versions Side-by-Side in the MSDN Library. -
Depending on your current system and what installation package
or packages you have downloaded, you might have to complete some additional
steps to prepare your installation:
- If you are installing complete
Intel®
Quartus® Prime installation package (from the Combined
Files tab of the Quartus Prime download page at the Download
Center for FPGAs):
No additional steps are needed before running the installation package.
- Installing separately downloaded
Intel®
Quartus® Prime (from Individual
Files tab of the Quartus Prime download page at the Download
Center for FPGA) and
Intel® HLS Compiler
(from the Additional Software tab of
the Quartus Prime download page at the Download Center for FPGA)
installation packages:
Ensure that you have both installation packages in the same directory. The Intel® Quartus® Prime installer detects the Intel® HLS Compiler installation package and installs both software packages for you.
- Updating the
Intel® HLS Compiler in
your
Intel®
Quartus® Prime Pro Edition installation:
- Ensure that you have Intel® Quartus® Prime Pro Edition already installed.
- Take note of the path to your
Intel®
Quartus® Prime installation.
You need this path information to complete the Intel® HLS Compiler installation wizard.
- Rename the HLS directory in your current
Intel®
Quartus® Prime version to keep that version
as a backup.
For example, if you are installing Intel® HLS Compiler Version 20.3 into an Intel® Quartus® Prime Pro Edition Version 20.2 installation, rename C:\intelFPGA_pro\20.2\hls to C:\intelFPGA_pro\20.2\hls_old.
- If you are installing complete
Intel®
Quartus® Prime installation package (from the Combined
Files tab of the Quartus Prime download page at the Download
Center for FPGAs):
-
Install the package that you downloaded in Downloading the Intel HLS Compiler Pro Edition.
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, refer to the Intel® FPGA Software Installation and Licensing .
-
If you use the
Mentor Graphics*
ModelSim*
software provided with
Intel®
Quartus® Prime, add the path to
ModelSim*
to your PATH
environment variable.
For example:
set "PATH=%PATH%:<quartus_installdir>\modelsim_ase\win32aloem"
- Optional:
If you plan to use Platform Designer to
integrate your component with a system, add the path to Platform Designer to your PATH
environment variable.
For example:
set "PATH=%PATH%:<quartus_installdir>\qsys\bin"
After completing these steps, the Intel® HLS Compiler is installed on your system. Before you can compile your component with the Intel® HLS Compiler i++ command, you must initialize your Intel® HLS Compiler environment for the i++ command to run successfully. For details, see Initializing the Intel HLS Compiler Pro Edition Environment.
1.5. Initializing the Intel HLS Compiler Pro Edition Environment
The Intel® HLS Compiler environment initialization script applies only to the environment variable settings in your current terminal or command prompt session. You must initialize the Intel® HLS Compiler environment each time that you start a terminal or command prompt session to develop your design.
To initialize your current terminal or command prompt session so that you can run the Intel® HLS Compiler:
-
On Linux systems, initialize your
environment as follows:
-
Start a terminal session and run
the following command from the command prompt:
<quartus_installdir>/hls/init_hls.sh
Where <quartus_installdir> is the path to your Intel® Quartus® Prime installation. For example, /home/<username>/intelFPGA_pro/20.3.
This script creates a subshell that does not change the environment in your initial working shell.
If you want modify your current working shell, use the source command to invoke the script:source <quartus_installdir>/hls/init_hls.sh
The environment initialization script shows the environment variables that it set, and you can now run the i++ command from this terminal session. -
Start a terminal session and run
the following command from the command prompt:
-
On Windows systems, initialize your
environment as follows:
-
Start a Windows Command Prompt
session and run the following command from the
command prompt:
<quartus_installdir>\hls\init_hls.bat
Where <quartus_installdir> is the path to your Intel® Quartus® Prime installation. For example, C:\intelFPGA_pro\20.3 .
You can now run the i++ command from this command prompt session. -
Start a Windows Command Prompt
session and run the following command from the
command prompt:
2. High Level Synthesis (HLS) Design Examples and Tutorials
The Intel® High Level Synthesis (HLS) Compiler Pro Edition includes design examples and tutorials to provide you with example components and demonstrate ways to model or code your components to get the best results from the Intel® HLS Compiler for your design.
High Level Synthesis Design Examples
The high level synthesis (HLS) design examples give you a quick way to see how various algorithms can be effectively implemented to get the best results from the Intel® HLS Compiler.
<quartus_installdir>/hls/examples/<design_example_name>
Where <quartus_installdir> is the directory where you installed the Intel® Quartus® Prime Design Suite. For example, /home/<username>/intelFPGA_pro/20.3 or C:\intelFPGA_pro\20.3 .
| Focus area | Name | Description |
|---|---|---|
| Linear algebra | QRD | Uses the Modified Gram-Schmidt algorithm for QR factorization of a matrix. |
| Signal processing | interp_decim_filter | Implements a simple and efficient interpolation/decimation filter. |
| Simple design | counter | Implements a simple and efficient 32-bit counter component. |
| Video processing | YUV2RGB | Implements a basic YUV422 to RGB888 color space conversion. |
| Video processing | image_downsample | Implements an image downsampling algorithm to scale an image to a smaller size using bilinear interpolation. |
HLS Design Tutorials
The HLS design tutorials show you important HLS-specific programming concepts as well demonstrating good coding practices.
Each tutorial has a README file that gives you details about what the tutorial covers and instructions on how to run the tutorial.
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/ac_datatypes |
|
| ac_fixed_constructor | Demonstrates the use of the ac_fixed constructor where you can get a better QoR by using minor variations in coding style. |
| ac_fixed_math_library | Demonstrates the use of the Intel® HLS Compiler ac_fixed_math fixed point math library functions. |
| ac_int_basic_ops | Demonstrates the operators available for the ac_int class. |
| ac_int_overflow | Demonstrates the usage of the DEBUG_AC_INT_WARNING and DEBUG_AC_INT_ERROR keywords to help detect overflow during emulation runtime. |
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/hls_float |
|
| 1_reduced_double | Demonstrates how your application can benefit from hls_float by changing the underlining type from double to hls_float<11, 44> (reduced double). |
| 2_explicit_arithmetic | Demonstrates how to use the explicit versions of hls_float binary operators to perform floating-point arithmetic operations based on your needs. |
| 3_conversions | Demonstrates when conversions appear in designs with hls_float types and how to use different conversion modes to generate compile-type constants using various hls_float types. |
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/component_memories |
|
| attributes_on_mm_slave_arg | Demonstrates how to apply memory attributes to Avalon® Memory Mapped (MM) slave arguments. |
| exceptions | Demonstrates how to use memory attributes on constants and struct members. |
| memory_bank_configuration | Demonstrates how to control the number of
load/store ports of each memory bank and optimize your component
area usage, throughput, or both by using one or more of the
following memory attributes:
|
| memory_geometry | Demonstrates how to split your memory into
banks and control the number of load/store ports of each memory
bank by using one or more of the following memory attributes:
|
| memory_implementation | Demonstrates how to implement variables or
arrays in registers, MLABs, or RAMs by using the following
memory attributes:
|
| memory_merging | Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory by merging them depth-wise or width-wise with the hls_merge memory attribute. |
| non_power_of_two_memory | Demonstrates how to use the force_pow2_depth memory attribute to control the padding of memories that are non-power-of-two deep, and how that impacts the FPGA memory resource usage. |
| non_trivial_initialization | Demonstrates how to use the C++ keyword constexpr to achieve efficient initialization of read-only variables. |
| static_var_init | Demonstrates how to control the initialization behavior of statics in a component using the hls_init_on_reset or hls_init_on_powerup memory attribute. |
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/interfaces |
|
| overview | Demonstrates the effects on quality-of-results (QoR) of choosing different component interfaces even when the component algorithm remains the same. |
| explicit_streams_buffer |
Demonstrates how to use explicit stream_in and stream_out interfaces in the component and testbench. |
| explicit_streams_packets_ empty | Demonstrates how to use the usesPackets, usesEmpty, and firstSymbolInHighOrderBits stream template parameters. |
| explicit_streams_packets_ ready_valid | Demonstrates how to use the usesPackets, usesValid, and usesReady stream template parameters. |
| mm_master_testbench_operators | Demonstrates how to invoke a component at different indicies of an Avalon Memory Mapped (MM) Master (mm_master class) interface. |
| mm_slaves | Demonstrates how to create Avalon-MM Slave interfaces (slave registers and slave memories). |
| mm_slaves_double_buffering | Demonstrates the effect of using the hls_readwrite_mode macro to control how memory masters access the slave memories |
| mm_slaves_csr_volatile | Demonstrates the effect of using volatile keyword to allow concurrent slave memory accesses while your component is running. |
| multiple_stream_call_sites | Demonstrates the benefits of using multiple stream call sites. |
| pointer_mm_master | Demonstrates how to create Avalon-MM Master interfaces and control their parameters. |
| stable_arguments | Demonstrates how to use the stable attribute for unchanging arguments to improve resource utilization. |
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/best_practices |
|
| ac_datatypes | Demonstrates the effect of using ac_int datatype instead of int datatype. |
| const_global | Demonstrates the performance and resource utilization improvements of using const qualified global variables. |
| divergent_loops | Demonstrates a source-level optimization for designs with divergent loops |
| floating_point_contract | Demonstrates how to use the fp_contract option to improve the performance of your design for double-precision floating-point operations. |
| floating_point_ops | Demonstrates the impact of --fpc and --fp-relaxed flags in i++ on floating point operations using a 32-tap finite impulse response (FIR) filter design that is optimized for throughput. |
| fpga_reg | Demonstrates how to use the fpga_reg macro to precisely tune pipelining in your design. |
| hyper_optimized_handshaking | Demonstrates how to use the --hyper-optimized-handshaking option of the Intel HLS Compiler i++ command. |
| loop_coalesce | Demonstrates the performance and resource
utilization improvements of using loop_coalesce pragma on nested loops. While the #pragma loop_coalesce is provided with both Standard and Pro edition, the design tutorial is provided only with Pro edition. |
| loop_fusion | Demonstrates the latency and resource utilization improvements of loop fusion. |
| loop_memory_dependency | Demonstrates breaking loop carried dependencies using the ivdep pragma. |
| lsu_control | Demonstrates the effects of controlling the types of LSUs instantiated for variable-latency Avalon® MM Master interfaces. |
| parallelize_array_operation | Demonstrates how to improve fMAX by correcting a bottleneck that arises when performing operations on an array in a loop. |
| optimize_ii_using_hls_register | Demonstrates how to use the hls_register attribute to reduce loop II and how to use hls_max_concurrency to improve component throughput |
| parameter_aliasing |
Demonstrates the use of the __restrict keyword on component arguments. |
| random_number_generator | Demonstrates how to use the random number generator library. |
| reduce_exit_fifo_width | Demonstrates how to improve fMAX by reducing the width of the FIFO belonging to the exit node of a stall-free cluster |
| relax_reduction_dependency |
Demonstrates a method to reduce the II of a loop that includes a floating point accumulator, or other reduction operation that cannot be computed at high speed in a single clock cycle. |
| remove_loop_carried_dependency | Demonstrates how you can improve loop performance by removing accesses to the same variable across nested loops. |
| resource_sharing_filter | Demonstrates an optimized-for-area variant of a 32-tap finite impulse response (FIR) filter design |
| set_component_target_fmax_1 | Demonstrates how to the target fMAX in various ways by leveraging the Loop Analysis report in the High-Level Design Reports. |
| set_component_target_fmax_2 | Demonstrates how the compiler handles the tradeoff between fMAX and II based on the presence or absence of the hls_scheduler_target_fmax_mhz component attribute and the ii loop pragma. |
| shift_register | Demonstrates the recommended coding style for implementing shift registers. |
| sincos_func | Demonstrates the effects of using sinpi or cospi functions in your component instead of sin or cos functions. |
| single_vs_double_ precision_math | Demonstrates the effect of using single precision literals and functions instead of double precision literals and functions. |
| stall_enable | Demonstrates how to replace stall-free clusters with stall-enabled clusters to improve latency in some small designs. |
| struct_interface | Demonstrates how to use ac_int to implement interfaces with no padding bits. |
| submnormal_and_rounding | Demonstrates the effects of use the --daz and --rounding i++ command options. |
| swap_vs_copy | Demonstrates the impact of using deep copying with registers on the performance and resource utilization of a component design. |
| triangular_loop | Demonstrates a method for describing triangular loop patterns with dependencies. |
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/usability |
|
| compiler_interoperability | (Linux only) Demonstrates how to use testbench code compiled with GCC along with code compiled by the i++ command. |
| enqueue_call | Demonstrates how to run components asynchronously and exercise their pipeline performance in the test bench using enqueue functionality. |
|
platform_designer_2xclock |
Demonstrates the recommended clock and reset generation for a component with a clock2x input. |
|
platform_designer_stitching |
Demonstrates how to combine multiple components to function as a single cohesive design. |
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/system_of_tasks |
|
| balancing_loop_delay | Demonstrates how to improve the throughput of a component that uses a system of tasks by buffering streams. |
| balancing_pipeline_latency | Demonstrates how to improve the throughput of a component that uses a system of tasks by buffering streams. |
| interfaces_sot | Demonstrates how to transfer information between, into, and out of tasks using Avalon® streaming and Avalon® memory-mapped master interfaces. |
| internal_stream | Demonstrates how to use "internal streams" in HLS tasks with the ihc::stream object. |
| parallel_loop | Demonstrates how you can run sequential loops in a pipelined manner by using a system of HLS tasks in your component. |
| resource_sharing | Demonstrates how you can share expensive compute blocks in your component to save area usage. |
| task_reuse | Demonstrates how to invoke multiple copies of the same task function. |
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/libraries |
|
| basic_rtl_library_flow |
Demonstrates the process of developing an RTL library and using it in an HLS component. |
| rtl_struct_mapping | Demonstrates how to obtain a mapping from C++ struct fields to bit-slices of RTL module interface signals. |
| Name | Description |
|---|---|
You can find these
tutorials in the following location on your
Intel®
Quartus® Prime
system:<quartus_installdir>/hls/examples/tutorials/loop_controls |
|
| max_interleaving |
Demonstrates a method to reduce the area
utilization of a loop that meets the following conditions:
|
| small_speculated_iterations | Demonstrates how decreasing the number of speculated iterations improves latency when a loop body has low latency and is expected to be frequently invoked. |
| speculated_iterations | Demonstrates how increasing the number of speculated iterations improves II when the exit condition calculation is the bottleneck preventing a lower II. |
2.1. Running an Intel HLS Compiler Design Example (Linux)
To run an Intel® HLS Compiler design example on Linux systems:
-
Start a terminal session and initialize
the
Intel® HLS Compiler
environment.
For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Pro Edition Environment.
-
Navigate to the
<quartus_installdir>/hls/examples/<design_example_name>
directory, where <quartus_installdir> is the directory
where you installed
Intel®
Quartus® Prime
software.
For example, /home/<username>/intelFPGA_pro/20.3 .
-
Run the make
test-x86-64 command. This command compiles
the C++ source code to an x86-64 binary executable. Then,
run the generated executable on your CPU.
Expected outcome after you run the make test-x86-64 command:
- The console displays the command used to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files> .
- The HLS compiler creates an executable file (for example, test-x86-64) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
$ make test-x86-64 i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -ffp-contract=fast -ffp-reassoc -march=x86-64 -o test-x86-64 +----------------------------------------+ | Run ./test-x86-64 to execute the test. | +----------------------------------------+
-
Run the make
test-fpga command. The command compiles the
C++ source code to a hardware executable and then runs a
simulation of the generated HDL.
Expected outcome after you run the make test-fpga command:
- The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
- The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
$ make test-fpga i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -v -ffp-contract=fast -ffp-reassoc -march=Arria10 -o test-fpga Target FPGA part name: 10AX115U1F45I1SG Target FPGA family name: Arria 10 Target FPGA speed grade: -2 Analyzing MGS.cpp for testbench generation Creating x86-64 testbench Analyzing MGS.cpp for hardware generation Analyzing QRD_Testbench.cpp for testbench generation Creating x86-64 testbench Analyzing QRD_Testbench.cpp for hardware generation Analyzing TestbenchHelpers.cpp for testbench generation Creating x86-64 testbench Analyzing TestbenchHelpers.cpp for hardware generation Optimizing component(s) and generating Verilog files Generating cosimulation support Generating simulation files for components: qrd HLS simulation directory: /data/username/HLS_Trainings/examples/QRD/test-fpga.prj/verification. Linking x86 objects +--------------------------------------+ | Run ./test-fpga to execute the test. | +--------------------------------------+
2.2. Running an Intel HLS Compiler Design Example (Windows)
To run an Intel® HLS Compiler design example on Windows systems:
-
Start a terminal session and initialize the
Intel® HLS Compiler environment.
For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Pro Edition Environment.
-
Navigate to the
<quartus_installdir>\hls\examples\<design_example_name>
directory, where <quartus_installdir>
is the directory where you installed
Intel®
Quartus® Prime
software.
For example, C:\intelFPGA_pro\20.3 .
-
Run the build.bat
test-x86-64. This command compiles the C++ source code to an
x86-64 binary executable. Then, run the generated executable on your CPU.
Expected outcome after you run the build.bat test-x86-64 command:
- The console displays the command it uses to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files> .
- The HLS compiler creates an executable file (for example, test-x86-64.exe) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
C:\intelFPGA_pro\20.3\hls\examples\QRD>build.bat test-x86-64 i++ -ffp-contract=fast -ffp-reassoc -march=x86-64 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-x86-64.exe Run test-x86-64.exe to execute the test. -
Run the build.bat
test-fpga command. The command compiles the C++ source code to a
hardware executable and then runs a simulation of the generated HDL.
Expected outcome after you run the build.bat test-fpga command:
- The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
- The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
- The console displays the output of the executable to signify a successful execution.
C:\intelFPGA_pro\20.3\hls\examples\QRD>build.bat test-fpga i++ -ffp-contract=fast -ffp-reassoc -march=Arria10 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-fpga.exe Run test-fpga.exe to execute the test.
3. Troubleshooting the Setup of the Intel HLS Compiler
3.1. Intel HLS Compiler Licensing Issues
In some cases, you might encounter problems with the licensing for ModelSim* software.
3.1.1. ModelSim Licensing Error Messages
If the HLS compiler fails to locate the ModelSim software license, it issues the following error message when you compile your design to the FPGA architecture:
$ i++ -march="<FPGA_family_or_part_number>" program.cpp HLS Elaborate cosim testbench. FAILED. See ./a.prj/a.log for details. Error: Missing simulator license. Either: 1) Ensure you have a valid ModelSim license 2) Use the --simulator none flag to skip the verification flow
Common causes for these errors include:
- Missing, expired, or invalid licenses
- Incorrect license server name in the license.dat file
- Unspecified or incorrectly-specified license location
3.1.2. LM_LICENSE_FILE Environment Variable
On Linux or UNIX systems, insert a colon (:) after each license file or license server location that you append to the LM_LICENSE_FILE environment variable.
On Windows systems, insert a semicolon (;) after each license file or license server location that you append to the LM_LICENSE FILE environment variable.
3.1.2.1. ModelSim Software License-Specific Considerations
For Mentor Graphics® applications, including the ModelSim software, you can specify the paths to license files and license servers in five different locations. If you specify paths to license files or license servers in multiple locations, the following search order is used to find the first valid path:
- MGLS_LICENSE_FILE environment variable you set in the user environment
- MGLS_LICENSE_FILE environment variable you set in the registry
- LM_LICENSE_FILE environment variable you set in the environment
- LM_LICENSE_FILE environment variable you set in the registry
- <path to FLEXlm>\license.dat, where <path to FLEXlm> is the default location of the FLEXlm license file.
When you install a Mentor Graphics product license on a computer, the MGLS_LICENSE_FILE environment variable settings take precedence over the LM_LICENSE_FILE environment variable settings. If you set both environment variables, set LM_LICENSE_FILE to point to the ModelSim license server and set MGLS_LICENSE_FILE to only point to the license server for other Mentor Graphics applications. If you only use the MGLS_LICENSE_FILE environment variable, ensure that the ModelSim license server and the license servers for other Mentor Graphics applications are on the same machine.
A. Intel HLS Compiler Pro Edition Getting Started Guide Archives
B. Document Revision History for Intel HLS Compiler Pro Edition Getting Started Guide
| Document Version | Intel® Quartus® Prime Pro Edition Version | Changes |
|---|---|---|
| 2020.09.28 | 20.3 |
|
| 2020.06.22 | 20.2 |
|
| 2020.04.13 | 20.1 |
|
| 2019.12.16 | 19.4 |
|
Document Revision History for Intel® HLS Compiler Getting Started Guide
Previous versions of the Intel® HLS Compiler Getting Started Guide contained information for both Intel® HLS Compiler Standard Edition and Intel® HLS Compiler Pro Edition.
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2019.09.30 | 19.3 |
|
| 2019.07.01 | 19.2 |
|
| 2019.04.01 | 19.1 |
|
| 2018.12.24 | 18.1 |
|
| 2018.09.24 | 18.1 |
|
| 2018.05.07 | 18.0 |
|
| 2017.12.22 | 17.1.1 |
|
| 2017.12.08 | 17.0 |
|
| 2017.11.06 | 17.0 |
|
| 2017.06.23 | — |
|
| 2017.06.09 | — |
|
| 2017.03.14 | — |
|
| 2017.03.01 | — |
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| 2017.02.03 | — |
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| 2016.11.30 | — |
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| 2016.09.12 | — |
|