Intel High Level Synthesis Compiler Pro Edition: User Guide
Version Information
Updated for: |
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Intel® Quartus® Prime Design Suite 20.4 |
1. Intel High Level Synthesis Compiler Pro Edition User Guide
Compared to traditional RTL development, the Intel® HLS Compiler offers the following advantages:
- Fast and easy verification
- Algorithmic development in C++
- Automatic integration of RTL verification with a C++ testbench
- Powerful microarchitecture optimizations
In this publication, <quartus_installdir> refers to the location where you installed Intel® Quartus® Prime Design Suite.
- Windows
- C:\intelFPGA_pro\20.4
- Linux
- /home/<username>/intelFPGA_pro/20.4
About the Intel® HLS Compiler Pro Edition Documentation Library
Title and Description | |
---|---|
Release
Notes
Provide late-breaking information about the Intel® HLS Compiler. |
Link |
Getting Started
Guide
Get up and running with the Intel® HLS Compiler by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the Intel® HLS Compiler. |
Link |
User Guide
Provides instructions on synthesizing, verifying, and simulating intellectual property (IP) that you design for Intel FPGA products. Go through the entire development flow of your component from creating your component and testbench up to integrating your component IP into a larger system with the Intel Quartus Prime software. |
Link |
Reference
Manual
Provides reference information about the features supported by the Intel HLS Compiler. Find details on Intel® HLS Compiler command options, header files, pragmas, attributes, macros, declarations, arguments, and template libraries. |
Link |
Best Practices
Guide
Provides techniques and practices that you can apply to improve the FPGA area utilization and performance of your HLS component. Typically, you apply these best practices after you verify the functional correctness of your component. |
Link |
Quick
Reference
Provides a brief summary of Intel HLS Compiler declarations and attributes on a single two-sided page. |
Link |
2. Overview of the Intel High Level Synthesis (HLS) Compiler Pro Edition
You can use the same testbench to verify your design both when it is compiled to x86-64 instructions or to RTL.
The Intel® HLS Compiler Pro Edition is command-line compatible with g++, and supports most of the g++ compiler flags. See the Intel® High Level Synthesis Compiler Reference Manual for a full list of compiler flags.
The Intel® HLS Compiler Pro Edition recognizes the same file name extensions as g++, namely .c, .C, .cc, .cpp, .CPP, .c++, .cp, and .cxx. The compiler treats all of these file types as C++. The compiler does not explicitly support C, other than as a subset of C++.
- Generated IP
- High-Level Design Reports (report.html)
- Verification testbench files
- Quartus project that you can use to accurately estimate area requirements and fMAX for your design.
To specify the name of the compiler output, include the -o <result> option in your i++ command, where <result> is the name of the executable. This command creates a project directory called <result>.prj.
Running the executable file runs your testbench. When you target the compilation to an x86-64 architecture, the output executable runs your design on the CPU like a regular C++ program. The output executable runs very quickly compared to running a simulation of your component RTL. When you target the compilation to an FPGA architecture, the output executable simulates your component RTL. This simulation can take a long time to run.
2.1. High Level Synthesis Design Flow
- Creating your component and testbench.
You can write a complete C++ application that contains both your component code and your testbench code.
For details, see Creating a High-Level Synthesis Component and Testbench.
- Verify the functionality of your component algorithm and testbench.
Verify the functionality by compiling your design to an x86-64 executable and running the executable. For details, see Verifying the Functionality of Your Design.
- Optimize and refine the FPGA performance of your component.
Optimize the FPGA performance of your component by compiling your design to an FPGA target and reviewing the high-level design report to see where you can optimize your component. This step generates RTL code for your component. For details, see Optimizing and Refining Your Component.
After initial optimizations, you can see where to further refine your component by simulating it. For details, see Verifying Your IP with Simulation.
- Synthesize your component with
Intel®
Quartus® Prime.
For details, see Synthesize your Component IP with Intel Quartus Prime Pro Edition.
Synthesizing your component generates accurate quality-of-results (QoR) metrics like FPGA area utilization and fMAX.
- Integrate your IP into a system with
Intel®
Quartus® Prime or Platform Designer
(formerly Qsys).
For details, see Integrating your IP into a System.
2.2. The Project Directory
Directory | Description |
---|---|
components | Contains a folder for each component, and all HDL and IP files that are needed to use that component in a design. |
verification | Contains all the files for the verification testbench. |
reports | Contains the High-Level Design Reports. The High-Level Design Reports are a set of reports and viewers that you open in a web browser. Use the reports to analyze the synthesized hardware implementation of your components and tasks. |
quartus | Contains an
Intel®
Quartus® Prime project that
instantiates the components. You can compile this
Intel®
Quartus® Prime project to generate more
detailed timing and area reports. Do not use the contents of this subdirectory to integrate your component in a design. Use the contents of the components directory. |
3. Creating a High-Level Synthesis Component and Testbench
While the compiler supports C++17, you can often achieve better component performance by using the supported subset of C99 whenever possible. The compiler is capable of synthesizing some C++ constructs, which might be easier for you to use to create cleaner code.
For more information about the supported subset of C99 and its restrictions, see "Supported Subset for Component Synthesis" in Intel® High Level Synthesis Compiler Pro Edition Reference Manual.
You can identify a function in your C++ application that you want to synthesize into RTL in one of the following ways:
- Insert the component keyword in the source code before the top-level C++ function to be synthesized.
-
Specify the function on the command line by using the
--component <component_list>
option of the i++ command.
To use this option, your component must be configured with C-linkage using the extern "C" specification. For example:
extern "C" int myComponent(int a, int b)
Components are synthesized into RTL for all functions labeled with the component keyword and for all components listed in the --component <component_list> option of the i++ command. Avoid combining these methods because you might unexpectedly synthesize unwanted components.
If you do not want components synthesized into RTL for a function, ensure that you do not have the component attribute specified in the function and ensure that the function is not specified in the --component <component_list> option of the i++ command.
You can see which components were synthesized into RTL in the summary page of the High-Level Design Reports ( <name>.prj/reports/report.html). For more information about the High-Level Design Reports, see The High-Level Design Reports.
The HLS compiler creates an executable to run on the CPU. The compiler then sends any calls to functions that you declared as components to simulation of the synthesized IP core, and the simulation results are returned.
3.1. Intel HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
Tool Invocation | __INTELFPGA_COMPILER__ |
---|---|
g++ or cl | Undefined |
i++ -march=x86-64 | 2040 |
i++ -march="<FPGA_family_or_part_number>" | 2040 |
Tool Invocation | HLS_SYNTHESIS | |
---|---|---|
Testbench Code | HLS Component Code | |
g++ or cl | Undefined | Undefined |
i++ -march=x86-64 | Undefined | Undefined |
i++ -march="<FPGA_family_or_part_number>" | Undefined | Defined |
4. Verifying the Functionality of Your Design
Verify the functionality of your design by compiling your component and testbench to an x86-64 executable that you can debug with a native C++ debugger. This process is sometimes referred to as debugging through emulation.
Compiling your design to an x86-64 executable is faster than generating and simulating RTL. This faster compilation time lets you debug and refine your component algorithms quickly before you move on to see how your component is implemented in hardware.
- Use the i++ -march=x86-64 command.
- On Linux systems, use the g++ command.
- On Windows systems, use Microsoft Visual Studio.
- Running the program to see if generates the expected output.
- Using printf statements in your code to output variable values at certain points in your code.
- Stepping through your code with a debugger.
If you want step through your code with a debugger, ensure that you set your compiler command to include debug information and to generate unoptimized binary files. The i++ command generates debug information by default, and the -march=x86-64 command option generates unoptimized binary files.
On Linux systems, you can use GDB to debug your component and testbench, even if you used the i++ command to compile your code for functional verification.
On Windows systems, you can use Microsoft Visual Studio to debug your component and testbench, even if you used the i++ command to compile your code for functional verification.
Using the g++ command or Microsoft Visual Studio might require additional configuration to compile your Intel® HLS Compiler Pro Edition code. For details, see Compiler Interoperability in the Intel® High Level Synthesis Compiler Pro Edition Reference Manual.
You can automate the process by using a makefile or batch script. Use the makefiles and scripts provided in the Intel® HLS Compiler Pro Edition example designs and tutorials as guides for creating your own makefiles or batch scripts.
5. Optimizing and Refining Your Component
After you have verified the functionality of your component and testbench, you can compile your component to RTL and review the High-Level Design Reports to further optimize and refine your component design. The High-Level Design Reports show estimates of various aspects of how your component will be implemented in hardware.
i++ -march="<FPGA_family_or_part_number>" --simulator none
You can also compile your component with a ModelSim* simulation flow by omitting the --simulator none option. Compiling without a simulation test bench is faster, but you cannot simulate your design to measure its latency and generate waveforms.
<result>.prj/reports/report.html
For information about techniques that you can apply to optimize and refine your component, see Intel® High Level Synthesis Compiler Pro Edition Best Practices Guide .
5.1. The High-Level Design Reports
The High-Level Design Reports are a group of reports and viewers that you can use to help optimize your design by reviewing the statistics and visualizations that the reports provide.
Access the High-Level Design Reports by using a web browser to open the report.html file found in the <name>.prj/reports folder created when you compile your component to RTL.
Use the tutorials provided with the Intel® HLS Compiler to view examples of the reports and learn how to use the reports and viewers to help optimize and refine your component design.
For details about using the reports to help optimize your design, review Reviewing the High-Level Design Reports (report.html).
In some cases, information in the reports and viewers are estimates and might not match the results from compiling your design with Intel® Quartus® Prime software. However, Compiling your component using the Intel® Quartus® Prime software might take several hours. In contrast, the Intel® HLS Compiler can generate the High Level Design Report in minutes for most designs.
- The report under Summary gives you a quick overview of the results of compiling your design including a summary of each component in your design and a summary of the estimated resources that each component in your design uses.
- The reports under Throughput Analysis help you optimize your design based results from analyzing loops and providing key performance metrics on component blocks.
- The reports under Area Analysis help you locate area usage inefficiency. The reports provide a detailed breakdown of the estimated FPGA area usage. It also provides feedback on key hardware features such as private memory configuration.
- The viewers under System Viewers provide different views into the structure, interfaces, datapaths, and computation flows in your component. These views can help identify bottlenecks in your design.
Category | Report or Viewer Name | Description |
---|---|---|
Summary | Summary | The Summary Report gives you a quick overview of the results
of compiling your design including a summary of each component in your design and a
summary of the estimated resources that each component in your design uses. The Functions section shows you the short names generated for overloaded and templated functions in your hardware design by the Intel® HLS Compiler to prevent name collisions. These short names are used in other parts of the High Level Design Report. Other sections of the summary contain information only after you compile your design with Intel® Quartus® Prime software. |
Throughput Analysis | Loop Analysis | The Loop Analysis Report shows the loop optimization
strategies either applied by the compiler or through the various loop pragmas
available. The report also provides key performance metrics on all blocks including any target II, scheduled fMAX, block II, and maximum interleaving iterations. You can use this report to help you with the following tasks:
Important:
The
scheduled fMAX that this report displays is not
an accurate estimate of the fMAX that your
design can achieve.
Synthesize your component with
Intel®
Quartus® Prime to ensure that your design meets your
performance requirements. You might also find that you can lower your scheduled
fMAX target to save FPGA area utilization.
|
Loop Viewer (alpha) | The Loop Viewer shows you the behavior of both implicit and explicit loops in your component and task functions as a color-coded bar graph. | |
Verification Statistics | For each component that the testbench calls, the verification
statistics report provides information such as the number and type of invocations,
latency, initiation interval, and throughput. This report is available only after you simulate your component. |
|
Area Analysis | Area Analysis of System | This report provides a detailed breakdown of the estimated
FPGA area usage of your design. It also provides information about key hardware
features such as private memory configuration. The Quartus Fit... sections are empty or hidden until you compile your design with Intel® Quartus® Prime software. The estimated area usage information correlates with, but does not necessarily match, the resource usage results from the Intel® Quartus® Prime software. Use the estimated area usage to identify parts of the design with large area overhead. You can also use the estimates to compare area usage between different designs. Do not use the estimated area usage information for final resource utilization planning. |
Area Analysis of Source | This report is deprecated and might be removed in a future release. Use the Area Analysis of System report instead. | |
System Viewers | Graph Viewer | The Graph Viewer is an interactive view of your system that
allows you to review information such as the sizes and types of loads and stores,
stalls, and latencies. Clicking on different entries in the hierarchical graph list displays different views of your design.
|
Function Memory Viewer | The Function Memory Viewer shows you the memory system that the Intel® HLS Compiler generated for your component. Use the Function Memory Viewer to help you identify data movement bottlenecks in your component design. | |
Schedule Viewer | The Schedule Viewer shows the estimated start and ending clock cycle for functions, blocks, clusters, and individual instructions in your design. |
6. Verifying Your IP with Simulation
The Intel® HLS Compiler Pro Edition uses Mentor Graphics® ModelSim® software to perform the simulation. You must have ModelSim* installed to use the Intel® HLS Compiler. For a list of supported versions of the ModelSim software, refer to the EDA Interface Information section in the Intel® Quartus® Prime Software and Device Support Release Notes.
Verifying the functionality of your design in this way is sometimes called debugging through simulation.
- Run the executable that the compiler generates by targeting the
FPGA architecture. By default, the name of the executable is a.out (Linux) or a.exe (Windows).For example, you might invoke a command like tone of the following commands for a simple single-file design:
- Linux: i++ -march="Arria10" […] design.cpp && ./a.out
- Windows: i++ -march="Arria10" […] design.cpp && a.exe
- Write variable values to output streams at certain points in your code.
- Review the waveforms generated when running your design.
The compiler does not log signals by default when you compile your design. To enable signal logging in simulation, refer to Debugging during Verification.
6.1. Generation of the Verification Testbench Executable
- Parses your design, and extracts the functions and symbols necessary for component synthesis to the FPGA. The HLS compiler also extracts the functions and symbols necessary for compiling the C++ testbench.
- Compiles the testbench code to generate an x86-64 executable that also runs the simulator.
- Compiles the code for component synthesis to the FPGA. This compilation generates RTL for the component and an interface to the x86-64 executable testbench.
6.2. Debugging during Verification
By default, the HLS compiler instructs the simulator not to log any signals because logging signals slows the simulation, and the waveforms files can be very large. However, you can configure the compiler to save these waveforms for debugging purposes.
i++ -march="<FPGA_family_or_part_number>" -ghdl[=<depth>] <input files>Specify the <depth> attribute to specify how many levels of hierarchy are logged. Specify -ghdl=1 to log only top level signals. If you do not specify the <depth> attribute, all signals are logged.
When the simulation finishes, open the vsim.wlf file inside the <result>.prj/verification directory to view the waveform.
To view the waveform after the simulation finishes:
- In ModelSim* , open the vsim.wlf file inside the <result>.prj/verification directory.
-
Right-click the
<component_name>_inst block
and select Add Wave.
You can now view the component top-level signals: start, busy, stall, done, parameters, and outputs. Use the waveform to see how the component interacts with its interfaces.
Tip:When you view the simulation waveform in ModelSim* , the simulation clock period is set to a default value of 1000 picoseconds (ps). To synchronize the Time axis to show one cycle per tick mark, change the time resolution from picoseconds (ps) to nanoseconds (ns):
- Right-click the timeline and select Grid, Timeline & Cursor Control.
- Under Timeline Configuration, set the Time units to ns.
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
Function | Description |
---|---|
ihc_hls_enqueue(void* retptr, void* funcptr, …) | This function enqueues one invocation of an HLS component. The return value is stored in the first argument which should be a pointer to the return type. The component does not execute until the ihc_hls_component_run_all() function is invoked. |
ihc_hls_enqueue_noret(void* funcptr, …) | This function is similar to ihc_hls_enqueue(void* retptr, void* funcptr, …), except that it does not have an output pointer to capture return values. |
ihc_hls_component_run_all (void* funcptr) | This function executes all enqueued calls to the specified component in a pipelined fashion. |
6.3.1. Execution Model
6.3.2. Comparison of Explicit and Enqueued Function Calls
Figure 2 illustrates the waveform of the signals for the component dut. The testbench does not include any enqueue function calls.
#include "HLS/hls.h" #include <stdio.h> component int dut(int a, int b) { return a*b; } int main (void) { int x1, x2, x3; x1 = dut(1, 2); x2 = dut(3, 4); x3 = dut(5, 6); printf("x1 = %d, x2 = %d, x3 = %d\n", x1, x2, x3); return 0; }

#include "HLS/hls.h" #include <stdio.h> component int dut(int a, int b) { return a*b; } int main (void) { int x1, x2, x3; ihc_hls_enqueue(&x1, &dut, 1, 2); ihc_hls_enqueue(&x2, &dut, 3, 4); ihc_hls_enqueue(&x3, &dut, 5, 6); ihc_hls_component_run_all(&dut); printf("x1 = %d, x2 = %d, x3 = %d\n", x1, x2, x3); return 0; }

7. Synthesize your Component IP with Intel Quartus Prime Pro Edition
When you are satisfied with the predicted performance of your component, use Intel® Quartus® Prime Pro Edition to synthesize your component. Synthesis also generates accurate area and performance (fMAX) estimates for your design, however your design is not expected to cleanly close timing in the Intel® Quartus® Prime reports.
You can expect to see timing closure warnings in the Intel® Quartus® Prime logs because the generated project in the Intel® HLS Compiler quartus folder targets a clock speed of 1000 MHz to achieve the best possible placement for your design. The fMAX value presented in the High-Level Design Reports is an estimate of the maximum clock rate that your component can cleanly close timing for.
After the Intel® Quartus® Prime compilation completes, the High-Level Design Reports show the area and performance data for your components. These estimates are more accurate than estimates generated when you compile your component with the Intel® HLS Compiler Pro Edition.
Typically, Intel® Quartus® Prime compilation times can take minutes to hours depending on the size and complexity of your components.
To synthesize your component IP and generate quality of results (QoR) data, do one of the following actions:
-
Instruct the HLS compiler to run the
Intel®
Quartus® Prime compilation flow automatically after synthesizing the
components. Include the
--quartus-compile
option in your i++ command.
i++ -march="<FPGA_family_or_part_number>" --quartus-compile ...
If you are trying to get an accurate estimate of the fMAX range of your component, use the --quartus-seed option to automate seed sweeps:i++ -march="<FPGA_family_or_part_number>" --quartus-compile --quartus-seed <num_of_sweeps> ...
-
If you already have the RTL for you component synthesized, you
can navigate to the quartus directory and
compile the
Intel®
Quartus® Prime project by invoking the
following command:
quartus_sh --flow compile quartus_compile
Tip: Add the path to quartus_sh (Linux) or quartus_sh.exe (Windows) to your PATH environment variable.
8. Integrating your IP into a System
To integrate your HLS compiler-generated IP into a system with Intel® Quartus® Prime, you must be familiar with Intel® Quartus® Prime Pro Edition as well as the Platform Designer (formerly Qsys Pro) system integration tool included with Intel® Quartus® Prime.
For overloaded and templated functions in your hardware design, the Intel® HLS Compiler sometimes generates short names to prevent name collisions. Use these short names when integrating the generated RTL into your design.
Review the Summary Report in the High-Level Design Reports (report.html) to see any short names generated by the compiler.8.1. Adding the HLS Compiler-Generated IP into an Intel Quartus Prime Pro Edition Project
- Create an Intel® Quartus® Prime Pro Edition project.
- Click Project > Add/Remove Files in Project.
-
In the Settings dialog
box, browse to and select the component .ip
file:
For example, <result>.prj/components/<component_name>/<component_name>.ip
- Instantiate the component top-level module in the Intel® Quartus® Prime project. For an example on how to instantiate the component's top-level module, refer to the <result>.prj/components/<component_name>/<component_name>_inst.v file.
8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
In Platform Designer, if your HLS compiler-generated IP does not appear in the IP Catalog, perform the following tasks:
- In Intel® Quartus® Prime, click Tools > Options.
- In the Options dialog box, under Category, expand IP Settings and click IP Catalog Search Locations.
- in the IP Catalog Search Locations dialog box, add the path to the directory that contains the .ip file to IP Search Paths as <result>.prj/components/<component_name>/<component_name> .
- In IP Catalog, add your IP to the Platform Designer system by selecting it from the HLS project directory.
For an example of adding HLS compiler-generated IP to a Platform Designer systems, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/usability/platform_designer_stitching.
A. Reviewing the High-Level Design Reports (report.html)
A.1. Reviewing the Summary Report
The Summary Report gives you a quick overview of the results of compiling your design including a summary of each component in your design and a summary of the estimated resources that each component in your design uses.
- Compile Info
- Functions
- Clock Frequency Summary
- Quartus Estimated Resource Utilization Summary
- HLS Estimated Resource Utilization Summary
- Warnings Summary

Compile Info
- Name of the project
- Target FPGA family and device
- HLS compiler version
- Intel® Quartus® Prime version
- The command that was used to compile the design
- The date and time at which the reports were generated
Functions
For overloaded and templated functions in your hardware design, this section of the Summary Report shows you the short names generated by the Intel® HLS Compiler for the functions to prevent name collisions.These short names are used in other parts of the High Level Design Report.
The Synthesized Function Name Mapping section does not show testbench functions. Only functions that are synthesizable to hardware are shown.
Clock Frequency Summary
- Quartus Fitter Clock Frequency
- Compiler Target Frequency (MHz)
- Compiler estimated frequency (MHz)
The Quartus Fitter clock frequency is the maximum clock frequency that can be achieved for the design. When the compiler estimates a lower frequency than the targeted frequency, the frequency value is highlighted in red.
Both the Functions section and Clock Frequency Summary display the target clock frequency applied at the source on the component. When the values of the source is different than the compilation flag you applied, the Clock Frequency Summary Compiler Target Frequency shows “Various” instead of reporting a number.
Quartus Estimated Resource Utilization Summary
After you compile your design with Intel® Quartus® Prime software, the Quartus Estimated Resource Utilization Summary section shows the total area utilization both for the entire design, and for each component individually. There is no breakdown of area information by source line.
Function Summary
When you compile your design to target Intel® Agilex™ or Intel® Stratix® 10 devices, this section of the report indicates whether a function in your design uses a modified handshaking protocol.You can control the use of the modified handshaking protocol with the --hyper-optimized-handshaking option of the i++ command.
HLS Estimated Resource Utilization Summary
The HLS Estimated Resource Utilization Summary section shows a summary of the estimated resources used by each component in your design, as well as the total resources used for all components.
Warnings Summary
The Warnings Summary section shows the compiler warnings generated during the compilation.
A.2. Reviewing Factors That Affect Throughput
The High-Level Design Reports (report.html) contain reports and tools that help you to understand the behavior of loops in your component and tasks. You can also view information about your component that is collected after simulation.
-
Loop Analysis Report
The Loop Analysis report contains information about all the loops (coalesced, unrolled, and fused loops) in your design and their unroll statuses.
-
Loop Viewer (Alpha)
The Loop Viewer shows the behavior of implicit and explicit loops in your design as a color-coded bar graphs. You adjust the trip counts of the loops in the viewer to see how the behavior of your design might change with different trip counts for loops.
-
Verification Statistics Report
After you simulate your design, you can review information such as the number and type of invocations, latency, initiation interval, and throughput. for each component that the testbench calls.
A.2.1. Loop Analysis Report
The Loops Analysis report in the High-Level Design Reports (<result>.prj/reports/report.html) contains information about all the loops (coalesced, unrolled, and fused loops) in your design and their unroll statuses. This report helps you examine whether the Intel® HLS Compiler Pro Edition can maximize the throughput of your component.
To access the report, click Throughput Analysis > Loop Analysis.
- Loop List
Refer to Loop List Pane for details.
- Loop Analysis
Refer to Loop Analysis Pane for details.
- Bottlenecks
Refer to Bottlenecks Pane for details.
- Code view
When you click a link under Source Location in the Loop Analysis pane, the code view pane highlights the statement in your code that analysis applies to.
- Details
When you click a row in the Loop Analysis pane, the Details pane provides additional details.
Loop List Pane
The left-hand Loop List pane displays the following types of loops:
- Fused loops
- Fused subloops
- Coalesced loops
- Fully unrolled loops
- Partial unrolled loops
- Regular loops
Loop Analysis Pane
The Loops Analysis report captures the following key performance metrics on all blocks:
- Source Location: Indicates the loop location in the source code.
- Pipelined: Indicates whether the body of a loop is pipelined. Pipelining allows for many data items to be processed concurrently (in the same clock cycle) while making efficient use of the hardware in the datapath by keeping it occupied.
-
II: Shows the
sustainable initiation interval (II) of the loop. Processing data in loops is an
additional source of pipeline parallelism. When you pipeline a loop, the next
iteration of the loop begins before previous iterations complete.
You can determine the number of clock cycles between iterations by the number of clock cycles you require to resolve any dependencies between iterations. You can refer to this number as the initiation interval (II) of the loop.
The Intel® HLS Compilerautomatically identifies these dependencies and builds hardware to resolve these dependencies while minimizing the II.
- Scheduled f MAX : Shows an early estimate of the maximum clock frequency (fMAX) at which the loop operates. This estimate does not account for the effects of placing and routing.
- Latency: Shows the number of clock cycles a loop takes to complete one or more instructions. Typically, you want to have low latency. However, lowering latency often results in decreased fMAX.
-
Speculated Iterations:
Shows the loop speculation. Loop speculation is an optimization technique that
enables more efficient loop pipelining by allowing future iterations to be
initiated before determining whether the loop was exited already.
For more information, refer to Loop Iteration Speculation (speculated_iterations Pragma) in the Intel HLS Compiler Reference Manual.
-
Max Interleaving
Iterations: Indicates the number of interleaved invocations of
an inner loop that can be executed simultaneously.
For more information, refer to Loop Interleaving Control (max_interleaving Pragma) in the Intel HLS Compiler Reference Manual.
Bottlenecks Pane
Bottlenecks in a loop mean that one or more loop-carried dependencies cause the loop to have an II greater than 1 or cause the fMAX of your component to be lowered to achieve a loop II of 1.
The Bottlenecks pane identifies the following categories of loop bottlenecks in your components and task:
- fMAX-reduction, II-increase, or both
- Compiler-applied bottlenecks (private copies set to 1 on local memory)
- Bottlenecks caused due to the pragmas or attributes that you apply to a loop
- Concurrency-limiter bottleneck
-
Graph Viewer (Beta)
The Graph Viewer provides information about the isolated failing path and bottleneck type.
-
Schedule Viewer (Beta)
The Schedule Viewer displays the bottleneck path for variables.
A.2.2. Loop Viewer (Alpha)
Use the Loop Viewer in the High-Level Design Reports to see the behavior of both implicit and explicit loops in your component and task functions. The Loop Viewer shows the behavior as a color-coded bar graph.
By default, the Loop Viewer shows the visualization for one iteration (trip count of 1) of the loops, unless the loop is defined in your code with a constant number of iterations. You can adjust the number of displayed iterations and update the viewer to see how different trip counts for loops affect your component.
To access this tool report, click Throughput Analysis > Loop Viewer.
- Loop List
The Loop List pane shows a list of the explicit and implicit loops identified by the compiler in your design.
Click entries in the Loop List pane to focus the graphs shown in the Loop Viewer pane on a loop in your design, or click System to have all loops in your design show in the Loop Viewer pane.
- Loop Viewer
Refer to Loop Viewer Pane for details.
- Bottlenecks
This pane does not provide any information in the Loop Viewer.
To see information about loop bottlenecks, use the Bottlenecks pane in the Loop Analysis Report. For details about this report, refer to Loop Analysis Report.
- Code view
The code view pane lets view all the code associated with your design.
- Details
When you click a row in the Loop View pane, the Details pane provides any additional details if they are available.
Loop Viewer Pane
The Loop Viewer pane is split into the following parts:
- The left part shows labels for loops and their parts, and the start and
end cycle for the loop parts. This part also shows the number of trip counts displayed for
a loop.
To adjust the number of trip counts displayed for a loop, change the value in the Trip Count field for a loop and click Update.
You might need to scroll left and right to see the Trip Count fields and the Update button.
- The right part shows the duration (in number of clock cycles) of loop
invocations and loop iterations as horizontal bars on a graph, similar to the presentation
of Gantt charts.The horizontal bars are color-coded as follows:
Table 7. Loop Viewer Color Coding Color Description Black bars show the length of a loop invocation. A loop can be invoked multiple times when your design runs.
Pink bars show the length of a loop iteration. A loop iteration is one execution of the body of your loop. One loop invocation typically results in more than one loop iteration.
Light-pink bars show speculated loop iterations. Speculated iterations are loop iterations that are initiated while the loop exit condition is being calculated. They help enable more efficient loop pipelining in your component.
For more information about speculated iterations, refer to Loop Iteration Speculation (speculated_iterations Pragma) in the Intel High Level Synthesis Compiler Pro Edition Reference Manual .
Blue bars show the execution of logic outside of the innermost loop body, including loop control logic created by the compiler. Light-blue bars show handshaking registers added by the compiler.
A.2.3. Verification Statistics Report
The verification statistics report becomes available after you simulate your component.
- The data presented in the verification statistics report might be dependent on the input values to the component from the test bench.
- The verification statistics report only reports the component loop initiation interval (II) values and throughput for enqueued invocations.
The following example verification statistics report is for a component dut that has been run once as a simple function call and 100 times as an enqueued invocation:
For components that use explicit streams, such as ihc::stream_in<> or ihc::stream_out<>, the verification statistics report also provides the throughput for each individual stream, as shown in the details pane:
View the simulation waveform by following the instructions in Debugging during Verification.
A.3. Reviewing Component Area Usage
The Area Analysis of System report (Area Analysis > Area Analysis of System) in the High-Level Design Reports (report.html) provides a detailed breakdown of the estimated FPGA area usage. It also provides information about key hardware features such as private memory configuration.
The estimated area usage information correlates with, but does not necessarily match, the resource usage results from the Intel® Quartus® Prime Pro Edition software. Use the estimated area usage to identify parts of the design with large area overhead. You can also use the estimates to compare area usage between different designs. Do not use the estimated area usage information for final resource utilization planning.
The System entry in the Area Analysis of System report refers to all the components in the design. Expanding the System entry allows you to view all the components in the design.
A.4. Reviewing Component Architecture
-
Graph Viewer (Beta)
The Graph Viewer is an interactive view of your system as a hierarchy of block diagrams of how the compiler constructed your component. These diagrams can help you understand how data flows through your component. Clicking on different parts of a digram shows you information such as the sizes and types of loads and stores, stalls, and latencies. The information is presented at various levels of granularity: system, function (component and task), block, and cluster.
-
Function Memory Viewer
The Function Memory Viewer report shows the data connections across the memory system of your component.
-
Schedule Viewer (Beta)
The Schedule Viewer report displays a Gantt-chart-like format that shows when each instruction is active relative to the other instructions.
A.4.1. Graph Viewer (Beta)
The Graph Viewer is an interactive view of your system as a hierarchy of block diagrams of how the compiler constructed your component. These diagrams can help you understand how data flows through your component.
Access system-, function-, block-, and cluster-level views of your component by selecting System Viewers > Graph Viewer in the High Level Design Reports menu.
The Graph Viewer represents your component and tasks as a system of functions. Each function is divided into a set of blocks. Inside each block is a set of non-branching instructions that covers your code and the compiler loop orchestration optimization. The connections between blocks show the execution flow of your component.
To save the amount of control handshaking infrastructure needed when synthesizing your design, the Intel® HLS Compiler Pro Edition groups instructions within a block into groups called clusters. For more information about clusters, refer to "Clustering the Datapath" in the Intel® HLS Compiler Best Practices Guide .
A branch node indicates the next block to go to and the condition required to go to that block.
The Graph Viewer is divided into two main panes: Graph List and Graph View. Clicking on different entries in the Graph List shows you different views of your component.
The different views available are as follows:.
-
System View
The System View of the Graph Viewer provides a high-level view of components and tasks in your system.
-
Function View
The Function views of the Graph Viewer show the blocks inside your component and any tasks. A function appears in this view if it is declared as component or launched as a task function. Other called functions are automatically inlined.
Click a function name in the Graph List of the Graph Viewer to see the function view.
-
Block View
The Block views of the Graph Viewer show stallable operations in your component and task functions, and the clusters and their connections.
-
Cluster View
The Cluster views of the Graph Viewer shows the contents of clusters in your components.
Hovering over elements in the Graph View pane typically displays a tooltip with details about the element and highlights connections to and from the element.
Clicking on an element displays details about the element in the Details pane below Graph List and Graph Viewer panes and highlights connections to and from the element.
You can control the zoom of the diagram in the Graph Viewer pane using your mouse scroll wheel or equivalent touchpad gesture.
A.4.1.1. Reviewing System Information
Use the System View in the Graph Viewer report to view of the various components in your system as well as the tasks. Additionally, this view displays the connectivity between a component and its tasks.
Click the system in the Graph List pane to see the
system in the Graph View pane.
The System View of the Graph Viewer shows ihc::launch and ihc::collect calls that are the synchronization points from component/task to the task function. They are represented as write nodes (labeled WR) and read nodes (labeled RD) that connect to the call.task_name and return.task_name nodes of the corresponding task.
This report also shows explicit streaming interfaces between tasks with the name of the stream displayed as a rectangular node in the connection between the tasks connected by the streaming interface.
A.4.1.2. Reviewing Function Information
The diagram of your function starts with an initialization block, called the runOnce block. When a function contains loops, cycles of blocks form, depending on the loop structure. Loops often impose initiation interval (II) bottlenecks and are a main optimization focus when you optimize your component.
- An input or loop input node
- A set of instructions
- A branch node
For an example of the Function View and the blocks it displays, refer to Reviewing Loops and Blocks in Your Component or Task.
Click a function in the Graph List pane to see the function in the Graph
View pane.
-
Control
Control connections are connections between blocks and loops.
-
Memory
Memory connections are connections between global or local memories.
-
Streams
Stream connections are connections to and from read or write streams
A.4.1.2.1. Reviewing Component Interfaces
Some parameters in your component can be marked as being stable. A parameter can be marked as stable if its argument does not change while your component executes, but the argument might change between component executions. In the Function View, a stable argument does not have any edge connection.
Default (Conduit) Interfaces
#include "HLS/hls.h" struct coordinate_t { int x; int y; }; component int default_comp(int b, coordinate_t p) { return b + p.x; }

For each default interface argument node, you can view details about the node when you hover over the node:
Avalon® MM Master Interfaces
#include "HLS/hls.h" component int master_comp(int *pointer_d, ihc::mm_master<int, ihc::aspace<3>, ihc::awidth<4>, ihc::dwidth<32>, ihc::latency<1>, ihc::align<4>> &master_i, int &result) { result = pointer_d[0] + master_i[0]; return result; }
- Stable
- Describes whether the interface argument is stable. That is, whether the hls_stable_argument attribute was applied.
- Data width
- The width of the memory-mapped data bus in bits.
- Address width
- The width of the memory-mapped address bus in bits.
- Latency
- The guaranteed latency from when the read command exits the component to when the external memory returns valid read data. The latency is measured in clock cycles.
- Maximum burst
- The maximum number of data transfers that can associate with a read or write transaction. For fixed latency interfaces, this value is set to 1.
- Alignment
- The byte alignment of the base pointer address. The Intel® HLS Compiler uses this information to determine the amount of coalescing that is possible for loads and stores to this pointer.
- Memory address space number
- The memory address space number for Avalon® MM Master interface.
- Number of banks
- The number of memory banks contained in the memory.
- Argument Name:
- The names of arguments that access the Avalon® MM Master interface.


Avalon® MM Slave Register Interfaces
#include "HLS/hls.h" component int slavereg_comp( int hls_avalon_slave_register_argument slave_scalar_f, int* hls_avalon_slave_register_argument slave_pointer_g ) { return slave_scalar_f + *slave_pointer_g; }
The resulting memory map is described in the automatically generated header
file
<component_name>_csr.h. This header file is available in the
menu in the source code pane. Clicking on the CSR
container node in the Function View of the Graph Viewer also opens up the header file:
#include "HLS/hls.h" hls_avalon_slave_component component int slavereg_comp( int hls_avalon_slave_register_argument slave_scalar_f, int* hls_avalon_slave_register_argument slave_pointer_g ) { return slave_scalar_f + *slave_pointer_g; }
Avalon® MM Slave Memory Interfaces
#include "HLS/hls.h" hls_avalon_slave_component component int slavemem_comp( hls_avalon_slave_memory_argument(4096) int* slave_mem_h, int index, int hls_avalon_slave_register_argument slave_scalar_f ) { return slave_mem_h[index] * slave_scalar_f; }
If you look at the same
Avalon®
MM slave
memory interface in the Component Memory Viewer report, the same
<slave memory name> LD/ST node is
shown to be connected to an external RW port.
Avalon® Streaming Interfaces
#include "HLS/hls.h" component int stream_comp( ihc::stream_in<int> &stream_in_c, ihc::stream_out<int> &stream_out_e, int scalar_b ) { stream_out_e.write(scalar_b + 1); return stream_in_c.read() + scalar_b * 2; }
- Width
- The width of the data signal in bits.
- Depth
- The depth of the stream in words
The word size of the stream is the size of the stream datatype.
- Bits per symbol
- Describes how the data is broken into symbols on the data bus.
- Uses Packets
- Indicates whether the interface exposes the startofpacket and endofpacket sideband signals on the stream interfaces. The signals can be access by the packet-based reads and writes.
- Uses Valid
- (stream_in) Indicates whether a valid signal is present on the stream interface. When Yes, the upstream source must provide valid data on every cycle that ready is asserted.
- Uses Ready
- (stream_in) Indicates whether a ready signal is present on the stream interface. When Yes, the downstream sink must be able to accept data on every cycle that valid is asserted.
A.4.1.2.2. Reviewing Loops and Blocks in Your Component or Task
The Function Views of the Graph Viewer in the High Level Design Report (report.html) shows an abstracted netlist of your component design. In the Function Views, you can visualize loops in your component and your component interactions with its internal RAM block and external interfaces.
#include "HLS/hls.h" #include <stdio.h> #include <stdlib.h> #define SIZE 32 typedef ihc::stream_in<int> my_operand; typedef ihc::stream_out<int> my_result; component void transpose_and_fold(my_operand &data_in, my_result &res) { int i; int j; int in_buf[SIZE][SIZE]; int tmp_buf[SIZE][SIZE]; for (i = 0; i < SIZE * SIZE; i++) { in_buf[i / SIZE][i % SIZE] = data_in.read(); tmp_buf[i / SIZE][i % SIZE] = 0; } #ifdef USE_IVDEP #pragma ivdep safelen(SIZE) #endif for (j = 0; j < SIZE * SIZE * SIZE; j++) { #pragma unroll for (i = 0; i < SIZE; i++) { tmp_buf[j % SIZE][i] += in_buf[i][j % SIZE]; } } for (i = 0; i < SIZE * SIZE; i++) { res.write(tmp_buf[i / SIZE][i % SIZE]); } }
The figure below shows that Block3 is highlighted in red to prompt you to review the loop in the Loop Analysis Report. The report shows that Block3 is a pipelined loop with an II value of 2. The loop pipeline with this II value might affect the throughput of your design.
The Loop Analysis Report shows that the II value is caused by a memory dependency on loads to the b_buf variable.
Confirm the memory dependency by looking at the memory arbitration in the Function Memory Viewer.

By hovering your mouse pointer over a node, you can view the tooltip and details that provide more information on the LSU. In the figure below, the tooltip shows information like the latency and that the LSU is stall-free.
For stallable nodes, latency values provided are estimates.

-
Control
Control connections are connections between blocks and loops.
-
Memory
Memory connections are connections between local memories, slave memories, or Avalon® MM Master interfaces.
-
Streams
Stream connections are connections to and from read or write streams

A.4.1.3. Reviewing Block Information
Use the Block Views in the Graph Viewer report to inspect the datapath of your design. The report shows the datapath within and between input nodes, clusters, and instructions that cannot be grouped into clusters.
If your design has loops, the compiler encapsulates the loop control logics into loop orchestration nodes (labeled as Loop Orch) and the initial conditions of the loops to loop input nodes.
Click a block in the Graph List pane to see the block
in the Graph View pane.
Within a block, the report shows connections between instruction nodes and cluster nodes.
Click the different nodes and look at the Details panel to see the information about the node.
For instruction nodes, you can find the type of instruction with specific details. For example, on a stream RD or WR node, you can see the width, depth, name, scheduling info, stall-free attributes of a stream in the Details panel. For stallable nodes, the latency value provided is an estimate.
For cluster nodes, you can find the type of the cluster and other cluster attributes.
A.4.1.4. Reviewing Cluster Information
Use the Cluster Views in the Graph Viewer report to examine the data path of computations within a cluster. The Intel® HLS Compiler Pro Edition groups instructions into clusters to reduce the amount of handshaking logic required when synthesizing your component.
For a description of clusters, review " Clustering the Datapath " in the Intel® HLS Compiler Pro Edition Best Practices Guide .
A cluster starts with an entry node and ends with an exit node. These nodes perform handshaking with logic outside of the cluster.
For a stall-free cluster, the exit node of the cluster has a FIFO with a depth greater than or equal to the latency of the cluster. This FIFO stores any in-flight data that needs to be passed outside of the cluster. To see the size of the cluster exit FIFO, click the exit node and see the information in the Details pane.
If your design contains loops, you see loop orchestration nodes (labeled as Loop Orch) and variable nodes as well as computation nodes. The loop orchestration nodes and variable nodes are shown along with their Feedback nodes.
The compiler generates the loop orchestration nodes to pipeline your loop to increase the performance.
A variable node corresponds to a variable that has a loop-carried dependency in your design. A variable node goes through various computation logic and finally feeds to a feedback node that connects back to the variable node. This connection shows that the new value of the variable is passed to the next iteration.
Look for loop-carried variables that have a long latency to the feedback nodes as they can be the initiation interval (II) bottlenecks. See the Loop Analysis report to reflect the II bottleneck.
The feedback node has a FIFO to store in-flight values of the variable in different iterations of the loop and has a size equal to the dependency distance multiplied by the II. The dependency distance is the number of iterations between successive load/store operations that depend on each other.
In a Cluster View, you can find the size of the cluster exit FIFO by clicking the exit node and looking at the Details pane. You can also find the size of the cluster exit FIFO in a Block View by clicking the exit node and looking at the Details pane.
Click a cluster in the Graph List pane to see that cluster in the Graph
View pane.
Click nodes in the Cluster View pane to see details about that node as well as highlight the connections for the node inputs and outputs. For stallable nodes, the latency value provided in the details is an estimate. For more accurate latency values, run simulation on your component.
A.4.2. Function Memory Viewer
Data movement is often a bottleneck in many algorithms. The Function Memory Viewer in the High Level Design Reports (report.html) shows you the memory system that the Intel® HLS Compiler Pro Edition generated for your component. Use the Function Memory Viewer to help you identify data movement bottlenecks in your component design.
Some patterns in memory accesses can cause undesired arbitration in the load-store units (LSUs), which can affect the throughput performance of your component. Use the Function Memory Viewer to find where you might have unwanted arbitration in the LSUs.
Access the Function Memory Viewer by clicking System Viewers > Function Memory Viewer.
The following figure shows the layout of the Function Memory Viewer:
-
Function Memory List pane
The Function Memory List pane lists all of the memories in your design. Click a memory name to see its graphical representation in the Function Memory Viewer pane.
-
Function Memory Viewer pane
The Function Memory Viewer pane shows a graphical representation of the memory system or memory bank selected in the Function Memory List pane.
- Code view pane
The code view pane shows the source code files for which the reports are generated.
-
Details pane
The Details pane shows the details of the memory system or memory bank selected in the Function Memory List pane.

Function Memory List
The Memory List pane shows you a hierarchy of component and task functions, with memories that are synthesized (RAMs, ROMs, and registers) and are optimized away in that component or task.

Icon or Label | Name | Description | |
---|---|---|---|
1 |
![]() |
Component or task name | The list of memories in your component or
task can be expanded or collapsed. Memories that do not belong to any component or task are shown under (Other). |
2 |
![]() |
RAM | A RAM is a memory that has at least one write to it. The name of the RAM memory is the same as its name in your design. Clicking the memory name displays a logical representation of the RAM in the Function Memory Viewer pane. By default, only the first bank of the memory system is displayed.To select which banks to display, expand the memory name. Clear the memory name check box to collapse all memory banks in the view. Select the memory name check box to show all memory banks in the view. |
3 |
![]() |
ROM | A ROM is a memory that is only read from. The name of the ROM memory is the same as its name in your design. Clicking the memory name displays a logical representation of the ROM in the Function Memory Viewer pane. By default, only the first bank of the memory system is displayed.To select which banks to display, expand the memory name. Clear the memory name check box to collapse all memory banks in the view. Select the memory name check box to show all memory banks in the view. |
4 | Bank #num | Bank | A memory bank is always associated with a
RAM or a ROM. Each bank is named as Bank #num
, where #num is the ID of the memory bank starting from 0. Clicking the bank name shows the bank view in the Function Memory Viewer pane: a graphical representation of the bank, with all of its replicates and private copies. This view can help you to focus on specific memory banks when you view a complex memory design. Clear the memory bank name check box to collapse the bank in the logical representation of the memory. Select the memory bank name check box to show the bank in the logical representation of the memory. |
5 |
![]() |
Register | A register is a component variable that is
carried through the pipeline in registers rather than being stored in a RAM or
ROM. The name of the register is the same as its name in your design. A register variable can be implemented either exclusively in flip-flops (FFs), or in a mix of FFs and RAM-based FIFOs. |
6 | text label | Optimized Away | A component variable might be optimized
away because it is unused in your design or compiler optimizations have
transformed all uses of the variable such that it is unnecessary. The name of the optimized away variable is the same as its name in your design. |
7 |
![]() |
Filter | Use the Function Memory List filter to
selectively view the list of RAMs, ROMs, registers and optimized away variables in
your design. Clearing the check box associated with a item in the filter hides all occurrences of that kind of item in the Function Memory List. Filter your Function Memory List to help you focus on a specific type of memory in your design. |
Function Memory Viewer
The Function Memory Viewer pane shows you connections between loads and stores to specific logical ports on the banks in a memory system. It also shows you the number of replicates and private copies created per bank for your memory system. The following types of nodes might be shown in the Function Memory Viewer pane, depending on the component memory system and what you have selected in the Function Memory List pane:
- Memory node: The memory system for a given variable in your design.
- Bank node: A bank in the memory system. A memory system contains at least one memory bank. A memory bank can have one or more port nodes. Only banks selected in the Function Memory List pane are shown.
- Replication node: A replication node shows memory bank replicates that are created to efficiently support multiple accesses to a local memory. A bank contains at least one replicate. You can view replicate nodes only when you view a memory bank by clicking its name in the Function Memory List pane.
- Private-copy node: A private-copy node shows private copies within a replicate that are created to allow concurrent execution of multiple loop iterations. A replicate contains at least one private copy. You can view private-copy nodes only when you view a memory bank by clicking its name in the Function Memory List pane
-
Port node: Each read or write access to a
local memory is mapped to a port. There are three types of port:
- R: A read-only port
- W: A write-only port
- RW: A read and write port
- LSU node: A store (ST) or load (LD) node connected to the memory through port nodes.
- Arbitration node: An arbitration (ARB) node shows that LSUs compete for access to a shared port node, which can lead to stalls.
- Port-sharing node: A port-sharing node (SHARE) shows that LSUs have mutually exclusive access to a shared port node, so the load-store units are free from stalls.
Hover over any node to view the attributes of that node.
Hover over an LSU node to highlight the path from the LSU node to all of the ports that the LSU connects to.
Hover over a port node to highlight the path from the port node to all of the LSUs that read or write to the port node.
Click a node to select it and have the node attributes displayed in the Details pane.


Code View
The code view pane shows your source code. Clicking on a memory or a bank in the Function Memory Viewer pane highlights the line of your code (in the code view pane) where you declared the memory.
Details
The Details pane shows the attributes of the node selected in the Function Memory Viewer pane. For example, when you select a memory in a component, the Details pane shows information such as the width and depths of the memory banks, the memory layout information, the address bit mapping and any user-defined HLS attributes that you specified in your source code.
For an example of this difference, see Example: Specifying Bank-Selection Bits for Local Memory Addresses in the Intel® HLS Compiler Pro Edition Best Practices Guide .
The content of the Details pane persists until you select a different node in the Component/Function Memory Viewer pane.
A.4.3. Schedule Viewer (Beta)
Use the Schedule Viewer to identify latency bottlenecks in your design. The Schedule Viewer shows the estimated start and ending clock cycle for functions, blocks, clusters, and individual instructions in your design.
Click an item in the Schedule List to focus the Schedule View at the selected level. You cannot click the system level of the component hierarchy in the Schedule List.
Click the schedule bar for an item in the Schedule View updates the Details pane with the information available about that item. The information can include a description of the item, start cycle, and latency.
Click an item in the Schedule View to show a popup menu for the item. For instructions, the popup menu includes a link that takes you to your C++ code that resulted in that instruction.
A.5. Accessing HLD FPGA Reports in JSON Format
The JSON files containing the data are available in the <result>.prj/reports/lib/json directory. The directory provides the following .json files:
File | Description |
---|---|
area.json | Area Analysis of System |
area_src.json | Area Analysis of Source (deprecated) |
block.json | Block View of Graph Viewer |
bottleneck.json | Bottleneck View of Loop Analysis Report and Schedule Viewer |
info.json | Summary of project name, compilation command, versions, and timestamps |
loops.json | Navigation tree of Loop Analysis report |
loops_attr.json | Loop Analysis report |
mav.json | Function View of Graph Viewer |
new_lmv.json | Function Memory Viewer |
pipeline.json | Cluster View of Graph Viewer |
quartus.json | Quartus Prime compilation summary |
summary.json | Component compilation name mapping |
system.json | System View of Graph Viewer |
tree.json | Navigation tree of Graph Viewer |
warnings.json | Compilation warning messages |
You can read the following .json files without a special parser:
- area.json
- area_src.json
- loops.json
- quartus.json
- summary.json
For example, if you want to identify all of the values and bottlenecks for the initiation interval (II) of a loop, you can find the information in the children section in the loops.json file, as shown below:
“name”:”<block name|Component: component name> # Find the loops which does not begin with “Component:” “data”:[<Yes|No>, <#|n/a>, <II|n/a>] # The data field corresponds to “Pipelined”, “II”, “Bottleneck”
B. Intel HLS Compiler Pro Edition Restrictions
C++ Language Restrictions
The Intel® HLS Compiler accepts C++ code.
- A component cannot include virtual functions, function pointers, or bit fields.
- Function-scoped static variables that are a part of the component cannot use function arguments for initialization.
- A component or task function cannot contain an irreducible loop. That is, loops in component and task functions must have only one entry point into the loop.
- C++ restrictions
-
- The HLS compiler does not support using lambda functions as components.
- Class membership
-
- HLS component functions cannot be a C++ class member. However, you can declare your component function as a wrapper function. This wrapper function can call a member function of a class or a part of a namespace.
- Exception handling
-
- A component cannot contain exception handling.
- Library calls
-
- The HLS compiler does not currently support calls to C++ runtime libraries on Windows, including calls from the testbench code.
- Library functions
-
- A component cannot contain standard C or C++ library functions, unless they are explicitly supported by header files provided with the Intel® HLS Compiler.
- Multiple inheritance
-
- The HLS compiler does not support classes with multiple inheritance used as parameters. You may use classes as parameters provided that each class inherits from, at most, one class directly.
- Namespaces
-
- HLS component functions cannot be a part of a declared namespace. However, you can declare your component function as a global wrapper function. This wrapper function can call a member function of a class or a part of a namespace
- Parameters
-
- The HLS compiler does not support classes with multiple inheritance used as parameters. You may use classes as parameters if each class inherits from, at most, one class directly.
- Recursion
-
- The HLS compiler does
not support the synthesis of components that use
recursion; however, tail recursion is
supported.
If a component has an algorithm that uses recursion, and it is identified for FPGA acceleration, modify the algorithm to use tail recursion, if possible.
- The HLS compiler does
not support the synthesis of components that use
recursion; however, tail recursion is
supported.
C. Intel HLS Compiler Pro Edition User Guide Archives
Intel® HLS Compiler Version | Title |
---|---|
20.3 | Intel® HLS Compiler Pro Edition User Guide |
20.2 | Intel® HLS Compiler Pro Edition User Guide |
20.1 | Intel® HLS Compiler Pro Edition User Guide |
19.4 | Intel® HLS Compiler Pro Edition User Guide |
19.3 | Intel® HLS Compiler User Guide |
19.2 | Intel® HLS Compiler User Guide |
19.1 | Intel® HLS Compiler User Guide |
18.1.1 | Intel® HLS Compiler User Guide |
18.1 | Intel® HLS Compiler User Guide |
18.0 | Intel® HLS Compiler User Guide |
17.1.1 | Intel® HLS Compiler User Guide |
17.1 | Intel® HLS Compiler User Guide |
D. Document Revision History for Intel HLS Compiler Pro Edition User Guide
Document Version | Intel® HLS Compiler Pro Edition Version | Changes |
---|---|---|
2020.12.14 | 20.4 |
|
2020.08.28 | 20.3 |
|
2020.06.22 | 20.2 |
|
2020.04.14 | 20.1 |
|
2019.12.16 | 19.4 |
|
Document Revision History for Intel® HLS Compiler User Guide
Previous versions of the Intel® HLS Compiler User Guide contained information for both Intel® HLS Compiler Standard Edition and Intel® HLS Compiler Pro Edition.
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.09.30 | 19.3 |
|
2019.07.01 | 19.2 |
|
2019.04.01 | 19.1 |
|
2019.01.03 | 18.1.1 |
|
2018.12.24 | 18.1.1 |
|
2018.09.24 | 18.1 |
|
2018.07.02 | 18.0 |
|
2018.05.07 | 18.0 |
|
2017.12.22 | 17.1.1 |
|
2017.11.06 | 17.1 |
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2017.06.23 | — |
|
2017.06.09 | — |
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2017.02.03 | — |
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2016.11.30 | — |
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2016.09.12 | — |
|