To help you understand how to use the Hybrid Memory Cube Controller IP core, the core features a simulatable testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled design to the Arria^® 10 GX FPGA Development Kit.

The hardware configuration and test files (the hardware design example) are located in <example_design_install_dir>/example_design/par. The simulation files (testbench for simulation only) are located in <example_design_install_dir>/example_design/sim.

The HMC Controller hardware design example includes the following components:

• HMC Controller IP core with CDR reference clock set to 125 MHz and with default RX mapping and TX mapping settings.
  Note: The design example requires these settings to operate properly on the Arria 10 GX FPGA Development Kit with the HMC daughter card.
• Client logic that coordinates the programming of the IP core, and packet generation and checking.
• JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.

Figure 5. Example Design Tab in Hybrid Memory Cube Controller Parameter Editor

Follow these steps to generate the Arria 10 hardware design example and testbench:

1. In the IP Catalog (Tools > IP Catalog), select the Arria 10 target device family.
2. In the IP Catalog, locate and select Hybrid Memory Cube Controller. The New IP Variation window appears.
3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .qsys .
4. You must select a specific Arria 10 device in the Device field, or keep the default device the Quartus Prime software selects.
5. Click OK. The IP parameter editor appears.
6. On the IP tab, specify the parameters for your IP core variation.
7. On the Example Design tab, choose the following settings for the design example:
   1. For Select Design, select the HMCC Daughter Board option.
   2. For Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.
   3. For Generated HDL Format, only Verilog is available.
   4. For Target Development Kit select the Arria 10 GX FPGA Development Kit (Production Silicon).
      Note:

      When you choose this kit, the hardware design example overwrites your previous device selection with the device on the target board.

      When you generate the design example, the Quartus^® Prime software creates Quartus^® Prime project, setting, and pin assignments for the board you selected. If you do not want the software to target a specific board, select None.

8. Click the Generate Example Design button.

Altera provides an design example with the HMC Controller IP core. The design example is available both for simulation of your IP core and for compilation. The design example in simulation functions as the HMC Controller IP core testbench.

If you click Generate Example Design in the HMC Controller parameter editor, the Quartus^® Prime software generates a demonstration testbench. The parameter editor prompts you for the desired location of the testbench.

To simulate the testbench, you must provide your own HMC bus functional model (BFM). Altera tests the design example testbench with the Micron Hybrid Memory Cube BFM. The testbench does not include an I²C master module, because the Micron HMC BFM does not support and does not require configuration by an I²C module.

In simulation, the testbench controls a TX PLL and the data path interfaces to perform the following sequence of actions:

1. Configures the HMC BFM with the HMC Controller IP core data rate and channel width, in Response Open Loop Mode.
2. Establishes the link between the BFM and the IP core.
3. Directs each of the IP core's four ports to write four packets of data to the BFM.
4. Directs the IP core to read back the data from the BFM.
5. Checks that the read data matches the write data.
6. If the data matches, displays TEST_PASSED.

Follow these steps to simulate the testbench:

1. At the command line, change to the <design example>/sim directory.
2. Type make scripts.
3. Type one of the following commands, depending on your simulator:

   Simulator License	Command Line
   Mentor Graphics QuestaSim	make vsim HMC_MODEL=< HMC BFM directory >
   Synopsys VCS	make vcs HMC_MODEL=< HMC BFM directory >
   Cadence NCSIM	make ncsim HMC_MODEL=< HMC BFM directory >

4. To view simulation results:
   • When you run the testbench in any of the three supported simulators, the script executes the testbench sequence and logs the simulator activity in <design example directory> /example_design/sim/ <simulator> .log. <simulator> is "vsim", "ncsim", or "vcs".
   • When you run the testbench in any of the three supported simulators, the script generates a waveform file. You can run the command make <simulator> _gui to load the waveform in the simulator-specific waveform viewer.
   To view the waveform file in your simulator, type one of the following commands:

   Simulator License	Command Line	Waveform File
   Mentor Graphics ModelSim	make vsim_gui	<design example directory> /example_design/sim/mentor/hmcc_wf.wlf
   Synopsys Discovery Visual Environment	make vcs_gui	<design example directory> /example_design/sim/hmcc_wf.vpd
   Cadence SimVision Waveform	make ncsim_gui	<design example directory> /example_design/sim/cadence/hmcc_wf.shm

5. Analyze the results. The successful testbench sends and receives ten packets per port, and displays Test_PASSED"

To compile and run a demonstration test on the hardware design example, follow these steps:

1. Ensure hardware design example generation is complete.
2. In the Quartus^® Prime software, open the Quartus^® Prime project <example_design_install_dir>/example_design/par/hmcc_example.qpf.
3. In the Compilation Dashboard, click Compile Design ( Quartus^® Prime Pro Edition) or choose Processing > Start Compilation ( Quartus^® Prime Standard Edition).
4. After you generate a .sof, follow these steps to program the hardware design example on the Arria 10 device:
   1. Choose Tools > Programmer.
   2. In the Programmer, click Hardware Setup.
   3. Select a programming device.
   4. Select and add the Arria 10 GX FPGA Development Kit to which your Quartus^® Prime session can connect.
   5. Ensure that Mode is set to JTAG.
   6. Click Auto Detect and choose any device.
   7. Double-click the Arria 10 device.
   8. Open the .sof in <example_design_install_dir>/example_design/par/output_files,
      Note: The Quartus^® Prime software changes the device to the one in the .sof.
   9. In the row with your .sof, check the box in the Program/Configure column.
   10. Click Start.
   11. After the software configures the device with the hardware design example, observe the board LEDs:
       • A blinking red LED signifies the design is running.
       • Two green LEDs near the red blinking LED signifies that the HMC link is initialized and the test passed.
       • One red LED near the red blinking LED signifies that the test failed.
   12. Optional. Use the System Console testbench to observe additional test output.
       Note: Use the System Console to monitor status signals in the design example when the board is connected to your computer via the JTAG interface. The System Console shows the board's LED status for remote monitoring, the initialization status for each step, and the status of each port’s request generator and response checker. The System Console also provides an interface to start or re-start the test.
       1. Choose Tools > System Debugging Tools > System Console.
       2. In the System Console, choose File > Execute Script.
       3. Open the file <example_design_install_dir>/example_design/par/sysconsole_testbench.tcl.
       4. The software loads graphical test output. Choose Re-start to run the test again.

Figure 8. System Console Testbench Output

• I²C master and I²C initialization state machine for HMC daughter card and HMC configuration
• ATX PLL and transceiver recalibration state machine
• Request generator
• Request monitor
• System Console interface

• Quartus^® Prime software
• System Console
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL only), or VCS simulator
• Arria 10 GX FPGA Development Kit
• HMC daughter card

You can use the design as an example for correct connection of your IP core to your design, or as a starter design you can customize for your own design requirements. The design example includes an I²C master module, a PLL/CDR recalibration module, one external transceiver PLL IP core, and logic to generate and check transactions. The design example assumes a Micron HMC 15G-SR HMC device, which is a four-link device, on the daughter card. The design example includes one instance of the IP core and connects to a single link on the HMC device.

After you configure the Arria 10 FPGA with the design example, the I²C controller configures the on-board clock generators and the HMC device. When calibration completes, the design example calibrates the ATX PLL. During operation, the request generator generates read and write commands that the HMC Controller IP core then processes. The request monitor captures the responses from the IP core and checks them for correctness.