Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

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UG-01068 | 2020.03.11

Version Information

Updated for:
Intel® Quartus® Prime Design Suite 17.0

1. About Embedded Memory IP Cores

The Intel^® Quartus^® Prime software offers several IP cores to implement memory modes. The available IP cores depend on the target device. You can access the features of the Embedded Memory using the On-Chip Memory IP cores in the Intel^® Quartus^® Prime software.

1.1. Features

Table 1. Memory IP Cores and Their Features
Memory IP	Supported Memory Mode	Features
RAM: 1-PORT	Single-port RAM	Non-simultaneous read and write operations from a single address. Read enable port to specify the behavior of the RAM output ports during a write operation, to overwrite or retain existing value. Supports freeze logic feature.
RAM: 2-PORT	Simple dual-port RAM	Simultaneous one read and one write operations to different locations. Supports error correction code (ECC). Supports freeze logic feature.
RAM: 2-PORT	True dual-port RAM	Simultaneous two reads. Simultaneous two writes. Simulatenous one read and one write at two different clock frequencies. Supports freeze logic feature.
ROM: 1-PORT	Single-port ROM	One port for read-only operations. Initialization using a .mif or .hex file.
ROM: 2-PORT	Dual-port ROM	Two ports for read-only operations. Initialization using a .mif or .hex file.

2. Embedded Memory IP Cores Getting Started

This chapter provides a general overview of the Intel^® FPGA IP core design flow to help you quickly get started with the Embedded Memory IP cores. The Intel^® FPGA IP Library is installed as part of the Intel^® Quartus^® Prime software installation process. You can select and parameterize any Intel^® FPGA IP core from the library. Intel provides an integrated parameter editor that allows you to customize the Embedded Memory IP cores to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports.

2.1. Changing Parameter Settings Manually

When the IP core has been generated using the IP Parameter Editor, you can use this flow to change of the parameter settings within the specified memory mode. However, to change the memory mode, use the IP Parameter Editor to configure and regenerate the IP core.

Follow these steps to change the parameter settings manually:

Locate the Verilog design file: <project directory>/<project name_software version>/synth/<projectName_coreName_QuartusVersion_random>.v.
Change the parameter settings in the design file. Ensure that you use only legal parameter values as specified in Parameters and Signals topic. Failing to do so results in compilation errors.
Compile the design using the Intel^® Quartus^® Prime software.

For example, the following codes enable the ECC feature and specify the initialization file.

altera_syncram_component.enable_ecc = "TRUE",
altera_syncram_component.ecc_pipeline_stage_enabled = "FALSE",
altera_syncram_component.init_file = "mif1.mif",

To disable the ECC feature and specify a different .mif file, make the following changes.

altera_syncram_component.enable_ecc = "FALSE",
altera_syncram_component.ecc_pipeline_stage_enabled = "FALSE",
altera_syncram_component.init_file = "mif2.mif",

2.2. RAM and ROM Parameter Settings

Table 2. Parameters for altera_syncram Use the parameter list when editing the design file manually.
Name	Legal Values	Description
`operation_mode`	SINGLE_PORT DUAL_PORT BIDIR_DUAL_PORT QUAD_PORT ROM	Operation mode of the memory block.
`width_a`	—	Data width of port A.
`widthad_a`	—	Address width of port A.
`widthad2_a`		Address 2 width of port A.
`numwords_a`	—	Number of data words in the memory block for port A.
`outdata_reg_a`	UNREGISTERED CLOCK1 CLOCK0	Clock for the data output registers of port A.
`outdata_aclr_a`	NONE CLEAR1 CLEAR0	Asynchronous clear for data output registers of port A. When the `outdata_reg_a` parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
`outdata_sclr_a`	NONE SCLEAR	Synchronous clear for data output registers of port A. When the `outdata_reg_a` parameter is set to NONE, this parameter specifies the clearing parameter for the output latch.
`address_aclr_a`	NONE CLEAR0	Option to clear the address input registers of port A.
`width_byteena_a`	—	Width of the byte-enable bus of port A. The width must be equal to the value of `width_a` divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
`width_b`	—	Data width of port B.
`widthad_b`	—	Address width of port B.
`widthad2_b`	—	Address 2 width of port B.
`numwords_b`	—	Number of data words in the memory block for port B.
`outdata_reg_b`	UNREGISTERED CLOCK1 CLOCK0	Clock for the data output registers of port B.
`indata_reg_b`	CLOCK1 CLOCK0	Clock for the data input registers of port B.
`address_reg_b`	CLOCK1 CLOCK0	Clock for the address registers of port B.
`byteena_reg_b`	CLOCK1 CLOCK0	Clock for the byte-enable registers of port B.
`outdata_aclr_b`	NONE CLEAR1 CLEAR0	Asynchronous clear for data output registers of port B. When the `outdata_reg_b` parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
`outdata_sclr_b`	NONE SCLEAR	Synchronous clear for data output registers of port B. When the `outdata_reg_b` parameter is set to NONE, this parameter specifies the clearing parameter for the output latch.
`address_aclr_b`	NONE CLEAR0	Option to clear the address input registers of port B.
`width_byteena_b`	—	Width of the byte-enable bus of port B. The width must be equal to the value of `width_b` divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
`intended_device_family`	“Arria 10” “Stratix 10” “Agilex”	Parameter used for simulation purpose.
`ram_block_type`	AUTO M20K MLAB	The memory block type.
`byte_size`	5 8 9 10	The byte size for the byte-enable mode.
`read_during_write_mode_mixed_ports`	DONT_CARE CONSTRAINT_DONT_CARE NEW_DATA OLD_DATA NEW_A_OLD_B	The behavior for the read-during-write mode. The default value is DONT_CARE. The value of NEW_DATA is supported only when the read address and output data are registered by the write clock in the LUTRAM mode. The value of CONSTRAINED_DONT_CARE is supported only in the LUTRAM mode. The value of NEW_A_OLD_B is supported only when the `operation_mode` parameter is set to QUAD_PORT.
`init_file`	`.mif` `.hex`	The initialization file.
`init_file_layout`	PORT_A PORT_B	The layout of the initialization file.
`maximum_depth`	—	The depth of the memory block slices.
`clock_enable_input_a`	NORMAL BYPASS ALTERNATE	The clock enable for the input registers of port A.
`clock_enable_output_a`	NORMAL BYPASS	The clock enable for the output registers of port A.
`clock_enable_core_a`	NORMAL BYPASS ALTERNATE	The clock enable for the core of port A.
`clock_enable_input_b`	NORMAL BYPASS ALTERNATE	The clock enable for the input registers of port B.
`clock_enable_output_b`	NORMAL BYPASS	The clock enable for the output registers of port B.
`clock_enable_core_b`	NORMAL BYPASS ALTERNATE	The clock enable for the core of port A.
`read_during_write_mode_port_a`	NEW_DATA_NO_NBE_READ NEW_DATA_WITH_NBE_READ OLD_DATA DONT_CARE	The read-during-write behavior for port A.
`read_during_write_mode_port_b`	NEW_DATA_NO_NBE_READ NEW_DATA_WITH_NBE_READ OLD_DATA DONT_CARE	The read-during-write behavior for port B.
`enable_ecc`	TRUE FALSE	Enables or disables the ECC feature.
`ecc_pipeline_stage_enabled`	TRUE FALSE	Specifies whether to enable ECC Pipeline Registers before the output decoder to achieve the same performance as non-ECC mode at the expense of one cycle of latency. The parameter `enable_ecc` must set to TRUE if this parameter is set to TRUE. The parameter `outdata_reg_b` cannot set to UNREGISTERED if this parameter is set to TRUE. The default value is FALSE.
`enable_ecc_encoder_bypass`	TRUE FALSE	Enables or disables the ECC Encoder Bypass feature. The parameter `enable_ecc` must set to TRUE if this parameter is set to TRUE.
`enable_coherent_read`	TRUE FALSE	Enables or disables the coherent read feature. The default value is FALSE.
`enable_force_to_zero`	TRUE FALSE	Enables or disables the Force-to-Zero feature. The default value is FALSE.
`width_eccencparity`	8	The width of the `eccencparity` signal.
`optimization_option`	AUTO HIGH_SPEED LOW_POWER	Specifies how the RAM block would be optimized. If AUTO is selected, the fitter determines whether the RAM block is in High_Speed or Low_Power mode. The RAM block type must be M20K when High_Speed or Low_Power is selected.

3. Functional Description

Describes the features and functionality of the embedded memory blocks and the ports of the RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT IP cores.

3.1. Memory Block Types

Intel^® provides various sizes of embedded memory blocks for various devices.

The parameter editor allows you to implement your memory in the following ways:

Select the type of memory blocks available based on your target device. To select the appropriate memory block type for your device, obtain more information about the features of your selected embedded memory block in your target device, such as the maximum performance, supported configurations (depth × width), byte enable, power-up condition, and the write and read operation triggering.
Use logic cells. As compared to embedded memory resources, using logic cells to create memory reduces the design performance and utilizes more area. This implementation is normally used when you have used up all the embedded memory resources. When logic cells are used, the parameter editor provides you with the following two types of logic cell implementations:
- Default logic cell style—the write operation triggers (internally) on the rising edge of the write clock and have continuous read. This implementation uses less logic cells and is faster, but it is not fully compatible with the Stratix^® M512 emulation style.
- Stratix M512 emulation logic cell style—the write operation triggers (internally) on the falling edge of the write clock and performs read only on the rising edge of the read clock.
Select the Auto option, which allows the software to automatically select the appropriate embedded memory resource. When you set the memory block type to Auto, the compiler favors larger block types that can support the memory capacity you require in a single embedded memory block. This setting gives the best performance and requires no logic elements (LEs) for glue logic. When you create the memory with specific embedded memory blocks, such as M9K, the compiler is still able to emulate wider and deeper memories than the block type supported natively. The compiler spans multiple embedded memory blocks (only of the same type) with glue logic added in the LEs as needed.

Note: To obtain proper implementation based on the memory configuration you set, allow the Intel^® Quartus^® Prime software to automatically choose the memory type. This gives the compiler the flexibility to place the memory function in any available memory resources based on the functionality and size.

Table 3. Embedded Memory Blocks in Intel^® FPGA Devices
Device Family	Memory Block Type
Device Family	MLAB (640 bits)	M9K (9 Kbits)	M144K (144 Kbits)	M10K (10 Kbits)	M20K (20 Kbits)	Logic Cell (LC)
Arria^® II GX	Yes	Yes	–	–	–	Yes
Arria^® II GZ	Yes	Yes	Yes	–	–	Yes
Arria^® V	Yes	–	–	Yes	–	Yes
Intel^® Arria^® 10	Yes	–	–	–	Yes	Yes
Cyclone^® IV	–	Yes	–	–	–	Yes
Cyclone^® V	Yes	–	–	Yes	–	Yes
Intel^® Cyclone^® 10 LP	–	Yes	–	–	–	Yes
Intel^® Cyclone^® 10 GX	Yes	–	–	–	Yes	Yes
MAX^® II	–	–	–	–	–	Yes
Intel^® MAX^® 10	–	Yes	–	–	–	Yes
Stratix^® IV	Yes	Yes	Yes	–	–	Yes
Stratix^® V	Yes	–	–	–	Yes	Yes

Note: To identify the type of memory block that the software selects to create your memory, refer to the Fitter report after compilation.

¹ MLAB blocks are not supported in simple dual-port RAM mode with mixed-width port feature, true dual-port RAM mode, and dual-port ROM mode.

3.2. Write and Read Operations Triggering

The embedded memory blocks vary slightly in its supported features and behaviors. One important variation is the difference in the write and read operations triggering.

Table 4. Write and Read Operations Triggering for Embedded Memory BlocksThis table lists the write and read operations triggering for various embedded memory blocks.
Embedded Memory Blocks	Write Operation	Read Operation
M10K	Rising clock edges	Rising clock edges
M20K	Rising clock edges	Rising clock edges
M144K	Rising clock edges	Rising clock edges
M9K	Rising clock edges	Rising clock edges
MLAB	Falling clock edges Rising clock edges (in Intel^® Arria^® 10, Arria^® V, Cyclone^® V, and Stratix^® V devices only)	Rising clock edges ³
M-RAM	Rising clock edges	Rising clock edges
M4K	Falling clock edges	Rising clock edges
M512	Falling clock edges	Rising clock edges

It is important that you understand the write operation triggering to avoid potential write contentions that can result in unknown data storage at that location.

These figures show the valid write operation that triggers at the rising and falling clock edge, respectively.

Figure 1. Valid Write Operation that Triggers at Rising Clock EdgesThis figure assumes that t_wc is the maximum write cycle time interval. Write operation of data 03 through port B does not meet the criteria and causes write contention with the write operation at port A, which result in unknown data at address 01. The write operation at the next rising edge is valid because it meets the criteria and data 04 replaces the unknown data.

Figure 2. Valid Write Operation that Triggers at Falling Clock Edges This figure assumes that t_wc is the maximum write cycle time interval. Write operation of data 04 through port B does not meet the criteria and therefore causes write contention with the write operation at port A that result in unknown data at address 01. The next data (05) is latched at the next rising clock edge that meets the criteria and is written into the memory block at the falling clock edge.

Note: Data and addresses are latched at the rising edge of the write clock regardless of the different write operation triggering.

² Write operation triggering is not applicable to ROMs.

³ MLAB supports continuos reads. For example, when you write a data at the write clock rising edge and after the write operation is complete, you see the written data at the output port without the need for a read clock rising edge.

3.3. Port Width Configurations

The following equation defines the port width configuration: Memory depth (number of words) × Width of the data input bus.

If your port width configuration (either the depth or the width) is more than the amount an internal memory block can support, additional memory blocks (of the same type) are used. For example, if you configure your M9K as 512 × 36, which exceeds the supported port width, two 512 × 18 M9Ks are used to implement your RAM.
In addition to the supported configuration provided, you can set the memory depth to a non-power of two, but the actual memory depth allocated can vary. The variation depends on the type of resource implemented.
If the memory is implemented in dedicated memory blocks, setting a non-power of two for the memory depth reflects the actual memory depth.
When you implement your memory using dedicated memory blocks, refer to the Fitter report to check the actual memory depth.

3.4. Mixed-width Port Configuration

Only dual-port RAM and dual-port ROM support mixed-width port configuration for all memory block types except when they are implemented with LEs. The support for mixed-width port depends on the width ratio between port A and port B. In addition, the supporting ratio varies for various memory modes, memory blocks, and target devices.

Note: MLABs do not have native support for mixed-width operation, thus the option to select MLABs is disabled in the parameter editor. However, the Intel^® Quartus^® Prime software can implement mixed-width memories in MLABs by using more than one MLAB. Therefore, if you select AUTO for your memory block type, it is possible to implement mixed-width port memory using multiple MLABs.

Memory depth of 1 word is not supported in simple dual-port and true dual-port RAMs with mixed-width port. The parameter editor prompts an error message when the memory depth is less than 2 words. For example, if the width for port A is 4 bits and the width for port B is 8 bits, the smallest depth supported by the RAM is 4 words. This configuration results in memory size of 16 bits (4 × 4) and can be represented by memory depth of 2 words for port B. If you set the memory depth to 2 words that results in memory size of 8 bits (2 × 4), it can only be represented by memory depth of 1 word for port B, and therefore the width of the port is not supported.

3.5. Mixed-width Ratio Configuration

Table 5. Supported Mixed-Width Ratio Configurations for Intel^® Arria^® 10
Operation Mode	Mixed-width Ratio
Operation Mode	Without Byte Enable	With Byte Enable
Simple dual-port	1, 2, 4, 8, 16, and 32	1, 2, and 4
True dual-port	1, 2, 4, 8, and 16	1 and 2
Simple quad-port	Not supported	Not supported

3.6. Maximum Block Depth Configuration

You can limit the maximum block depth of the dedicated memory block you use.

The memory block can be sliced to your desired maximum block depth. For example, the capacity of an M9K block is 9,216 bits, and the default memory depth is 8K, in which each address is capable of storing 1 bit (8K × 1). If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 × 18).

You can use this option to save power usage in your devices. However, this parameter might increase the number of LEs and affects the design performance.

When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower slices.

You can also use this option to reduce the total number of memory blocks used (but at the expense of LEs). The 8K × 36 RAM uses 36 M9K RAM blocks with a default slicing of 8K × 1. By setting the maximum block depth to 1K, the 8K × 36 RAM can fit into 32 M9K blocks.

The maximum block depth must be in a power of two, and the valid values vary among different dedicated memory blocks.

Table 6. Valid Range of Maximum Block Depth for Various Embedded Memory Blocks
Embedded Memory Blocks	Valid Range
M10K	256–8K
M20K	512–16K
M144K	2K–16K
M9K	256–8K
MLAB	32–64 ⁵
M512	32–512
M4K	128–4K
M-RAM	4K–64K

The parameter editor prompts an error message if you enter an invalid value for the maximum block depth. Intel^® recommends that you set the value to Auto if you are not sure of the appropriate maximum block depth to set or the setting is not important for your design. This setting enables the compiler to select the maximum block depth with the appropriate port width configuration for the type of embedded memory block of your memory.

⁴ The maximum block depth must be in a power of two.

⁵ The maximum block depth setting (64) for MLAB is not available for Arria^® V and Cyclone^® V devices.

3.7. Clocking Modes and Clock Enable

The embedded memory block supports various types of clocking modes depending on the memory mode you select.

Table 7. Clocking Modes
Clocking Modes	Description
Single Clock Mode	In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory block.
Read/Write Clock Mode	In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address, write-enable, and byte enable registers.
Input/Output Clock Mode	In input/output clock mode, a separate clock is available for each input and output port. An input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
Independent Clock Mode	In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Note: You can create independent clock enable for different input and output registers to control the shut down of a particular register for power saving purposes. From the parameter editor, click More Options (beside the clock enable option) to set the available independent clock enable that you prefer.

Table 8. Clocking ModesThis table lists the embedded memory clocking modes.
Clocking Modes	Single-port RAM	Simple Dual-port RAM	True Dual-port RAM	Single-port ROM	Dual-port ROM
Single clock	Supported	Supported	Supported	Supported	Supported
Read/Write	—	Supported	—	—	—
Input/Output	Supported	Supported	Supported	Supported	Supported
Independent	—	—	Supported	—	Supported

Note: Asynchronous clock mode is only supported in MAX series of devices, and not supported in Stratix and newer devices. However, newer devices support asynchronous read memory for simple dual-port RAM mode if you choose MLAB memory block with unregistered rdaddress port.

Note: The clock enable signals are not supported for write address, byte enable, and data input registers on Arria V, Cyclone V, and Stratix V MLAB blocks.

3.8. Memory Blocks Address Clock Enable Support

The embedded memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled).

Figure 3. Address Clock EnableThis figure shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall.

Figure 4. Address Clock Enable During Read Cycle WaveformThis figure shows the address clock enable waveform during the read cycle.

Figure 5. Address Clock Enable During the Write Cycle WaveformThis figure shows the address clock enable waveform during the write cycle.

3.9. Byte Enable

All embedded memory blocks that are implemented as RAMs support byte enables that mask the input data so that only specific bytes, nibbles, or bits of data are written. The unwritten bytes or bits retain the previously written value.

The LSB of the byte-enable port corresponds to the LSB of the data bus. For example, if you use a RAM block in x18 mode and the byte-enable port is 01, data [8..0] is enabled and data [17..9] is disabled. Similarly, if the byte-enable port is 11, both data bytes are enabled.

You can specifically define and set the size of a byte for the byte-enable port. The valid values are 5, 8, 9, and 10, depending on the type of embedded memory blocks. The values of 5 and 10 are only supported by MLAB. To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores.

Note: To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores.

To create a byte-enable port, the width of the data input port must be a multiple of the size of a byte for the byte-enable port. For example, if you use an MLAB memory block, the byte enable is only supported if your data bits are multiples of 5, 8, 9 or 10, that is 10, 15, 16, 18, 20, 24, 25, 27, 30, and so on. If the width of the data input port is 10, you can only define the size of a byte as 5. In this case, you get a 2-bit byte-enable port, each bit controls 5 bits of data input written. If the width of the data input port is 20, then you can define the size of a byte as either 5 or 10. If you define 5 bits of input data as a byte, you get a 4-bit byte-enable port, each bit controls 5 bits of data input written. If you define 10 bits of input data as a byte, you get a 2-bit byte-enable port, each bit controls 10 bits of data input written.

Figure 6. Byte Enable Functional WaveformThis figure shows the results of the byte enable on the data that is written into the memory, and the data that is read from the memory.

When a byte-enable bit is deasserted during a write cycle, the corresponding masked byte of the q output can appear as a “Don't Care” value or the current data at that location. This selection is only available if you set the read-during-write output behavior to New Data.

3.10. Asynchronous Clear

The embedded memory blocks in the Arria II GX, Arria II GZ, Stratix IV, Stratix V, and newer device families support the asynchronous clear feature used on the output latches and output registers. Therefore, if your RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear. The asynchronous clear feature allows you to clear the outputs even if the q output port is not registered. However, this feature is not supported in MLAB memory blocks.

The outputs stay cleared until the next clock. However, in Arria V, Cyclone V, and Stratix V devices, the outputs stay cleared until the next read.

Note: You cannot use the asynchronous clear port to clear the contents of the embedded memory. Use the asynchronous clear port to clear the contents of the input and output register stages only.

Table 9. Asynchronous Clear Effects on the Input Ports for Various Devices in Various Memory SettingsThis table lists the asynchronous clear effects on the input ports for various devices in various memory settings.
Memory Mode	Arria II GX, Arria II GZ, Arria V, Cyclone V, Stratix IV, Stratix V, and newer devices
Single-port RAM	All registered input ports are not affected. ⁶
Single dual-port RAM and True dual-port RAM	Only registered input read address port can be affected.
Single-port ROM	Registered input address port can be affected.
Dual-port ROM	All registered input ports are not affected.

Note: During a read operation, clearing the input read address asynchronously corrupts the memory contents. The same effect applies to a write operation if the write address is cleared.

Note: Beginning from Arria V, Cyclone V, and Stratix V devices onwards, an output clock signal is needed to successfully recover the output latch from an asynchronous clear signal. This implies that in a single clock mode true dual-port RAM, setting clock enabled on the registered output may affect the recovery of the unregistered output because they share the same output clock signal. To avoid this, provide an output clock signal (with clock enabled) to the output latch to deassert an asynchronous clear signal from the output latch.

⁶ When LCs are implemented in this memory mode, registered output port is not affected.

3.11. Read Enable

Support for the read enable feature depends on the target device, memory block type, and the memory mode you select.

Table 10. Read-Enable Support in Various Device FamiliesThis table lists the memory configurations for various device families that support the read enable feature.
Memory Modes	M9K, M144K, M10K, M20K	MLAB
Single-port RAM	Supported	—
Simple dual-port RAM	Supported	—
True dual-port RAM	Supported	—
Tri-port RAM	Supported	—
Single-port ROM	Supported	—
Dual-port ROM	Supported	—

If you create the read-enable port and perform a write operation (with the read enable port deasserted), the data output port retains the previous values that are held during the most recent active read enable. If you activate the read enable during a write operation, or if you do not create a read-enable signal, the output port shows the new data being written, the old data at that address, or a “Don't Care” value when read-during-write occurs at the same address location.

3.12. Read-During-Write

The read-during-write (RDW) occurs when a read and a write target the same memory location at the same time.

Table 11. RDW OperationThis table lists the RDW operations.
RDW Operation	Description
Same-Port RDW	The same-port RDW occurs when the input and output of the same port access the same address location with the same clock. The same-port RDW has the following output choices: New Data—New data is available on the rising edge of the same clock cycle on which it was written. Old Data—The RAM outputs reflect the old data at that address before the write operation proceeds. Old Data is not supported for M10K and M20K memory blocks in single-port RAM and true dual-port RAM. Don't Care—The RAM outputs “don't care” values for the RDW operation.
Mixed-Port RDW	The mixed-port RDW occurs when one port reads and another port writes to the same address location with the same clock. The mixed-port RDW has the following output choices: Old Data—The RAM outputs reflect the old data at that address before the write operation proceeds. Old Data is supported for single clock configuration only. Don't Care—The RAM outputs “don't care” or “unknown” values for RDW operation without analyzing the timing path. For LUTRAM, this option functions differently whereby when you enable this option, the RAM outputs “don’t care” or “unknown” values for RDW operation but analyzes the timing path to prevent metastability. Therefore, if you want the RAM to output “don’t care” values without analyzing the timing path, you have to turn on the Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time option.

3.12.1. Selecting RDW Output Choices for Various Memory Blocks

The available output choices for the RDW behavior vary, depending on the types of RDW and embedded memory block in use.

Table 12. Output Choices for the Same-Port and Mixed-Port Read-During-WriteThis table lists the available output choices for the same-port, and mixed-port RDW for various embedded memory blocks.
Memory Block Types	Single-port RAM ⁷	Simple dual-port RAM ⁸	True dual-port RAM
Memory Block Types	Same port RDW	Mixed-port RDW	Same port RDW ⁹	Mixed-port RDW ¹⁰
M512	No parameter editor ¹¹	Old Data Don’t Care	N/A
M4K		Old Data Don’t Care	No parameter editor ¹¹	Old Data Don’t Care
M-RAM		Don’t Care	No parameter editor ¹¹	Don’t Care
MLAB	Don’t Care New Data ¹²	New Data ¹³ Old Data Don’t Care	N/A MLAB is not supported in true dual-port RAM
M9K	Don’t Care New Data ¹⁴ Old Data	Old Data Don’t Care	New Data ¹⁴ Old Data	Old Data Don’t Care
M144K	Don’t Care New Data ¹⁴ Old Data	Old Data Don’t Care	New Data ¹²	Old Data Don’t Care
M10K	Don’t Care New Data ¹²	Old Data Don’t Care	New Data ¹²	Old Data Don’t Care
M20K	Old Data Don’t Care	Old Data Don’t Care	New Data ¹²	Old Data Don’t Care
LCs	No parameter editor ¹¹	Old Data Don’t Care	N/A

Note: The RDW old data mode is not supported when the Error Correction Code (ECC) is engaged.

Note: If you are not concerned about the output when RDW occurs and would like to improve performance, you can select Don't Care. Selecting Don't Care increases the flexibility in the type of memory block being used, provided you do not assign block type when you instantiate the memory block.

⁷ Single-port RAM only supports same-port RDW, and the clocking mode must be either single clock mode, or input/output clock mode.

⁸ Simple dual-port RAM only supports mixed-port RDW, and the clocking mode must be either single clock mode, or input/output clock mode.

⁹ The clocking mode must be either single clock mode, input/output clock mode, or independent clock mode.

¹⁰ The clocking mode must be either single clock mode, or input/output clock mode.

¹¹ There is no option page available from the parameter editor in this mode. By default, the new data flows through to the output.

¹² The new data behavior for same-port RDW support NEW_DATA_NO_NBE_READ for x on masked byte only when the byte enable applies.

¹³ Only supported in single clock mode with new data behavior of NEW_DATA_NO_NBE_READ.

¹⁴ There are two types of new data behavior for same-port RDW that you can choose from the parameter editor. When byte enable is applied, you can choose to read old data, or ‘X’ on the masked byte. The respective parameter values are:

NEW_DATA_WITH_NBE_READ for old data on masked byte.
NEW_DATA_NO_NBE_READ for x on masked byte.

3.13. Power-Up Conditions and Memory Initialization

Power-up conditions depend on the type of embedded memory blocks in use and whether or not the output port is registered.

Table 13. Power-Up Conditions for Various Embedded Memory BlocksThis table lists the power-up conditions in the various types of embedded memory blocks.
Embedded Memory Blocks	Power-Up Conditions
M512	Outputs cleared
M4K	Outputs cleared
M-RAM	Outputs cleared if registered, otherwise unknown
MLAB	Outputs cleared if registered, otherwise reads memory contents
M9K	Outputs cleared
M144K	Outputs cleared
M10K	Outputs cleared
M20K	Outputs cleared

The outputs of M512, M4K, M9K, M144K, M10K, and M20K blocks always power-up to zero, regardless of whether the output registers are used or bypassed. Even if a memory initialization file is used to pre-load the contents of the memory block, the output is still cleared.

MLAB and M-RAM blocks power-up to zero only if output registers are used. If output registers are not used, MLAB blocks power-up to read the memory contents while M-RAM blocks power-up to an unknown state.

Note: When the memory block type is set to Auto in the parameter editor, the compiler is free to choose any memory block type, in which the power-up value depends on the chosen memory block type. To identify the type of memory block the software selects to implement your memory, refer to the fitter report after compilation.

All memory blocks (excluding M-RAM) support memory initialization via the Memory Initialization File (.mif) or Hexadecimal ( Intel^® -format) file (.hex). You can include the files using the parameter editor when you configure and build your RAM. For RAM, besides using the .mif file or the .hex file, you can initialize the memory to zero or ‘X’. To initialize the memory to zero, select No, leave it blank. To initialize the content to ‘X’, turn on Initialize memory content data to XX..X on power-up in simulation. Turning on this option does not change the power-up behavior of the RAM but initializes the content to ‘X’. For example, if your target memory block is M4K, the output is cleared during power-up (based on Table 13). The content that is initialized to ‘X’ is shown only when you perform the read operation.

Note: The Intel^® Quartus^® Prime software searches for the altsyncram init_file in the project directory, the project db directory, user libraries, and the current source file location.

3.14. Error Correction Code

The error correction code (ECC) feature detects and corrects output data errors. You have the option to use pipeline registers to improve performance. The ECC feature is supported only in the following conditions:

Memory blocks and not MLABs or logic cells
Simple dual-port mode
Same-width ports
Byte-enable feature is disabled

Note: When the ECC feature is enabled, the result of a RDW in a mixed-port configuration is always Don't care.

Note: The simulation model does not support the ECC feature for Intel^® Arria^® 10 devices.

Table 14. ECC Features in Memory Blocks
Memory Block	Supported Port Width	Single Error	Double Adjacent Error	Triple Adjacent Error
M144K	Up to 64 bits	Detection and correction	Detection only	–
M20K	Up to 32 bits	Detection and correction	Detection and correction	Detection only
M20K ( Intel^® Arria^® 10)	More than 32 bits—achieved by stitching 32-bit M20K blocks together.	Detection and correction	Detection and correction	Detection only

Table 15. Error StatusThe IP uses the `eccstatus` signal to indicate the status of the error detection and correction.
M144K eccstatus[2..0]	M20K eccstatus[1..0]	Description
000	00	No error.
011	–	Single error was detected and corrected.
101	–	Double error was detected.
001	01	Illegal status.
010	01	Illegal status.
100	01	Illegal status.
11X	01	Illegal status.
–	10	An error was detected and corrected. However, the memory array is not updated.
–	11	An error was detected but not corrected in the output data.

3.15. Freeze Logic

The freeze logic feature specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.

This feature is applicable only to the RAM modes:

Single-port RAM
Dual-port RAM

You have the option to turn on Implement clock-enable circuitry for use in a partial reconfiguration to enable the freeze logic feature in the parameter editors of the RAM/ROM IP cores.

4. Embedded Memory Design Consideration

4.1. Avoid Providing Non-Deterministic Input

When running the embedded memory simulation model, you must ensure that you do not provide “X” or dont_care as inputs to the simulation model. Providing “X” or don’t_care may result in unexpected behavior in simulation.

5. Parameters and Signals

5.1. RAM: 1-Port IP Core Parameters

Table 16. RAM: 1-Port IP Core Parameters Description
Parameter		Legal Values	Description
Parameter Settings: Widths/Blk Type/Clks
How wide should the ‘q’ output bus be?		—	Specifies the width of the ‘q’ output bus.
How many <X>-bit words of memory?		—	Specifies the number of <X>-bit words.
What should the memory block type be?		Auto, M-RAM, M4K, M512, M9K, M10K, M144K, MLAB, M20K, LCs	Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to		Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192,16384, 32768, 65536	Specifies the maximum block depth in words.
What clocking method would you like to use?		Single clock Dual clock: use separate ‘input’ and ‘output’ clocks	Specifies the clocking method to use. Single clock—A single clock and a clock enable controls all registers of the memory block. Dual clock: use separate ‘input’ and ‘output’ clocks—An input and an output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables.
Parameter Settings: Regs/Clken/Byte Enable/Aclrs
Which ports should be registered? The following options are available: ‘data’ and ‘wren’ input ports ‘address’ input port ‘q’ output port		On/Off	Specifies whether to register the input and output ports.
Create one clock enable signal for each clock signal. Note: All registered ports are controlled by the enable signal(s)		On/Off	Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Options	Use clock enable for port A input registers	On/Off	Specifies whether to use clock enable for port A input registers.
	Use clock enable for port A output registers	On/Off	Specifies whether to use clock enable for port A output registers.
	Create an ‘addressstall_a’ input port.	On/Off	Specifies whether to create a addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers.
Create byte enable for port A		On/Off	Specifies whether to create a byte enable for port A. Turn on this option if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written. To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores.
What is the width of a byte for byte enables?		MLAB: 5 or 10 Other memory block types: 8 or 9 M10K and M20K: 8, 9, or 10	Specifies the byte width of the byte enable port. The width of the data input port must be divisible by the byte size.
Create an ‘aclr’ asynchronous clear for the registered ports.		On/Off	Specifies whether to create an asynchronous clear port for the registered data, wren, address, q, and byteena_a ports.
More Options	‘q’ port	On/Off	Turn on this option for the ‘q’ port to be affected by the asynchronous clear signal. The disabled ports are not affected by the asynchronous clear signal.
Create a ‘rden’ read enable signal		On/Off	Specifies whether to create a read enable signal.
Parameter Settings: Read During Write Option
What should the q output be when reading from a memory location being written to?		New data, Don’t Care	Specifies the output behavior when read-during-write occurs. New Data—New data is available on the rising edge of the same clock cycle on which it was written. Don’t Care—The RAM outputs “don't care” or “unknown” values for read-during-write operation.
Get x’s for write masked bytes instead of old data when byte enable is used		On/Off	Turn on this option to obtain ‘X’ on the masked byte. For M10K and M20K memory block, this option is not available if you specify New Data as the output behavior when RDW occurs.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?		No, leave it blank Yes, use this file for the memory content data	Specifies the initial content of the memory. To initialize the memory to zero, select No, leave it blank. To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data.
Enable Partial Reconfiguration Initialization Mode		On/Off	Initializes a clock enable circuit in the same PR region as the RAM.
Allow In-System Memory Content Editor to capture and update content independently of the system clock		On/Off	Specifies whether to allow In-System Memory Content Editor to capture and update content independently of the system clock.
The ‘Instance ID’ of this RAM is		None	Specifies the RAM ID.
Implement clock-enable circuitry for use in a partial reconfiguration region		On/Off	Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.

5.2. RAM: 2-Port IP Core Parameters

This table lists the parameters for the RAM: 2-Port IP Core

Table 17. RAM: 2-Port Parameter Settings
Parameter		Legal Values	Description
Parameter Settings: General
How will you be using the dual port RAM?		With one read port and one write port With two read /write ports	Specifies how you use the dual port RAM.
How do you want to specify the memory size?		As a number of words As a number of bits	Determines whether to specify the memory size in words or bits.
Parameter Settings: Widths/ Blk Type
How many <X>-bit words of memory?		—	Specifies the number of <X>-bit words.
Use different data widths on different ports		On/Off	Specifies whether to use different data widths on different ports.
When you select With one read port and one write port, the following options are available: How wide should the ‘q_a’ output bus be? How wide should the ‘data_a’ input bus be? How wide should the ‘q’ output bus be?		—	Specifies the width of the input and output ports.
When you select With two read/write ports, the following options are available: How wide should the ‘q_a’ output bus be? How wide should the ‘q_b’ output bus be?		—	Specifies the width of the input and output ports.
What should the memory block type be?		Auto, M-RAM, M4K, M512, M9K, M10K, M144K, MLAB, M20K, LCs	Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
How should the memory be implemented?		Use default logic cell style Use Stratix M512 emulation logic cell style	Specifies the logic cell implementation options. This option is enabled only when you choose LCs memory type.
Set the maximum block depth to		Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096	Specifies the maximum block depth in words. This option is enabled only when you set the memory block type to Auto.
Parameter Settings: Clks/Rd, Byte En
What clocking method would you like to use?		When you select With one read port and one write port, the following values are available: Single clock Dual clock: use separate ‘input’ and ‘output’ clocks Dual clock: use separate ‘read’ and ‘write’ clock When you select With two read/write ports, the following options are available: Single clock Dual clock: use separate ‘input’ and ‘output’ clocks Dual clock: use separate clocks for A and B ports	Specifies the clocking method to use. Single clock—A single clock and a clock enable controls all registers of the memory block. Dual Clock: use separate ‘input’ and ‘output’ clocks—An input and an output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables. Dual clock: use separate ‘read’ and ‘write’ clock—A write clock controls the data-input, write-address, and write-enable registers while the read clock controls the data-output, read-address, and read-enable registers. Dual clock: use separate clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
When you select With one read port and one write port, the following option is available: Create a ‘rden’ read enable signal		—	Specifies whether to create a read enable signal for port B.
When you select With two read/write ports, the following option is available: Create a ‘rden_a’ and ‘rden_b’ read enable signal		—	Specifies whether to create a read enable signal for port A and B.
Create byte enable for port A		—	Specifies whether to create a byte enable for port A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written. To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores. The option to create a byte enable for port B is only available when you select the With two read/write ports option.
Create byte enable for port B		—
Enable error checking and correcting (ECC) to check and correct single bit errors and detect double errors		On/Off	Specifies whether to enable the ECC feature that corrects single bit errors and detects double errors at the output of the memory. This option is only available in devices that support M144K memory block type.
Enable error checking and correcting (ECC) to check and correct single bit errors, double adjacent bit errors, and detect triple adjacent bit errors		On/Off	Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory. This option is only available in devices that support M20K memory block type.
Parameter Settings: Regs/Clkens/Aclrs
Which ports should be registered? When you select With one read port and one write port, the following options are available: ‘data’, ‘wraddress’, and ‘wren’ write input ports ‘raddress’ and ‘rden’ read input port Read output port(s) ‘q’ When you select With two read/write ports, the following options are available: ‘data_a’, ‘wraddress_a’, and ‘wren_a’ write input ports Read output port(s) ‘q’_a and ‘q_b’		On/Off	Specifies whether to register the read or write input and output ports.
More Options	When you select With one read port and one write port, the following options are available: ‘data’ port ‘wraddress’ port ‘wren’ port ‘raddress’ port ‘q_b’ port When you select With two read /write ports, the following options are available: ‘data_a’ port ‘data_b’ port ‘wraddress_a’ port ‘wraddress_b’ port ‘wren_a’ port ‘wren_b’ port ‘q_a’ port ‘q_b’ port	On/Off	The read and write input ports are turned on by default. You only need to specify whether to register the Q output ports.
Create one clock enable signal for each clock signal.		On/Off	Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Options	When you select With one read port and one write port, the following option is available: Use clock enable for write input registers When you select With two read /write ports, the following options are available: Use clock enable for port A input registers Use clock enable for port B input registers Use clock enable for port A output registers Use clock enable for port B output register	On/Off	Clock enable for port B input and output registers are turned on by default. You only need to specify whether to use clock enable for port A input and output registers.
More Options	When you select With one read port and one write port, the following options are available: Create an ‘wr_addressstall’ input port. Create an ‘rd_addressstall’ input port. When you select With two read /write ports, the following options are available: Create an ‘addressstall_a’ input port. Create an ‘addressstall_b’ input port.	On/Off	Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.
Create an ‘aclr’ asynchronous clear for the registered ports.		On/Off	Specifies whether to create an asynchronous clear port for the registered ports.
More Options	When you select With one read port and one write port, the following options are available: ‘q_b’ port ‘rdaddress’ port When you select With two read /write ports, the following options are available: ‘q_a’ port ‘q_b’ port	On/Off	Specifies whether the ‘raddress’, ‘q_a’, and ‘q_b’ ports are cleared by the aclr port.
Parameter Settings: Output 1
When you select With one read port and one write port, the following option is available: How should the q output behave when reading a memory location that is being written from the other port? When you select With two read /write ports, the following option is available: How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port?		Old memory contents appear I do not care	Specifies the output behavior when read-during-write occurs. Old memory contents appear— The RAM outputs reflect the old data at that address before the write operation proceeds. I do not care—This option functions differently when you turn it on depending on the following memory block type you select: When you set the memory block type to Auto, M144K, M512, M4K, M9K, M10K, M20K or any other block RAM, the RAM outputs ‘don't care’ or “unknown” values for read-during-write operation without analyzing the timing path. When you set the memory block type to MLAB (for LUTRAM), the RAM outputs ‘dont care’ or ‘unknown’ values for read-during-write operation but analyzes the timing path to prevent metastability.
Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time.		On/Off	Turn on this option when you want the RAM to output ‘don’t care’ or unknown values for read-during-write operation without analyzing the timing path. This option is only available for LUTRAM and is enabled when you set memory block type to MLAB.
Parameter Settings: Output 2 (This tab is only available when you select two read/ write ports)
What should the ‘q_a’ output be when reading from a memory location being written to?		New data Old Data	Specifies the output behavior when read-during-write occurs. New Data—New data is available on the rising edge of the same clock cycle on which it was written. Old Data—The RAM outputs reflect the old data at that address before the write operation proceeds.
What should the ‘q_b’ output be when reading from a memory location being written to?		New data Old Data
Get x’s for write masked bytes instead of old data when byte enable is used		On/Off	Turn on this option to obtain ‘X’ on the masked byte.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?		No, leave it blank Yes, use this file for the memory content data	Specifies the initial content of the memory. To initialize the memory to zero, select No, leave it blank. To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data.
Enable Partial Reconfiguration Initialization Mode		On/Off	Initializes a clock enable circuit in the same PR region as the RAM.
Implement clock-enable circuitry for use in a partial reconfiguration region		On/Off	Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.

5.3. ROM: 1-PORT IP Core Parameters

This table lists the parameters for the ROM: 1-PORT IP Core.

Table 18. ROM: 1-PORT IP Core Parameters
Parameter		Legal Values	Description
Parameter Settings: General Page
How wide should the ‘q’ output bus be?		—	Specifies the width of the ‘q’ output bus.
How many <X>-bit words of memory?		—	Specifies the number of <X>-bit words.
What should the memory block type be?		Auto, M4K, M9K, M144K, M10K, M20K	Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to		Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096	Specifies the maximum block depth in words.
What clocking method would you like to use?		Single clock Dual clock: use separate ‘input’ and ‘output’ clocks	Specifies the clocking method to use. Single clock—A single clock and a clock enable controls all registers of the memory block Dual clock (Input and Output clock)—The input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode.
Parameter Settings: Regs/Clken/Aclrs
Which ports should be registered? ‘q’ output port		On/Off	Specifies whether to register the ‘q’ output port.
Create one clock enable signal for each clock signal. Note: All registered ports are controlled by the enable signal(s)		On/Off	Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Options	Use clock enable for port A input registers	On/Off	Specifies whether to use clock enable for port A input registers.
	Use clock enable for port A output registers	On/Off	Specifies whether to use clock enable for port A output registers.
	Create an ‘addressstall_a’ input port.	On/Off	Specifies whether to create a addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers.
Create an ‘aclr’ asynchronous clear for the registered ports.		On/Off	Specifies whether to create an asynchronous clear port for the registered ports.
More Options	‘address’ port	On/Off	Specifies whether the ‘address’ port should be affected by the ‘aclr’ port.
More Options	‘q’ port	On/Off	Specifies whether the ‘q’ port should be affected by the ‘aclr’ port.
Create a ‘rden’ read enable signal		On/Off	Specifies whether to create a read enable signal.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?		Yes, use this file for the memory content data	Specifies the initial content of the memory. In ROM mode you must specify a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex). The Yes, use this file for the memory content data option is turned on by default.
Allow In-System Memory Content Editor to capture and update content independently of the system clock		On/Off	Specifies whether to allow In-System Memory Content Editor to capture and update content independently of the system clock
The ‘Instance ID’ of this ROM is		—	Specifies the ROM ID.

5.4. ROM: 2-PORT IP Core Parameters

This table lists the ROM: 2-PORT IP Core parameters.

Table 19. ROM: 2-PORT IP Core Parameters
Parameter		Legal Values	Description
Parameter Settings: Widths/Blk Type
How do you want to specify the memory size?		As a number of words As a number of bits	Determines whether to specify the memory size in words or bits.
How many <X>-bit words of memory?		32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536	Specifies the number of <X>-bit words.
Use different data widths on different ports		On/Off	Specifies whether to use different data widths on different ports.
How wide should the ‘q_a’ output bus be?		—	Specifies the width of the ‘q_a’ and ‘q_b’ output ports.
How wide should the ‘q_b’ output bus be?		—	Specifies the width of the ‘q_a’ and ‘q_b’ output ports.
What should the memory block type be?		Auto, M4K, M9K, M144K, M10K, M20K	Specifies the memory block type. The types of memory block that are available for selection depends on your target device
Set the maximum block depth to		Auto, 128, 256, 512, 1024, 2048, 4096	Specifies the maximum block depth in words. This option is enabled only when you choose Auto as the memory block type.
Parameter Settings: Clks/Rd, Byte En
What clocking method would you like to use?		Single clock Dual clock: use separate ‘input’ and ‘output’ clocks Dual clock: use separate clocks for A and B ports	Specifies the clocking method to use. Single clock—A single clock and a clock enable controls all registers of the memory block Dual clock: use separate ‘input’ and ‘output’ clocks—The input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode. Dual clock: use separate clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
Create a ‘rden_a’ and ‘rden_b’ read enable signals		—	Specifies whether to create read enable signals.
Parameter Settings: Regs/Clkens/Aclrs
Read output port(s) ‘q_a’ and ‘q_b’		On/Off	Specifies whether to register the ‘q_a’ and ‘q_b’ output ports.
More Options	‘q_a’ port	On/Off	Specifies whether to register the ‘q_a’ output port.
More Options	‘q_b’ port	On/Off	Specifies whether to register the ‘q_b’ output port.
Create one clock enable signal for each clock signal.		On/Off	Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Options	Use clock enable for port A input registers	On/Off	Specifies whether to use clock enable for port A input registers.
	Use clock enable for port A output registers	On/Off	Specifies whether to use clock enable for port A output registers.
	Create an ‘addressstall_a’ input port.	On/Off	Specifies whether to create addressstall_a and addressstall_b input ports. You can create these ports to act as an extra active low clock enable input for the address registers.
	Create an ‘addressstall_b’ input port.	On/Off	Specifies whether to create an asynchronous clear port for the registered ports.
Create an ‘aclr’ asynchronous clear for the registered ports.		On/Off	Specifies whether to create an asynchronous clear port for the registered ports.
More Options	‘q_a’ port	On/Off	Specifies whether the ‘q_a’ port should be cleared by the aclr port.
More Options	‘q_b’ port	On/Off	Specifies whether the ‘q_b’ port should be cleared by the aclr port.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?		Yes, use this file for the memory content data	Specifies the initial content of the memory. In ROM mode you must specify a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex). The Yes, use this file for the memory content data option is turned on by default.
The initial content file should conform to which port’s dimensions?		PORT_A PORT_B	Specifies whether the initial content file conforms to port A or port B.

5.5. Signals

Table 20. Interface Signals of the Embedded Memory IP Cores
Signal	Type	Required	Description
`data_a`	Input	Optional	Data input to port A of the memory. The `data_a` port is required if you set the operation_mode parameter to any of the following values: `SINGLE_PORT` `DUAL_PORT` `BIDIR_DUAL_PORT`
`address_a`	Input	Yes	Address input to port A of the memory. The `address_a` signal is required for all operation modes.
`wren_a`	Input	Optional	Write enable input for address_a port. The `wren_a` signal is required if you set the operation_mode to any of the following values: SINGLE_PORT DUAL_PORT BIDIR_DUAL_PORT
`rden_a`	Input	Optional	Read enable input for `address_a` port. The `rden_a` signal is supported depending on your selected memory mode and memory block.
`byteena_a`	Input	Optional	Byte enable input to mask the `data_a` port so that only specific bytes, nibbles, or bits of the data are written. The `byteena_a` port is not supported in the following conditions: If `implement_in_les` parameter is set to ON If `operation_mode` parameter is set to ROM
`addressstall_a`	Input	Optional	Address clock enable input to hold the previous address of address_a port for as long as the addressstall_a port is high.
`q_a`	Output	Yes	Data output from port A of the memory. The `q_a` port is required if the `operation_mode` parameter is set to any of the following values: `SINGLE_PORT` `BIDIR_DUAL_PORT` `ROM` The width of `q_a` port must be equal to the width of `data_a` port.
`data_b`	Input	Optional	Data input to port B of the memory. The `data_b` port is required if the `operation_mode` parameter is set to `BIDIR_DUAL_PORT`.
`address_b`	Input	Optional	Address input to port B of the memory. The `address_b` port is required if the `operation_mode` parameter is set to the following values: `DUAL_PORT` `BIDIR_DUAL_PORT`
`wren_b`	Input	Yes	Write enable input for `address_b` port. The `wren_b` port is required if `operation_mode` is set to `BIDIR_DUAL_PORT`.
`rden_b`	Input	Optional	Read enable input for `address_b` port. The `rden_b` port is supported depending on your selected memory mode and memory block
`byteena_b`	Input	Optional	Byte enable input to mask the `data_b` port so that only specific bytes, nibbles, or bits of the data are written. The `byteena_b` port is not supported in the following conditions: If `implement_in_les parameter` is set to `ON` If `operation_mode parameter` is set to `SINGLE_PORT`, `DUAL_PORT`, or `ROM`
`addressstall_b`	Input	Optional	Address clock enable input to hold the previous address of `address_b` port for as long as the `addressstall_b` port is high.
`q_b`	Output	Yes	Data output from port B of the memory. The `q_b` port is required if the `operation_mode` is set to the following values: `DUAL_PORT` `BIDIR_DUAL_PORT` The width of `q_b` port must be equal to the width of `data_b` port.
`clock0`	Input	Yes	The following describes which of your memory clock must be connected to the `clock0` port, and port synchronization in different clocking modes: Single clock: Connect your single source clock to `clock0` port. All registered ports are synchronized by the same source clock. Read/Write: Connect your write clock to `clock0` port. All registered ports related to write operation, such as `data_a` port, `address_a` port, `wren_a` port, and `byteena_a` port are synchronized by the write clock. Input Output: Connect your input clock to `clock0` port. All registered input ports are synchronized by the input clock. Independent clock: Connect your port A clock to `clock0` port. All registered input and output ports of port A are synchronized by the port A clock.
`clock1`	Input	Optional	The following describes which of your memory clock must be connected to the `clock1` port, and port synchronization in different clocking modes: Single clock: Not applicable. All registered ports are synchronized by `clock0` port. Read/Write: Connect your read clock to `clock1` port. All registered ports related to read operation, such as `address_b` port, `rden_b` port, and `q_b` port are synchronized by the read clock. Input Output: Connect your output clock to `clock1` port. All the registered output ports are synchronized by the output clock. Independent clock: Connect your port B clock to `clock1` port. All registered input and output ports of port B are synchronized by the port B clock.
`clocken0`	Input	Optional	Clock enable input for `clock0` port.
`clocken1`	Input	Optional	Clock enable input for `clock1` port.
`clocken2`	Input	Optional	Clock enable input for `clock0` port.
`clocken3`	Input	Optional	Clock enable input for `clock1` port.
`aclr0` `aclr1`	Input	Optional	Asynchronously clear the registered input and output ports. The `aclr0` port affects the registered ports that are clocked by `clock0` clock, while the `aclr1` port affects the registered ports that are clocked by `clock1` clock. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as `outdata_aclr_a`,`address_aclr_a`, and so on.
`eccstatus`	Output	Optional	A 3-bit wide error correction status port. Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs. In Stratix V devices, the M20K ECC status is communicated with two-bit wide error correction status port. The M20K ECC detects and fixes a single bit error event or a double adjacent error event, or detects three adjacent errors without fixing the errors. The `eccstatus` port is supported if all the following conditions are met: `operation_mode` parameter is set to `DUAL_PORT` `ram_block_type` parameter is set to `M144K` or `M20K` `width_a` and `width_b` parameter have the same value Byte enable is not used
`data`	Input	Yes	Data input to the memory. The data port is required and the width must be equal to the width of the `q` port.
`wraddress`	Input	Yes	Write address input to the memory. The `wraddress` port is required and must be equal to the width of the `raddress` port.
`wren`	Input	Yes	Write enable input for `wraddress` port. The `wren` port is required.
`rdaddress`	Input	Yes	Read address input to the memory. The `rdaddress` port is required and must be equal to the width of `wraddress` port.
`rden`	Input	Optional	Read enable input for `rdaddress` port. The `rden` port is supported when the `use_eab` parameter is set to `OFF`. The `rden` port is not supported when the `ram_block_type` parameter is set to `MLAB`. Instantiate the ALTSYNCRAM IP core if you want to use read enable feature with other memory blocks.
`byteena`	Input	Optional	Byte enable input to mask the data port so that only specific bytes, nibbles, or bits of data are written. The `byteena` port is not supported when `use_eab` parameter is set to `OFF`. It is supported in Arria II GX and newer devices with the `ram_block_type` parameter set to MLAB.
`wraddressstall`	Input	Optional	Write address clock enable input to hold the previous write address of `wraddress` port for as long as the `wraddressstall` port is high.
`rdaddressstall`	Input	Optional	Read address clock enable input to hold the previous read address of `rdaddress` port for as long as the `wraddressstall` port is high. The `rdaddressstall` port is only supported in newer devices except when the `rdaddress_reg` parameter is set to `UNREGISTERED.`
`q`	Output	Yes	Data output from the memory. The `q` port is required, and must be equal to the width data port.
`inclock`	Input	Yes	The following describes which of your memory clock must be connected to the `inclock` port, and port synchronization in different clocking modes: Single clock: Connect your single source clock to `inclock` port and `outclock` port. All registered ports are synchronized by the same source clock. Read/Write: Connect your write clock to `inclock` port. All registered ports related to write operation, such as `data` port, `wraddress` port, `wren` port, and `byteena` port are synchronized by the write clock. Input/Output: Connect your input clock to `inclock` port. All registered input ports are synchronized by the input clock.
`outclock`	Input	Yes	The following describes which of your memory clock must be connected to the `outclock` port, and port synchronization in different clocking modes: Single clock: Connect your single source clock to `inclock` port and `outclock` port. All registered ports are synchronized by the same source clock. Read/Write: Connect your read clock to `outclock` port. All registered ports related to read operation, such as `rdaddress` port, `rdren` port, and `q` port are synchronized by the read clock. Input/Output: Connect your output clock to `outclock` port. The registered `q` port is synchronized by the output clock.
`inclocken`	Input	Optional	Clock enable input for `inclock` port.
`outclocken`	Input	Optional	Clock enable input for `outclock` port.
`aclr`	Input	Optional	Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as `indata_aclr`, `wraddress_aclr`, and so on.

Note: When running the embedded memory simulation model, you must ensure that you do not provide “X” or dont_care as inputs to the simulation model. Providing “X” or don’t_care may result in unexpected behavior in simulation.

6. Design Example

Simulate the designs using the ModelSim* - Intel^® FPGA Edition software to generate a waveform display of the device behavior.

The following design files in Internal_Memory_DesignExample.zip:

ecc_encoder.v
ecc_decoder.v
true_dp_ram.v
top_dpram.v
true_dp_ram.vt
true_dp.do
true_dp_ram.qar ( Intel^® Quartus^® Prime design file)

6.1. External ECC Implementation with True-Dual-Port RAM

The ECC features are only supported internally in simple dual-port RAM by Stratix IV devices when the M144K is implemented or by Stratix V when the M20K is implemented. Therefore, this design example describes how ECC features can be implemented in other RAM modes, regardless of the type of device memory block you use. It also demonstrates the features of the same-port and mixed-port read-during-write behaviors.

This design example uses a true dual-port RAM and illustrates how the ECC feature can be implemented external to the RAM. The ALTECC_ENCODER and ALTECC_DECODER IP cores are required as the ALTECC_ENCODER IP core encodes the data input before writing the data into the RAM, while the ALTECC_DECODER IP core decodes the data output from the RAM before transferring the data out to other parts of the logic.

In this design example, the raw data width is 8 bits and is encoded by the ALTECC_ENCODER IP core block to produce a 13-bit width data that is written into the true dual-port RAM when write-enable signal is asserted. Because the RAM mode has two dedicated write ports, another encoder is implemented for the other RAM input port.

Two ALTECC_DECODER blocks are also implemented at each of the data output ports of the RAM. When the read-enable signal is asserted, the encoded data is read from the RAM address and decoded by the ALTECC_DECODER blocks, respectively. The decoder shows the status of the data as no error detected, single-bit error detected and corrected, or fatal error (more than 1-bit error).

This example also includes a "corrupt zero bit" control signal at port A of the RAM. When the signal is asserted, it changes the state of the zero-bit (LSB) encoded data before it is written into the RAM. This signal is used to corrupt the zero-bit data storing through port A, and examines the effect of the ECC features.

This design example describes how ECC features can be implemented with the RAM for cases in which the ECC is not supported internally by the RAM. However, the design examples might not represent the optimized design or implementation.

6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core

To generate the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP core, follow these steps:

Open the Internal_Memory_DesignExample.zip file and extract true_dp.qar.
In the Intel^® Quartus^® Prime software, open the true_dp.qar file and restore the archive file into your working directory.
In the IP Catalog (Tools > IP Catalog), locate and double-click the ALTECC IP core. The parameter editor appears.

Specify the following parameters:

Table 21. Configuration Settings for ALTECC_ENCODER
Option	Value
How do you want to configure this module?	Configure this module as an ECC encoder
How wide should the data be?	8 bits
Do you want to pipeline the functions?	Yes, I want an output latency of 1 clock cycle
Create an 'aclr' asynchronous clear port	Not selected
Create a 'clocken' clock enable clock	Not selected

Click Finish. The ecc_encoder.v module is built.
In the IP Catalog double-click the ALTECC IP core. The parameter editor appears.

Specify the following parameters:

Table 22. Configuration Settings for ALTECC_DECODER
Option	Value
How do you want to configure this module?	Configure this module as an ECC decoder
How wide should the data be?	13 bits
Do you want to pipeline the functions?	Yes, I want an output latency of 1 clock cycle
Create an 'aclr' asynchronous clear port	Not selected
Create a 'clocken' clock enable clock	Not selected

Click Finish. The ecc_decoder.v module is built.
In the IP Catalog double-click the ALTECC IP core. The parameter editor appears.

Specify the following parameters:

Table 23. Configuration Settings for RAM: 2-Port IP Core
Option	Value
Which type of output file do you want to create?	Verilog HDL
What name do you want for the output file?	true_dp_ram
Return to this page for another create operation	Turned off
Currently selected device family:	Stratix IV
How will you be using the dual port ram?	With two read/write ports
How do you want to specify the memory size?	As a number of words
How many 8-bit words of memory?	16
Use different data widths on different ports	Not selected
How wide should the 'q_a' output bus be?	13
What should the memory block type be?	M9K
Set the maximum block depth to	Auto
Which clocking method do you want to use?	Single clock
Create 'rden_a' and 'rden_b' read enable signals	Not selected
Byte Enable Ports	Not selected
Which ports should be registered?	All write input ports and read output ports
Create one clock enable signal for each signal	Not selected
Create an 'aclr' asynchronous clear for the registered ports	Not selected
Mixed Port Read-During-Write for Single Input Clock RAM	Old memory contents appear
Port A Read-During-Write Option	New Data
Port B Read-During-Write Option	Old Data
Do you want to specify the initial content of the memory?	Not selected
Generate netlist	Turned off
Variation file (.vhd)	Turned on
AHDL Include file (.inc)	Turned off
VHDL component declaration file (.cmp)	Turned on
Intel^® Quartus^® Prime symbol file (.bsf)	Turned off
Instantiation template file(.vhd)	Turned off

Click Finish. The true_dp_ram.v module is built.

The top_dpram.v is a design variation file that contains the top level file that instantiates two encoders, a true dual-port RAM, and two decoders. To simulate the design, a testbench, true_dp_ram.vt, is created for you to run in the ModelSim* - Intel^® FPGA Edition software.

6.1.2. Simulating the Design

To simulate the design in the ModelSim* - Intel^® FPGA Edition software, follow these steps:

Unzip the Internal_Memory_DesignExample.zip file to any working directory on your PC.
Start the ModelSim* - Intel^® FPGA Edition software.
On the File menu, click Change Directory.
Select the folder in which you unzipped the files.
Click OK.
On the Tools menu, point to TCL and click Execute Macro. The Execute Do File dialog box appears.
Select the true_dp.do file and click Open. The true_dp.do file is a script file that automates all the necessary settings, compiles and simulates the design files, and displays the simulation waveform.
Verify the result shown in the Waveform Viewer window.

You can rearrange signals, remove signals, add signals, and change the radix by modifying the script in true_dp.do accordingly.

6.1.2.1. Simulation Results

This table lists the top-level block contains the input and output ports.

Table 24. Top-level Input and Output Ports Representations
Ports Name	Ports Type	Descriptions
`clock`	Input	System Clock for the encoders, RAM, and decoders.
`corrupt_dataa_bit0`	Input	Registered active high control signal that 'twist' the zero bit (LSB) of input encoded data at port A before writing into the RAM. ¹⁵
`address_a` `data_a` `wren_a` `rden_a`	Input	Address input, data input, write enable, and read enable to port A of the RAM. ¹⁵
`address_b` `data_b` `wren_b` `rden_b`	Input	Address input, data input, write enable, and read enable to port B of the RAM. ¹⁵
`rdata1` `err_corrected1` `err_detected1` `err_fatal1`	Output	Output data read from port A of the RAM, and the ECC-status signals reflecting the data read. ¹⁶
`rdata2` `err_corrected2` `err_detected2` `err_fatal2`	Output	Output data read from port B of the RAM, and the ECC-status signals reflecting the data read. ¹⁶

Figure 7. Simulation ResultsThis figure shows the expected simulation waveform results in the ModelSim* - Intel^® FPGA Edition software.

Figure 8. Same-Port Read-During-WriteThis figure shows the timing diagram of when the same-port read-during-write occurs for each port A and port B of the RAM.

At 2500 ps, same-port read-during-write occurs for each port A and port B. Because the true dual-port RAM configured to port A is reading the new data and port B is reading the old data when the same-port read-during-write occurs, the rdata1 port shows the new data aa and the rdata2 port shows the old data 00 after four clock cycles at 17500 ps. When the data is read again from the same address at the next rising clock edge at 7500 ps, the rdata2 port shows the recent data bb at 22500 ps.

Figure 9. Mixed-Port Read-During-WriteThis figure shows the timing diagram of when the mixed-port read-during-write occurs.

At 12500 ps, mixed-port read-during-write occurs when data cc is both written to port A, and is reading from port B, simultaneously targeting the same address 1. Because the true dual-port RAM that is configured to mixed-port read-during-write is showing the old data, the rdata2 port shows the old data bb after four clock cycles at 27500 ps. When the data is read again from the same address at the next rising clock edge at 17500 ps, the rdata2 port shows the recent data cc at 32500 ps.

Figure 10. Write ContentionThis figure shows the timing diagram of when the write contention occurs.

At 22500 ps, the write contention occurs when data dd and ee are written to address 0 simultaneously. Besides that, the same-port read-during-write also occurs for port A and port B. The setting for port A and port B for same-port read-during-write takes effect when the rdata1 port shows the new data dd and the rdata2 port shows the old data aa after four clock cycles at 37500 ps. When the data is read again from the same address at the next rising clock edge at 27500 ps, rdata1 and rdata2 ports show unknown values at 42500 ps. Apart from that, the unknown data input to the decoder also results in an unknown ECC status.

Figure 11. Error Injection– Asserting corrupt_dataa_bit0 This figure shows the timing diagram of the effect when an error is injected to twist the LSB of the encoded data at port A by asserting corrupt_dataa_bit0.

At 32500 ps, same-port read-during-write occurs at port A while mixed-port read-during-write occurs at port B. The corrupt_dataa_bit0 is also asserted to corrupt the LSB of encoded data at port A; therefore, the storing data has the LSB corrupted, in which the intended data ff is corrupted, becomes fe, and stored at address 0. After four clock cycles at 47500 ps, the rdata1 port shows the new data ff that has been corrected by the decoder, and the ECC status signals, err_corrected1 and err_detected1, are asserted. For rdata2 port, old data (which is unknown) is shown and the ECC-status signal remains unknown.

Note: The decoders correct the single-bit error of the data shown at rdata1 and rdata2 ports only. The actual data stored at address 0 in the RAM remains corrupted, until new data is written.

At 37500 ps, the same condition happens to port A and port B. The difference is port B reads the corrupted old data fe from address 0. After four clock cycles at 52500 ps, the rdata2 port shows the old data ff that has been corrected by the decoder and the ECC status signals, err_corrected2 and err_detected2, are asserted to show the data has been corrected.

¹⁵ For input ports, only data signal goes through the encoder; others bypass the encoder and go directly to the RAM block. Because the encoder uses one pipeline, signals that bypass the encoder require additional pipelines before going to the RAM. This has been implemented in the top level.

¹⁶ The encoder and decoder each use one pipeline while the RAM uses two pipelines, making the total pipeline equal to four. Therefore, read data is only shown at output ports four clock cycles after the read enable is initiated.

7. Document Revision History for Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

Document Version	Intel^® Quartus^® Prime Version	Changes
2020.03.11	17.0	Updated the Design Example topic. Restructured the document.
2019.10.22	17.0	Added new Topic—Avoid Providing Non-Deterministic Input. Added a note to the RAM and ROM Interface Signals topic.

Date	Version	Changes
November 2017	2017.11.06	Updated the Changing Parameter Settings Manually topic. Updated the Freeze Logic topic. Updated "ROM: 2-PORT IP Core Parameters" table: Removed MLAB reference in legal values for memory block type. Updated for latest branding standards. Made editorial updates throughout the document.
May 2017	2017.05.08	Rebranded to Intel. Updated to Embedded Memory IP Cores Getting Started topic with links to Introduction to IP core. Updated the Features topic to include freeze logic feature support for RAM modes. Updated the Write Operation description for MLAB blocks in the Write and Read Operations Triggering for Embedded Memory Blocks table. Added Mixed-width Ratio Configuration topic. Added Freeze Logic topic. Added the Implement clock-enable circuitry for use in a partial reconfiguration region option for the RAM: 1-PORT and RAM: 2-PORT IP cores. Added support for Cyclone 10 LP and GX device families. Updated the legal value for `operation_mode` from TRUE_DUAL_PORT to BIDIR_DUAL_PORT in the Parameters for altera_syncram table. Updated the Interface Signals of the Embedded Memory IP Cores table. Updated the Configuration Settings for RAM: 2-Port IP Core table in the Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core topic. Updated note in the Clocking Modes and Clock Enable topic to remove Stratix III. Updated Quartus II to Intel^® Quartus^® Prime. Minor typographical corrections.
May 2016	2016.05.02	Updated the About Embedded Memory IP Cores topics. Added a new topic: Changing Parameter Settings Manually. Updated the Memory Block Types topic to add the memory types for Arria 10 and MAX 10. Updated the Error Correction Code topic.
December 2014	2014.12.17	Specified that to enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores. Updated document template.
2014.06.30	5.0	Replaced MegaWizard Plug-In Manager information with IP Catalog. Added standard information about upgrading IP cores. Added standard installation and licensing information. Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor. Removed all references to obsolete SOPC Builder tool.
May 2014	4.4	Editorial fix to Table 4–1 on page 4–5.
November 2013	4.3	Updated Table 3–8 on page 3–18 to update M20K block information.
May 2013	4.2	Updated Table 3–4 on page 3–11 to fix a typographical error.
November 2012	4.1	Added a note to the “Asynchronous Clear” on page 3–15 to state that internal contents cannot be cleared with the asynchronous clear signal. Updated note in “Clocking Modes and Clock Enable” on page 3–11 to include Stratix V devices. Added a note to the “Asynchronous Clear” on page 3–15 to clarify that clear deassertion on output latch is dependent on output clock.
January 2012	4.0	Added a note to “Power-Up Conditions and Memory Initialization” section.
November 2011	3.0	Updated the RAM2:Port parameter settings. Updated the Read-During-Write section. Added M10K memory block information. Added support information for Arria V and Cyclone V.
March 2011	2.0	Added new features for M20K memory block.
November 2009	1.0	Initial release