AN 720: Simulating the ASMI Block in Your Design
1. Simulating the ASMI Block in Your Design
1.1. Supported Devices
- Arria® V, Arria® V GZ, Intel® Arria® 10
- Cyclone® V
- Stratix® V
1.2. Overview
1.2.1. Block Diagrams for ASMI Block
1.2.2. Signals for ASMI Block
Signal | Direction | Width (bits) | Description |
---|---|---|---|
dclk | Input | 1 | Clock signal from your FPGA design to the external DCLK pin through the ASMI hard logic. |
sce | Input | 3 | Chip select signal from your FPGA design to the external nCSO pin through the ASMI hard logic. |
oe | Input | 1 | Active-low signal to enable DCLK and nCSO pins to reach the flash. The DCLK and nCSO are fixed to high when you set this signal to high, blocking the connection between FPGA and flash. |
data0out | Input of the ASMI block, which outputs the data from your FPGA design to the AS data pin | 4 |
Control signal from your FPGA design to the AS data pin for sending data into the serial configuration device. If you want to connect your Intel® Arria® 10, Arria® V, Arria® V GZ, Cyclone® V, or Stratix® V device to the EPCS device, Altera recommends setting the data out ports to the following:
|
data1out | |||
data2out | |||
data3out | |||
data0oe | Input | 4 |
Controls data pin either as input or output because the dedicated pins for active serial data is bidirectional. To set the AS data pin as input, set the desired data pin oe to 0. To set the AS data pin as output, set the desired data pin oe to 1. If you want to connect your Intel® Arria® 10, Arria® V, Arria® V GZ, Cyclone® V or Stratix® V device to the EPCS device, then set the data pin oe to the following:
|
data1oe | |||
data2oe | |||
data3oe | |||
data0in | Output of the ASMI block, which receives input from the AS data pin and outputs to your FPGA design | 4 |
Signal from the AS data pin to your FPGA design. If you want to connect your Intel® Arria® 10, Arria® V, Arria® V GZ, Cyclone® V or Stratix® V device to the EPCS device, then set the data in pin to the following:
|
data1in | |||
data2in | |||
data3in |
1.2.3. WYSIWYG for ASMI Block
Example of Verilog WYSIWYG for Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V ASMI Block
<device>_asmiblock <name> ( .dclk(<clock source from user design>), .sce(<1 bit SCE from user design>), .oe(<output enable from user design>), .data0out(<AS_DATA0 from user design>), .data1out(<AS_DATA1 from user design>), .data2out(<AS_DATA2 from user design>), .data3out(<AS_DATA3 from user design>), .data0oe (<OE of data0out from user design>), .data1oe (<OE of data1out from user design>), .data2oe (<OE of data2out from user design>), .data3oe (<OE of data3out from user design>), .data0in(<AS_DATA0 to user design>), .data1in(<AS_DATA1 to user design>), .data2in(<AS_DATA2 to user design>), .data3in(<AS_DATA3 to user design>) ); defparam <name>.enable_sim = "false";
Example of VHDL WYSIWYG for Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V ASMI Block
component <device>_asmiblock generic( enable_sim : string := "false" ); port( dclk : in std_logic; sce : in std_logic; oe : in std_logic; data0out : in std_logic; data1out : in std_logic; data2out : in std_logic; data3out : in std_logic; data0oe : in std_logic; data1oe : in std_logic; data2oe : in std_logic; data3oe : in std_logic; data0in : out std_logic; data1in : out std_logic; data2in : out std_logic; data3in : out std_logic ); end component;
Example of Verilog WYSIWYG for Intel® Arria® 10 ASMI Block
<device>_asmiblock <name> ( .dclk(<clock source from user design>), .sce(<3 bit SCE from user design>), .oe(<output enable from user design>), .data0out(<AS_DATA0 from user design>), .data1out(<AS_DATA1 from user design>), .data2out(<AS_DATA2 from user design>), .data3out(<AS_DATA3 from user design>), .data0oe (<OE of data0out from user design>), .data1oe (<OE of data1out from user design>), .data2oe (<OE of data2out from user design>), .data3oe (<OE of data3out from user design>), .data0in(<AS_DATA0 to user design>), .data1in(<AS_DATA1 to user design>), .data2in(<AS_DATA2 to user design>), .data3in(<AS_DATA3 to user design>) ); defparam <name>.enable_sim = "false";
Example of VHDL WYSIWYG for Intel® Arria® 10 ASMI Block
component <device>_asmiblock generic( enable_sim : string := "false" ); port( dclk : in std_logic; sce : in std_logic_vector(2 downto 0); oe : in std_logic; data0out : in std_logic; data1out : in std_logic; data2out : in std_logic; data3out : in std_logic; data0oe : in std_logic; data1oe : in std_logic; data2oe : in std_logic; data3oe : in std_logic; data0in : out std_logic; data1in : out std_logic; data2in : out std_logic; data3in : out std_logic ); end component;
1.3. Simulating the ASMI Block in Your Design
Set the enable_sim parameter to false, if you are using third-party flash devices. Otherwise, the default setting is true, which indicates EPCQ1024.
If you are using third-party devices, create a wrapper with the same module name in the simulation project.
1.3.1. Example: Simulating the ASMI Block in a Stratix V Device Using EPCQ Flash
To simulate the ASMI block in a Stratix® V device using the EPCQ flash, (for example, EPCQ1024), follow these steps:
-
Create a design which instantiates the ASMI block, and set the
enable_sim parameter to true.
Figure 3. Sample Code to Instantiate the ASMI Block Using EPCQ Flash
- Compile the design in the Intel® Quartus® Prime software and ensure that the design does not contain any syntax error.
-
In a simulation project, compile the following
file
to your working folder:
-
quartus/eda/sim_lib/stratixv_atoms.v or quartus/eda/sim_lib/stratixv_atoms.vhd (if
you are not using the
ModelSim* - Intel® FPGA Edition
software) Note: The ModelSim* - Intel® FPGA Edition software contains all device atom libraries, so no compilation is needed.
-
quartus/eda/sim_lib/stratixv_atoms.v or quartus/eda/sim_lib/stratixv_atoms.vhd (if
you are not using the
ModelSim* - Intel® FPGA Edition
software)
- Run simulation. The FPGA design is connected to the flash simulation model via the ASMI interface.
1.3.2. Example: Simulating the ASMI Block in a Stratix V Device Using Third-Party Flash Devices
To simulate the ASMI block in a Stratix® V device using third-party flash devices, follow these steps:
-
Create a
design which instantiated the ASMI block and set the enable_sim parameter to false.
Figure 4. Sample Code to Instantiate the ASMI Block
- Compile the design in the Intel® Quartus® Prime software and ensure that the design does not contain any syntax error.
-
Create a wrapper to connect a third-party flash simulation
model to the ASMI block through the asmi_sim_model module. Note that the interface for the asmi_sim_model module varies according to
devices.
Figure 5. Sample Code for Wrapper to Connect the Flash Model with the ASMI Block
-
In a simulation project, compile the following file to your
working folder:
- Flash simulation model
- asmi_sim_model design wrapper
-
quartus/eda/sim_lib/stratixv_atoms.v or quartus/eda/sim_lib/stratixv_atoms.vhd (if
you are not using the
ModelSim* - Intel® FPGA Edition
software) Note: The ModelSim* - Intel® FPGA Edition software contains all device atom libraries, so no compilation is needed.
- Run simulation. The FPGA design is connected to the flash simulation model via the ASMI interface.
1.4. Document Revision History for AN 720: Simulating the ASMI Block in Your Design
Document Version | Changes |
---|---|
2020.07.29 |
|
Date | Version | Changes |
---|---|---|
August 2015 | 2015.08.03 |
|
December 2014 | 2014.12.15 | Initial release. |