You can customize the IP cores by configuring various parameters to accommodate your needs.

The Quartus^® Prime software installs IP cores in the following locations by default:

If you are an expert user, and choose to configure the IP core directly through parameterized instantiation in your design, refer to the port and parameter details. The details of these ports and parameters are hidden in the parameter editor.

For a normal floating-point number, a leading 1 is always implied, for example, binary 1.0011 or decimal 1.1875 is stored as 0011 in the mantissa field. This format saves the mantissa field from using an extra bit to represent the leading 1. However, the leading bit for a denormal number can be either 0 or 1. For zero, infinity, and NaN, the mantissa field does not have an implied leading 1 nor any explicit leading bit.

• The MSB holds the sign bit.
• The next 8 bits hold the exponent bits.
• 23 LSBs hold the mantissa.

The total width of a floating-point number in the single-precision format is 32 bits. The bias for the single-precision format is 127.

• The MSB holds the sign bit.
• The next 11 bits hold the exponent bits.
• 52 LSBs hold the mantissa.

The total width of a floating-point number in the double-precision format is 64 bits. The bias for the double-precision format is 1023.

• The MSB holds the sign bit.
• The exponent and mantissa fields do not have fixed widths.
• The minimum exponent field width is 11 bits and must be less than the width of the mantissa field.
• The width of the mantissa field must be a minimum of 31 bits.

The sum of the widths of the sign bit, exponent field, and mantissa field must be a minimum of 43 bits and a maximum of 64 bits. The bias for the single-extended precision format is unspecified in the IEEE-754 standard. In these IP cores, a bias of 2 ⁽WIDTH_EXP–1⁾–1 is assumed for the single-extended precision format.

• round-to-nearest-even
• round-toward-zero
• round-toward-positive-infinity
• round-toward-negative-infinity

Altera floating-point IP cores support only the most commonly used rounding mode, which is the round-to-nearest-even mode (TO_NEAREST). With round-to-nearest-even, the IP core rounds the result to the nearest floating-point number. If the result is exactly halfway between two floating-point numbers, the IP core rounds the result so that the LSB becomes a zero, which is even.

The fixed-point data type is similar to the conventional integer data type, except that the fixed-point data carries a predetermined number of fractional bits. If the width of the fraction is 0, the data becomes a normal signed integer.

The notation for fixed-point format numbers in this user guide is Qm.f, where Q designates that the number is in Q format notation, m is the number of bits used to indicate the integer portion of the number, and f is the number of bits used to indicate the fractional portion of the number.

For example, Q4.12 describes a number with 4 integer bits and 12 fractional bits in a 16-bit word.

The following figures show the difference between the signed-integer format and the fixed-point format for a 32-bit number.

For specific details about latency options, refer to the Output Latency section of your selected IP core in this user guide.

Simulate the designs in the ModelSim^®-Altera software to generate a waveform display of the device behavior. You must be familiar with the ModelSim-Altera software before trying out the design examples.

• Cholesky decomposition function.

  The Cholesky decomposition function generates a lower triangular matrix.

• Triangular matrix inversion function.

  The triangular matrix inversion process then generates the inverse of the lower triangular using backward substitution.

• Matrix multiplication function.

  The matrix multiplier multiplies the transpose of the inverse triangular matrix with the inverse triangular matrix.

In linear algebra, the Cholesky decomposition states that every positive definite matrix A is decomposed as A = L×LT

where, L is a lower triangular matrix, and LT denotes the transpose of L.

The property of invertible matrices states that (X×Y)-1 = X-1×Y-1 and the property of transpose states that (XT )-1 = (X-1)T. Combining these two properties, the following equation represents a derivation of a matrix inversion using the Cholesky decomposition method:

A-1 = (L×LT)-1

       = (LT)-1 × L-1

       = (L-1)T × L-1

where a Cholesky decomposition function is needed to obtain L, a triangular matrix inversion is needed to obtain L-1, and a matrix multiplication is needed for (L-1)T × L-1.

The other memory block is the processing matrix block which consists of multiple column memories to enable an entire row to be read at once. During the loading of the input memory, the FPC datapath preprocesses the input elements to generate the first column of the resulting triangular matrix. The top element of the first column, l00, is the square root of the input matrix value a00. The rest of the first column, li0 is the input value ai0 divided by l00. This preprocessing step introduces latency into the load, during which the INIT_BUSY signal is asserted. The CALCULATE signal initiates and starts processing after the INIT_BUSY signal is deasserted.

This figure shows the top-level architecture of the Cholesky decomposition function, where the monolithic input memory and the column-wise processing memory, also known as the vector matrix, are shown. The gray block is the FPC datapath section.

Although the Cholesky decomposition algorithm only operates on the lower triangular matrix, the core requires the entire matrix to be loaded, during which the processing or vector memory is initialized.

The FPC datapath is split into two sections. The first section, also known as the vector section, takes the inner product of two vectors and subtracts it from the input matrix element, a_ij. The second section, also known as the root section, calculates square roots and performs division by the square root. The first element is loaded into both inputs of the root section and the outcome is its own square root. The first element continues to stay latched in the left input field of the root section while all the other elements of the first column are loaded into the right input field. The resulting output is the value of the respective column element divided by the value of the first element of the Cholesky decomposition matrix.

During processing, two rows from the processing matrix are loaded. For the first element in each new column, both rows have the same index; hence contain the same values. The first row is latched into the input register of the vector section. For the rest of the column, the row index is increased, and a new a_ij element and triangular matrix vector, L_j is loaded. The first result out of the vector section is latched onto the left register of the root section. All results from the column, including the first result, are loaded into the right register of the root section. The root section generates the square root of the first vector result, while for the other results coming from the vector section, the number is divided by the square root of the first result.

All calculated values are written to another memory block for further processing. The first column values are output singly during preprocessing, while the values of other columns are burst out during processing.

There are only minor differences between the architectures for real and complex matrices. For the complex matrix, both the input and processing memory blocks contain complex values. Similarly, all values going into the vector section are complex numbers. The complex conjugate of the latched register is obtained by simply inverting the sign bit. As for the root section, the structure is simplified by the nature of the positive definite matrix. The diagonal value, which is the first value at the top of each column in the decomposition, is always a real number so that the result from the inverse square root calculation is always a real number. The complex multiplier in the root section is therefore a real scalar, so only two real multipliers are required.

for j = n:-1:1,

X(j,j) = 1/L(j, j);

for k = j+1:n

for i = j+1:n

X(k, j) = X(k, j) + X(k, i)*L(i, j);

end;

end;

for k = j+1:n

X(k, j) = -X(j, j)*X(k, j);

end;

The pseudo code is converted into an RTL file. The result, L-1 is stored in the input matrix storage in the Cholesky decomposition function.

Figure 15. ALTERA_FP_MATRIX_INV ModelSim Simulation Waveform (Input Data)This figure shows the expected simulation results in the ModelSim-Altera software.

This design example implements a floating-point matrix inversion to calculate the inverse value of matrices in single-precision formats. The optional input ports (enable and reset) are enabled.

The following figure shows the equation:

The matrix A and B can be loaded when the ready signal on their respective interfaces are asserted. When the input matrices are loaded, the core will start computing the output. Valid signal on the output interface will be asserted to indicate valid output data. The input data may be loaded at any time the ready signal is asserted even when the previously loaded data is still being computed.

The ALTERA_FP_MATRIX_MULT IP core consists of the following components:

• Memory blocks for the matrix A storage
• Memory blocks for the matrix B storage
• Dot product
• Accumulator
  Figure 19. Top-Level View of the ALTERA_FP_MATRIX_MULT IP CoreThis figure shows the top-level view of the ALTERA_FP_MATRIX_MULT IP core.

The following lists the key features of the architecture:

• Matrix A and B storage are double buffered to allow processing to happen in parallel with data loading.
• Where the number of columns of A (A_COLUMNS) and rows of B (same as A_COLUMNS) are greater than the size of the dot product (VECTOR_SIZE), the rows of A and columns of B are divided into sub rows and sub columns respectively, each containing VECTOR_SIZE elements. In this case, A_COLUMNS/VECTOR_SIZE iterations are needed to compute a full dot product corresponding to a single output element.
• Matrix B memory has sufficient bandwidth so that all the data needed for the dot product can be loaded at once.
• Matrix A memory is allocated with less bandwidth. The bandwidth of the matrix A is a parameter (NUM_BLOCKS) that you can control. A sub row of matrix A is loaded into local registers over a number of cycles before an iteration of the dot product. Once a sub row of Matrix A has been loaded into local registers, all partial dot products involving that sub row are computed before another sub row is loaded.
• For Arria 10 devices, where hardened single precision floating-point DSP blocks exist, those will be used for single precision floating point arithmetic.

The matrix multiply architecture is not optimized for sparse matrices and constant matrices.

Figure 24. ALTFP_DIV Simulation WaveformThis figure shows the expected simulation results in the ModelSim-Altera software.

This design example implements a floating-point divider for the division of single-precision numbers with a low latency option. The output latency is 6, hence every division generates the output result 6 clock cycles later.

Figure 26. ALTFP_MULT Simulation WaveformThis figure shows the expected simulation results in the ModelSim-Altera software.

This design example implements a floating-point multiplier for the multiplication of double-precision format numbers. All the optional input ports (clk_en and aclr) and output ports (overflow, underflow, zero, and nan) are enabled.

In this example, the latency is set to 6 clock cycles. Therefore, every multiplication result appears at the result port 6 clock cycles later.

This IP core performs square root calculation based on the input provided.You can use the ports and parameters available to customize the ALTFP_SQRT IP core according to your application.

These figures show the expected simulation results in the ModelSim-Altera software.

Figure 27. ALTFP_SQRT ModelSim Simulation Waveform (Input Data)

Figure 28. ALTFP_SQRT ModelSim Simulation Waveform (Output Data)

This design example implements a floating-point square root function for single-precision format numbers with all the exception output ports instantiated. The output ports include overflow, zero, and nan.

The output latency is 28 clock cycles. Every square root computation generates the output result 28 clock cycles later.

These figures show the expected simulation results in the ModelSim-Altera software.

Figure 30. ALTFP_EXP ModelSim Simulation Waveform (Input Data)

Figure 31. ALTFP_EXP ModelSim Simulation Waveform (Output Data)

This design example implements a floating-point exponential for the single-precision format numbers. The optional input ports (clk_en and aclr) and all four exception handling output ports (nan, overflow, underflow, and zero) are enabled.

For single-precision format numbers, the latency is fixed at 17 clock cycles. Therefore, every exponential operation outputs the results 17 clock cycles later.

This IP core performs the function of 1/a where a is the given input.

This design example uses the ALTFP_INV IP core to compute the inverse of single-precision format numbers. This example uses the parameter editor in the Quartus II software.

These figures show the expected simulation results in the ModelSim-Altera software.

Figure 33. ALTFP_INV ModelSim Simulation Waveform (Input Data)

Figure 34. ALTFP_INV ModelSim Simulation Waveform (Output Data)

This design example implements a floating-point inverse for single-precision format numbers. The optional input ports (clk_en and aclr) and all four exception handling output ports (division_by_zero, nan, zero, and underflow) are enabled.

The latency is fixed at 20 clock cycles; therefore, every inverse operation outputs results 20 clock cycles later.

This table lists the inputs and corresponding outputs obtained from the simulation in the waveforms.

This IP core performs inverse square root value of a given input.

These figures show the expected simulation results in the ModelSim-Altera software.

Figure 35. ALTFP_INV_SQRT ModelSim Simulation Waveform (Input Data)

Figure 36. ALTFP_INV_SQRT ModelSim Simulation Waveform (Output Data)

This design example implements a floating-point inverse square root for single-precision format numbers. The optional input ports (clk_en and aclr) and all three exception handling output ports (division_by_zero, nan, and zero) are enabled.

The latency is fixed at 26 clock cycles. Therefore, every inverse square root operation outputs the results 26 clock cycles later.

This table lists the inputs and corresponding outputs obtained from the simulation in the waveforms.

This IP core performs arctangent calculation. You can use the ports and parameters available to customize the ALTFP_ATAN IP core according to your application.

This IP core performs absolute value calculation for the given input.

Figure 42. ALTFP_ABS Simulation Waveform

This design example produces a floating-point absolute value function for the multiplication results of single-precision format numbers. All the optional input ports (clk_en and aclr) and optional output ports (overflow, underflow, zero, division_by_zero, and nan) are enabled.

In this example, the latency of the multiplier is set to five clock cycles, while none is being set for the absolute value function. Thus, the absolute value result only appears at the result[] port five cycles after the input values are captured on the input ports.

The dataa[] and datab[] values in the simulation waveform above portray the two input values that are being fed to the multiplier. The value in the result[] port depicts the multiplication result that has gone through the absolute value operation.

This table lists the inputs and corresponding outputs obtained from the simulation.

This figure shows the expected simulation results in the ModelSim-Altera software.

Figure 44. ALTFP_COMPARE Simulation Waveform

This design example implements a floating-point comparator for single-precision numbers. Both optional input ports (clk_en and aclr) and all seven output ports (ageb, aeb, agb, aneb, alb, aleb, and unordered) are enabled.

The chosen output latency is 3. Therefore, the comparison operation generates the output result 3 clock cycles later.

This table lists the inputs and corresponding outputs obtained from the simulation in the waveform.