The random number generator IP core allows you to define the random
sequence seed manually.The uniformly distributed integer number generator is a random sequence
of 32 bit data, which can be interpreted as signed or unsigned integer.
The IP core offers two algorithms to generate the Gaussian sequence:
central-limit theorem (CLT) components and Box-Muller transform. The CLT components make use
of a mixture of Irwin-hall distribution (the distribution of sum of uniform distribution) to
approximate the Gaussian distribution. The classic Box-Muller transform is for reference, as
it is more costly to implement on hardware and has only average random sequence quality.
1.1. Random Number Generator IP Core Features
Uniformly distributed integer number
Uniformly distributed floating point number
Floating point number under Gaussian distribution
1.2. Random Number Generator Device Family Support
Intel offers the following device
support levels for Intel FPGA IP cores:
Advance support—the IP
available for simulation and compilation for this device family. FPGA
programming file (.pof) support is not
available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP
timing closure cannot be guaranteed. Timing models include initial engineering
estimates of delays based on early post-layout information. The timing models
are subject to change as silicon testing improves the correlation between the
actual silicon and the timing models. You can use this IP core for system
architecture and resource utilization studies, simulation, pinout, system
latency assessments, basic timing assessments (pipeline budgeting), and I/O
transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
Preliminary support—Intel verifies
with preliminary timing models for this device family. The IP core meets all
functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.
Final support—Intel verifies the
with final timing models for this device family. The IP core meets all
functional and timing requirements for the device family. You can use it in
Table 1. DSP IP
Arria® II GX
Arria II GZ
Stratix® IV GT
Stratix IV GX/E
Other device families
1.3. Random Number Generator Performance and Resource Usage
Table 2. Performance and Resource UsageTargeting 10AX115S3F45E2SGE3 Arria 10 device.
Uniform distribution integer
Uniform distribution float
Normal distribution with central limit transform (CLT) components
Normal distribution with Box-Muller
1.4. Random Number Generator IP Core Signals
Table 3. Parameters
Stalls the IP core for backpressure.
Indicates valid output.
1.5. Random Number Generator IP Core Parameters
Set the parameters to create an IP core suitable for your design.
Table 4. Parameters
Type of the generator
Uniform distribution (integer), uniform distribution (float),
normal distribution (float)
The type of the random number generator.
Central limit components (recommended) or Box Muller
The algorithm to use for the Gaussian distribution generator
(normal distribution only).
Auto or manaul
Set the seed manually or automatically.
Value of the seed
1 to 2147483647; default: 68997764
Manually input the seed for the random sequence, in the format of
1.6. Document Revision History for the Random Number Generator IP Core User Guide
Removed support for Cyclone
IV, Cyclone V, and Intel MAX 10 devices.
Corrected rand_num_data and rand_num_valid signals to be