AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
The Intel FPGA JESD204B IP Core is a high-speed point-to-point serial interface intellectual property (IP).
The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) DAC (digital-to-analog) devices.
This report highlights the interoperability of the JESD204B IP core with the AD9371 converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results.
The AD9371 is a wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. Its high speed JESD204B interface supports lane rates up to 6144 Mbps.
Hardware Requirements
The hardware checkout test requires the following hardware and software tools:
- Intel® Arria® 10 GX FPGA Development Kit
- ADI AD9371-PCBZ EVM
- Mini-USB cables
- SMA Cables
- Oscilloscope/Spectrum Analyzer
- Clock source capable of generating 122.88MHz
Hardware Setup
An Intel® Arria® 10 GX Development Kit is used with the ADI AD9371 daughter card module installed to the FMC connector A of the development board.
- The AD9371 EVM derives power from FMC pins.
- The clock generator AD9528 is available on the EVM. The reference clock for AD9528 is sourced from external clock.
- The device clocks for both converter and FPGA are generated by AD9528.
- The FPGA device clock is supplied through FMC pins. The link and frame clocks are generated from this device clock using Intel IOPLL.
- For subclass 1, AD9528 clock generator on the EVM generates SYSREF for both FPGA and AD9371. The sysref for FPGA is supplied through FMC pins.
- The sync_n signal is transmitted from
- the DAC of AD9371 to FPGA through FMC.
- the FPGA to ADC of AD9371 through FMC.
The following system-level diagram shows how the different modules connect in this design.
In this setup, the maximum data rate of transceiver lanes is 6.144Gbps. The clock generator available on the EVM is used for clocking both the EVM and the FPGA. The SPI master in FPGA programs both AD9371 registers and AD9528 clock generator registers available on the EVM through 4 wire SPI interface via FMC pins. The reference clock for this clock generator has to be provided by an external clock source. The converter device clock, FPGA device clock, and SYSREF (for both FPGA and converters) are generated by AD9528. FPGA receives these clocks through FMC pins. The converters operate in a single JESD link in all configurations with a maximum of 4 lanes.
AD9371 EVM Software Setup
The AD9371 Transceiver evaluation software is used to generate the setup files for the AD9371 device and AD9528 clock generator for JESD204B link operation. For more information about AD9371 Transceiver evaluation software, visit the Analog website.
Setup files for each of the parameter configurations are included in the software installation in the form of predefined profiles. You need to generate the C scripts using the profiles with correct settings for the JESD204B link to operate at the targeted data rate and JESD204B link parameters.
Follow these steps to generate the configuration C scripts via the AD9371 Transceiver evaluation software graphical user interface (GUI):
- Start the AD9371 Transceiver
Evaluation Software (TES). Figure 3 shows the opening page of TES.Figure 3. AD9371 TES interface
- In the case when evaluation
hardware is not connected, the user can still use the software in demonstration mode by
following these steps:
- Click Connect (top left corner).
- The Zynq board is disconnected message appears; click OK. After clicking OK, the software enters demonstration mode in which a subset of all features is displayed as shown in Figure 4.
- The first tab displayed is the
Configuration tab. Selecting this tab opens the initial screen, as shown in Figure 4. The
following selections are available from this tab:
- Device clock frequency
- Number of active Rx channels
- Number of active Tx channels
- Select observation/Sniffer input
- Select profiles for Rx, Tx, ORx, and Sniffer Rx
- Select Rx, Tx, and SnRx/ORx RF frequency
- The AD9371 provides a observation
receiver (ORx ADC). The SERDES for main receiver datapath and observation receiver datapath
are shared, but they have independent JESD204B framers (For more information, refer to the
AD9371 User Guide). In this interoperability report, only the main ADC datapath has been
considered. Figure 4. TES configuration tab
- Set the Configurations based on the requirements and move to JESD204b setup tab, which appears as shown in Figure 5.
- In this tab, set the required JESD link parameters and lane rate for both
Tx Deframer (DAC) and Rx Framer (Main ADC). Figure 5. JESD204B setup tab
- After configuring the GUI with required settings, the C scripts for
configuring the EVM can be generated by clicking on Tools -> Create Script -> C script as
shown in Figure 6. Save the file with name “myk_config” so that the existing software
makefiles can be used for compiling the scripts.Figure 6. Generating configuration C scripts
Hardware Checkout Methodology for JESD204B Transmitter
The following section describes the test objectives, procedure, and the passing criteria for JESD204B transmitter.
- Transmitter data link layer
- Transmitter transport layer
- Scrambling
- Deterministic latency (Subclass 1)
Transmitter Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initial lane alignment sequence (ILAS).
On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The Signal Tap Logic Analyzer tool monitors the transmitter data link layer operation.
Code Group Synchronization (CGS)
Test Case |
Objective |
Description |
Passing Criteria |
---|---|---|---|
TX_CGS.1 |
Check that /K/ characters are transmitted when sync_n is asserted. |
The following signals in <ip_variant_name>_inst_phy.v are tapped:
The following signals in <ip_variant_name>.v are tapped:
The txlink_clk is used as the sampling clock for the Signal Tap. Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data. The 32-bit data bus for is divided into 4 octets. |
|
TX_CGS.2 |
Check that /K/ characters are transmitted after sync_n is deasserted but before the start of multiframe. |
The following signals in <ip_variant_name>_inst_phy.v are tapped:
The following signals in <ip_variant_name>.v are tapped:
The txlink_clk is used as the sampling clock for the Signal Tap. Each lane is represented by 32-bit data bus in the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into 4 octets. Check the following status and error in the AD9371 register:
|
|
Initial Frame and Lane Synchronization
Test Case | Objective | Description | Passing Criteria |
---|---|---|---|
TX_ILA.1 |
Check that the /R/ and /A/ characters are transmitted at the beginning and end of each multiframe. Verify that four multiframes are transmitted in ILAS phase and receiver detects the initial lane alignment sequence correctly. |
The following signals in <ip_variant_name>_inst_phy.v are tapped:
The following signals in <ip_variant_name>.v are tapped:
The txlink_clk is used as the sampling clock for the Signal Tap. Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data. The 32-bit data bus for is divided into 4 octets. Check the following status in the AD9371 registers:
|
|
TX_ILA.2 |
Check the JESD204B configuration parameters are transmitted in the second multiframe. |
The following signals in <ip_variant_name>_inst_phy.v are tapped:
The following signal in <ip_variant_name>.v is tapped:
The txlink_clk is used as the sampling clock for the Signal Tap. The Nios® console accesses the following JESD204B CSR registers:
The content of 14 configuration octets in second multiframe is stored in the above 32-bit registers. Check the following status and error in the AD9371 register:
|
|
TX_ILA.3 |
Check the constant pattern of transmitted user data after the end of
4th multiframe. Verify that the receiver successfully enters user data phase. |
The following signals in <ip_variant_name>_inst_phy.v are tapped:
The following signals in <ip_variant_name>.v are tapped:
The txlink_clk is used as the sampling clock for the Signal Tap. The Nios console accesses the JESD204B CSR register - tx_err. Check the following errors in the AD9371 register:
|
|
Transmitter Transport Layer
To verify the data integrity of the payload data stream through the JESD204B transmitter IP core and transport layer and to verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a monotone sine wave. Connect an oscilloscope/spectrum analyzer to observe the waveform/spectrum of a singletone at the DAC analog channels.
The AD9371 upconverts signal to RF frequency. This RF frequency is tunable by the user and specified to AD9371 as LO frequency. Depending on the phase of I and Q streams, the output frequency at DAC analog channels will be LO frequency ± monotone frequency. In our configuration the output frequency will be observed to be LO frequency – monotone frequency.
The Signal Tap II Logic Analyzer tool monitors the operation of the transmitter transport layer.
Test Case |
Objective |
Description |
Passing Criteria |
---|---|---|---|
TX_TL.1 |
Verify the data transfer from digital to analog domain. |
Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope. |
A monotone sine wave is observed on the oscilloscope. |
Scrambling
The test setup is similar to test case TX_TL.1 except that the scrambler at the JESD204B transmitter IP core and the descrambler at the DAC JESD core are enabled.
The Signal Tap II Logic Analyzer tool monitors the operation of the transmitter transport layer.
Test Case | Objective | Description | Passing Criteria |
---|---|---|---|
TX_SCR.1 |
Verify the data transfer from digital to analog domain. |
Enable descrambler at the DAC JESD core and scrambler at the JESD204B transmitter IP core. Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope. |
A monotone sine wave is observed on the oscilloscope. |
JESD204B IP Core and DAC Configurations
The JESD204B IP Core parameters (L, M, and F) in this hardware checkout are natively supported by the AD9371 device's configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9371 operating conditions.
The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.
Configuration |
Mode |
Mode |
Mode |
Mode |
Mode |
Mode |
---|---|---|---|---|---|---|
LMF |
124 |
222 |
421 |
148 |
244 |
442 |
HD |
0 |
0 |
1 |
0 |
0 |
0 |
S |
1 |
1 |
1 |
1 |
1 |
1 |
N |
16 |
16 |
16 |
16 |
16 |
16 |
N’ |
16 |
16 |
16 |
16 |
16 |
16 |
CS |
0 |
0 |
0 |
0 |
0 |
0 |
CF |
0 |
0 |
0 |
0 |
0 |
0 |
Subclass |
1 |
1 |
1 |
1 |
1 |
1 |
Lane Rate (Gbps) |
6.144 |
6.144 |
3.072 |
6.144 |
6.144 |
6.144 |
DAC IQ rate (MSPS) |
153.6 |
307.2 |
307.2 |
76.8 |
153.6 |
307.2 |
AD9371 Device Clock (MHz) |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
FPGA Device Clock (MHz) 4 |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
FPGA Management Clock (MHz) |
100 |
100 |
100 |
100 |
100 |
100 |
FPGA Frame Clock (MHz) 5 |
153.6 |
307.2 |
76.8 |
76.8 |
153.6 |
153.6 |
FPGA Link Clock (MHz) 5 |
153.6 |
153.6 |
76.8 |
153.6 |
153.6 |
153.6 |
DAC RF local oscillator frequency (GHz) |
1.0 |
1.0 |
1.0 |
1.0 |
1.0 |
1.0 |
Character Replacement |
Enabled |
Enabled |
Enabled |
Enabled |
Enabled |
Enabled |
PCS Option |
Hard PCS |
Hard PCS |
Hard PCS |
Hard PCS |
Hard PCS |
Hard PCS |
Data Pattern |
Sine 6 Single pulse 7 Sinc 7 |
Sine 6 Single pulse 7 Sinc 7 |
Sine 6 Single pulse 7 Sinc 7 |
Sine 6 Single pulse 7 Sinc 7 |
Sine 6 Single pulse 7 Sinc 7 |
Sine 6 Single pulse 7 Sinc 7 |
Hardware Checkout Methodology for JESD204B Receiver
The following section describes the test objectives, procedure, and the passing criteria for JESD204B receiver.
The test covers the following areas:
- Receiver data link layer
- Receiver transport layer
- Descrambling
- Deterministic latency (Subclass 1)
Receiver Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization.
On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. TheSignal Tap Logic Analyzer tool monitors the receiver data link layer operation.
Code Group Synchronization (CGS)
Test Case | Objective | Description | Passing Criteria |
---|---|---|---|
RX_CGS.1 |
Check whether sync request is deasserted after correct reception of four successive /K/ characters. |
The following signals in <ip_variant_name>_inst_phy.v are tapped:
The following signals in <ip_variant_name>.v are tapped:
The rxlink_clk is used as the sampling clock for the Signal Tap. Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus for is divided into 4 octets. |
|
RX_CGS.2 |
Check full CGS at the receiver after correct reception of another four 8B/10B characters. |
The following signals in <ip_variant_name>_inst_phy.v are tapped:
The following signals in <ip_variant_name>.v are tapped:
The rxlink_clk is used as the sampling clock for the Signal Tap. |
The following signals should not be asserted during CGS phase:
|
Initial Frame and Lane Synchronization
Test Case | Objective | Description | Passing Criteria |
---|---|---|---|
RX_ILA.1
|
Check whether the initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters. |
The following signals in <ip_variant_name>_inst_phy.v are
tapped:
The following signals in <ip_variant_name>.v are tapped:
The rxlink_clk is used as the sampling clock for the Signal Tap. Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus for is divided into 4 octets. |
|
RX_ILA.2
|
Check the JESD204B configuration parameters from ADC in second multiframe. |
The following signals in <ip_variant_name>_inst_phy.v are
tapped:
The following signal in <ip_variant_name>.v is tapped:
The rxlink_clk is used as the sampling clock for the Signal Tap. The Nios console
accesses the following registers:
The content of 14 configuration octets in second multiframe is stored in these 32-bit registers - ilas_octet0, ilas_octet1, ilas_octet2 and ilas_octet3. |
|
RX_ILA.3
|
Check the lane alignment |
The following signals in <ip_variant_name>_inst_phy.v are
tapped:
The following signals in <ip_variant_name>.v are tapped:
The rxlink_clk is used as the sampling clock for the Signal Tap. |
|
Receiver Transport Layer
To check the data integrity of the payload data stream through the JESD204B receiver IP Core and transport layer, the ADC is fed with a monotone sine wave test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP Core.
The AD9371 downconverts from RF frequency to monotone frequency. This RF frequency is tunable by the user and specified to AD9371 as LO frequency. Depending on the required phase of I and Q streams, the input frequency at ADC analog channels should be LO frequency ± monotone frequency. In our configuration the input frequency of LO frequency – monotone frequency is used. This is easily available at AD9371 DAC analog output and the same waveform is looped back to ADC through SMA cable.
Test Case | Objective | Description | Passing Criteria |
---|---|---|---|
RX_TL.1 |
Check the transport layer mapping using Sine test pattern. |
The following signals in altera_jesd204_transport_rx_top.sv are tapped:
The following signals in jesd204b_ed.sv are tapped:
The rxframe_clk is used as the sampling clock for the Signal Tap II. |
|
Descrambling
The test setup is similar to test case RX_TL.1 except that the descrambler at the JESD204B receiver IP core and the scrambler at the ADC JESD transmitter core are enabled.
The Signal Tap II Logic Analyzer tool monitors the operation of the receiver transport layer.
Test Case | Objective | Description | Passing Criteria |
---|---|---|---|
RX_SCR.1 |
Check the functionality of the descrambler using sine wave test pattern. |
Enable scrambler at the ADC and descrambler at the JESD204B receiver IP Core. The signals that are tapped in this test case are similar to test case TL.1 |
|
JESD204B IP Core and Main ADC Configurations
The JESD204B IP Core parameters (L, M, and F) in this hardware checkout are natively supported by the AD9371 device. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9371 operating conditions.
The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.
Configuration |
Mode |
Mode |
Mode |
Mode |
Mode |
Mode |
---|---|---|---|---|---|---|
LMF |
124 |
222 |
421 10 |
148 |
244 |
442 |
HD |
0 |
0 |
1 |
0 |
0 |
0 |
S |
1 |
1 |
1 |
1 |
1 |
1 |
N |
16 |
16 |
16 |
16 |
16 |
16 |
N’ |
16 |
16 |
16 |
16 |
16 |
16 |
CS |
0 |
0 |
0 |
0 |
0 |
0 |
CF |
0 |
0 |
0 |
0 |
0 |
0 |
Subclass |
1 |
1 |
1 |
1 |
1 |
1 |
Lane Rate (Gbps) |
6.144 |
3.072 |
1.536 10 |
6.144 |
6.144 |
3.072 |
ADC IQ rate(MSPS) |
153.6 |
153.6 |
153.6 |
76.8 |
153.6 |
153.6 |
AD9371 Device Clock (MHz) |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
FPGA Device Clock (MHz) 11 |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
153.6 |
FPGA Management Clock (MHz) |
100 |
100 |
100 |
100 |
100 |
100 |
FPGA Frame Clock (MHz) 12 |
153.6 |
153.6 |
38.4 |
76.8 |
153.6 |
76.8 |
FPGA Link Clock (MHz) 12 |
153.6 |
76.8 |
38.4 |
153.6 |
153.6 |
76.8 |
ADC RF local oscillator frequency (GHz) |
1.0 |
1.0 |
1.0 |
1.0 |
1.0 |
1.0 |
Character Replacement |
Enabled |
Enabled |
Enabled |
Enabled |
Enabled |
Enabled |
PCS Option |
Hard PCS |
Hard PCS |
Hard PCS |
Hard PCS |
Hard PCS |
Hard PCS |
Data Pattern |
Sine 13 Single pulse 14 Sinc 14 |
Sine 13 Single pulse 14 Sinc 14 |
Sine 13 Single pulse 14 Sinc 14 |
Sine 13 Single pulse 14 Sinc 14 |
Sine 13 Single pulse 14 Sinc 14 |
Sine 13 Single pulse 14 Sinc 14 |
Deterministic Latency (Subclass 1)
The figure below shows a block diagram of the deterministic latency test setup. AD9528 clock generator on the EVM provides periodic SYSREF pulses for both the AD9371 and JESD204B IP Core. The period of SYSREF pulses is configured to be an integer multiple of Local Multi Frame Clocks (LMFC). The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.
The link latency for DAC and ADC is measured collectively by performing external loopback at RF level using SMA cable. The time difference between rising edge of pattern transmitted at transmitter transport layer and rising edge of pattern received back at receiver transport layer gives us the link latency. This latency has to remain constant across multiple power cycles of the system.
While performing the loopback delay measurement, the transmitter and receiver are both configured with same JESD204B configurations. The only exception is the JESD204B receiver mode with LMF = 421, which cannot be implemented in Intel® Arria® 10 FPGA because of unsupported data rate. In this mode, the ADC and FPGA are configured with LMF=222 configuration and the data rate is 3.072 Gbps. The FPGA and DAC JESD transmitter are configured with LMF = 421 configuration and the data rate is 3.072 Gbps. This enables us to perform delay measurement for this mode.
The FPGA can generate a 16-bit digital sample for single pulse or sinc pattern at the transport layer. Either waveform can be used to measure the loopback latency. The transmitted pulse and received pulse are both plotted in Signal Tap Logic Analyzer. The time difference between the 2 pulses gives us the loopback latency which includes both transmitter link latency and receiver link latency.
Test Case |
Objective |
Description |
Passing Criteria |
---|---|---|---|
DL.1 |
Check the FPGA SYSREF single detection. |
Check that the FPGA detects the first rising edge of SYSREF pulse. Read the status of sysref_singledet (bit[2]) identifier in syncn_sysref_ctrl register at address 0x54. |
The value of sysref_singledet identifier should be zero. |
DL.2 |
Check the SYSREF capture. |
Check that FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both FPGA and ADC are also repetitively reset. Read the value of rbd_count (bit[10:3]) identifier in rx_status0 register at address 0x80. |
If the SYSREF is captured correctly and the LMF counter restarts, for every reset, the rbd_count value should only drift a little due to word alignment. |
DL.3 |
Measure the total latency. |
Measure the time difference between the rising edge of pulses in Signal Tap Logic Analyzer. |
The latency should be consistent. |
DL.4 |
Re-measure the total latency after setup power cycle and FPGA reconfiguration. |
Measure the time difference between the rising edge of pulses in Signal Tap Logic Analyzer. |
The latency should be consistent. |
Test Results
The following table contains the possible results and their definition.
Result | Definition |
---|---|
PASS | The Device Under Test (DUT) was observed to exhibit conformant behavior. |
PASS with comments | The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed. |
FAIL | The DUT was observed to exhibit non-conformant behavior. |
Warning | The DUT was observed to exhibit behavior that is not recommended. |
Refer to comments | From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included. |
The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.
Test | L | M | F | SCR | K | Lane rate (Gbps) | DAC IQ rate (MSPS) | Link Clock (MHz) | Result |
---|---|---|---|---|---|---|---|---|---|
1 | 1 | 2 | 4 | 0 | 32 | 6.144 | 153.6 | 153.6 | PASS with comments |
2 | 1 | 2 | 4 | 1 | 32 | 6.144 | 153.6 | 153.6 | PASS with comments |
3 | 2 | 2 | 2 | 0 | 32 | 6.144 | 307.2 | 153.6 | PASS with comments |
4 | 2 | 2 | 2 | 1 | 32 | 6.144 | 307.2 | 153.6 | PASS with comments |
5 | 4 | 2 | 1 | 0 | 32 | 3.072 | 307.2 | 76.8 | PASS with comments |
6 | 4 | 2 | 1 | 1 | 32 | 3.072 | 307.2 | 76.8 | PASS with comments |
7 | 1 | 4 | 8 | 0 | 32 | 6.144 | 76.8 | 153.6 | PASS with comments |
8 | 1 | 4 | 8 | 1 | 32 | 6.144 | 76.8 | 153.6 | PASS with comments |
9 | 2 | 4 | 4 | 0 | 32 | 6.144 | 153.6 | 153.6 | PASS with comments |
10 | 2 | 4 | 4 | 1 | 32 | 6.144 | 153.6 | 153.6 | PASS with comments |
11 | 4 | 4 | 2 | 0 | 32 | 6.144 | 307.2 | 153.6 | PASS with comments |
12 | 4 | 4 | 2 | 1 | 32 | 6.144 | 307.2 | 153.6 | PASS with comments |
Test | L | M | F | SCR | K | Lane rate (Gbps) | ADC IQ rate (MSPS) | Link Clock (MHz) | Result |
---|---|---|---|---|---|---|---|---|---|
1 | 1 | 2 | 4 | 0 | 32 | 6.144 | 153.6 | 153.6 | Pass |
2 | 1 | 2 | 4 | 1 | 32 | 6.144 | 153.6 | 153.6 | Pass |
3 | 2 | 2 | 2 | 0 | 32 | 3.072 | 153.6 | 76.8 | Pass |
4 | 2 | 2 | 2 | 1 | 32 | 3.072 | 153.6 | 76.8 | Pass |
5 | 1 | 4 | 8 | 0 | 32 | 6.144 | 76.8 | 153.6 | Pass |
6 | 1 | 4 | 8 | 1 | 32 | 6.144 | 76.8 | 153.6 | Pass |
7 | 2 | 4 | 4 | 0 | 32 | 6.144 | 153.6 | 153.6 | Pass |
8 | 2 | 4 | 4 | 1 | 32 | 6.144 | 153.6 | 153.6 | Pass |
9 | 4 | 4 | 2 | 0 | 32 | 3.072 | 153.6 | 7.68 | Pass |
10 | 4 | 4 | 2 | 1 | 32 | 3.072 | 153.6 | 7.68 | Pass |
The following table shows the results for test cases DL.1 and DL.2 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies
Test | L | M | F | Sub- class | SCR | K | Transmitter Lane rate (Gbps) | Receiver Lane rate (Gbps) | SYSREF pulse frequency 15 (MHz) | Total Latency Result |
---|---|---|---|---|---|---|---|---|---|---|
1 | 1 | 2 | 4 | 1 | 1 | 32 | 6.144 | 6.144 | 0.48 | Pass (1.146 us) |
2 | 2 | 2 | 2 | 1 | 1 | 32 | 6.144 | 3.072 | 0.48 | Pass (1.328-1.341 us) |
3 | 4 | 2 | 1 | 1 | 1 | 32 | 3.072 | -16 | 0.48 | Pass 16
(0.651-0.657 us) |
4 | 1 | 4 | 8 | 1 | 1 | 32 | 6.144 | 6.144 | 0.48 | Pass (2.331 us) |
5 | 2 | 4 | 4 | 1 | 1 | 32 | 6.144 | 6.144 | 0.48 | Pass (1.133-1.146 us) |
6 | 4 | 4 | 2 | 1 | 1 | 32 | 6.144 | 3.072 | 0.48 | Pass (1.328-1.354 us) |





Test Result Comments
In each test case, both the JESD204B transmitter and JESD204B receiver IP core successfully initialize from CGS phase, ILAS phase, and until user data phase.
The test results for JESD204B transmitter are marked with Pass with comments because the deframer of AD9371 raises IRQ due to ILAS configuration mismatch. The conflicting ILAS parameters are N value and CS value. The AD9371 deframer register contains the following JESD204B parameter values N=14 and CS=2 while FPGA transmits ILAS with following JESD204B parameter N=16 and CS=0. The FPGA is configured with JESD204B parameters as per values defined in AD9371-User-Guide-UG-992 document available at the time of testing (refer Figure 15). Otherwise the behavior of the JESD204B transmitter IP core meets the passing criteria.

The monotone sine wave from FPGA is transmitted into RF domain successfully at desired frequency and when loopbacked into ADC, the original monotone sine wave is received back.
In the deterministic latency measurement, consistent total latency is observed across the JESD204B transmitter link and JESD204B receiver link.
Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Date | Version | Changes |
---|---|---|
December 2017 | 2017.12.18 |
|
May 2017 | 2017.05.08 | Initial release. |