AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

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AN-749 | 2015.12.18

Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) DAC (digital-to-analog) devices.

This report highlights the interoperability of the JESD204B IP core with the AD9144 converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results.

Hardware Requirements

The hardware checkout test requires the following hardware tools:

Arria 10 GX FPGA Development Kit
ADI AD9144 Evaluation Board (AD9144-FMC-EBZ)
Mini-USB cable
SMA Cable

Hardware Setup

Figure 1. Hardware Setup. The ADI AD9144 daughter card module connects to the Arria 10 GX development board’s FMC connector.

The AD9144 EVM derives power from the Arria 10 FMC port.
A reference clock, which is equal to the DAC sampling clock, is provided to the DAC through SMA pin J1. An internal clock source (AD9516-1) present on the DAC EVM uses this reference and provides the device clock to both the DAC and FPGA.
For subclass 1, the AD9516-1 clock generator generates SYSREF for the JESD204B IP core as well as the AD9144 device.
The sync_n signal is also transmitted from the AD9144 to FPGA through the FMC pins.
To configure the DAC using SPI over FMC, short the pads at JP3 by soldering it. The location of JP3 is beside XP1 header. In addition, the PIC controller must be held in reset by putting a jumper at pin 5 and 6 of the XP1 header.

Figure 2. System-Level Block Diagram. The system-level block diagram shows how different modules connect in this design.

In this setup, where the LMF=841, the data rate of transceiver lanes is 9.8304 Gbps. A clock source on the EVM (AD9516) provides 245.76 MHz clock to the FPGA and 983.04 MHz sampling clock to the AD9144. The AD9516 provides SYSREF pulses to both the AD9144 and FPGA. The AD9144 provides the sync_n signal through the FMC pins. The AD9144 operates in LINK0 only mode (single link) in all configurations.

Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria.

The test covers the following areas:

Transmitter data link layer
Transmitter transport layer
Scrambling
Deterministic latency (Subclass 1)

Transmitter Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial lane alignment sequence.

On link start-up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool monitors the transmitter data link layer operation.

Code Group Synchronization (CGS)

Table 1. CGS Test Cases
Test Case	Objective	Description	Passing Criteria
CGS.1	Check that /K/ characters are transmitted when `sync_n` signal is asserted.	The following signals in <ip_variant_name>_inst_phy.v are tapped: `jesd204_tx_pcs_data[(L32)-1:0]` `jesd204_tx_pcs_kchar_data[(L4)-1:0]` The following signals in <ip_variant_name>.v are tapped: `sync_n` `jesd204_tx_int` The `txlink_clk` is used as the sampling clock for the SignalTap II . Each lane is represented by a 32-bit data bus in the `jesd204_tx_pcs_data` signal. The 32-bit data bus is divided into 4 octets. Check the following error in the AD9144 register: Code Group Synchronization Status	/K/ character or K28.5 (0xBC) is transmitted at each octet of the `jesd204_tx_pcs_data` bus when the receiver asserts the `sync_n` signal. The `jesd204_tx_pcs_kchar_data` signal is asserted whenever control characters like /K/ are transmitted. The `jesd204_tx_int` signal is deasserted if there is no error. The “Code Group Synchronization Status” for all lanes should be asserted in AD9144 register 0x470.
CGS.2	Check that /K/ characters are transmitted after `sync_n` is deasserted but before the start of multiframe.	The following signals in <ip_variant_name>_inst_phy.v are tapped: `jesd204_tx_pcs_data[(L32)-1:0]` `jesd204_tx_pcs_kchar_data[(L4)-1:0]` ¹ The following signals in <ip_variant_name>.v are tapped: `sync_n` `tx_sysref` `jesd204_tx_int` The `txlink_clk` is used as the sampling clock for the SignalTap II . Each lane is represented by a 32-bit data bus in the `jesd204_tx_pcs_data` signal. The 32-bit data bus is divided into 4 octets. Check the following error in the AD9144 register: 8b/10b Not-in-Table Error 8b/10b Disparity Error	The /K/ character transmission continues for at least 1 frame plus 9 octets. The `sync_n` and `jesd204_tx_int` signals are deasserted. The “8b/10b Not-in-Table Error” and “8b/10b Disparity Error” bit in the AD9144 registers 0x46E and 0x46D are not asserted.

¹ L denotes the number of lanes.

Initial Frame and Lane Synchronization

Table 2. Initial Frame and Lane Synchronization Test Cases
Test Case	Objective	Description	Passing Criteria
ILA.1	Check that the /R/ and /A/ characters are transmitted at the beginning and end of each multiframe. Verify that four multiframes are transmitted in ILAS phase and the receiver detects the initial lane alignment sequence correctly.	The following signals in <ip_variant_name>_inst_phy.v are tapped: `jesd204_tx_pcs_data[(L32)-1:0]` `jesd204_tx_pcs_kchar_data[(L4)-1:0]` The following signals in <ip_variant_name>.v are tapped: `sync_n` `jesd204_tx_int` The `txlink_clk` is used as the sampling clock for the SignalTap II. Each lane is represented by a 32-bit data bus in the `jesd204_tx_pcs_data`signal. The 32-bit data bus is divided into 4 octets. Check the following errors in the AD9144 registers: Frame Synchronization Initial Lane Synchronization	The /R/ character or K28.0 (0x1C) is transmitted at the `jesd204_tx_pcs_data` bus to mark the beginning of multiframe. The /A/ character or K28.3 (0x7C) is transmitted at the `jesd204_tx_pcs_data` bus to mark the end of each multiframe. The `sync_n` and `jesd204_tx_int` signals are deasserted. The `jesd204_tx_pcs_kchar_data` signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are transmitted. The “Frame and Initial Lane Synchronization” status for all lanes are asserted in the AD9144 registers 0x471 and 0x473 respectively.
ILA.2	Check that the JESD204B configuration parameters are transmitted in the second multiframe.	The following signals in <ip_variant_name>_inst_phy.v are tapped: `jesd204_tx_pcs_data[(L32)-1:0]` ² The following signal in <ip_variant_name*>.v is tapped: `jesd204_tx_int` The `txlink_clk` is used as the sampling clock for the SignalTap II. The system console accesses the following registers: ilas_data1 ilas_data2 The content of 14 configuration octets in the second multiframe is stored in the above 32-bit registers. Check the following error in the AD9144 register: Configuration Mismatch Error	The /R/ character is followed by /Q/ character or K28.4 (0x9C) in the `jesd204_tx_pcs_data` signal at the beginning of the second multiframe. The `jesd204_tx_int` is deasserted if there is no error. The JESD204B parameters read from ilas_data1 and ilas_data2 registers are the same as the parameters set in the JESD204B IP core Qsys parameter editor. The “Link Configuration Mismatch Error” bit n the AD9144 register 0x47B is not asserted.
ILA.3	Check the constant pattern of transmitted user data after the end of the 4^th multiframes. Verify that the receiver successfully enters user data phase.	The following signals in <ip_variant_name>_inst_phy.v are tapped: `jesd204_tx_pcs_data[(L32)-1:0]` ² The following signal in <ip_variant_name*>.v is tapped: `jesd204_tx_int` The `txlink_clk` is used as the sampling clock for the SignalTap II. The system console accesses the `tx_err` register. Check the following errors in the AD9144 register: Lane FIFO Full Lane FIFO Empty	When scrambler is turned off, the first user data is transmitted after the last /A/ character, which marks the end of the 4^th multiframe transmitted. ³ Bits 2 and 3 of the `tx_err` register are not set to “1”. The “Lane FIFO Full” and “Lane FIFO Empty” in the AD9144 registers 0x30C and 0x30D are not asserted. The `jesd204_tx_int` is deasserted if there is no error.

² L denotes the number of lanes.

³ When the scrambler is turned on, the data pattern cannot be recognized after the 4^th multiframe in the ILAS phase.

Transmitter Transport Layer

To verify the data integrity of the payload data stream through the TX JESD204B IP core and transport layer, the DAC's JESD core is configured to check either the PRBS test pattern that the FPGA's test pattern generator transmits. The DAC JESD core checks the transport layer test patterns based on F = 1, 2, 4, or 8 configuration. You can check the DAC registers 0x14C and 0x14D for individual DAC’s error status.

To verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a sinewave. Connect an oscilloscope to observe the waveform at the DAC analog channels.

Figure 3. Data Integrity Check Block Diagram. This figure shows the conceptual test setup for data integrity checking.

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

Table 3. Transport Layer Test Cases
Test Case	Objective	Description	Passing Criteria
TL.1	Check the transport layer mapping using PRBS-7 test pattern.	The following signals in altera_jesd204_transport_tx_top.sv are tapped: `jesd204_tx_data_valid` `jesd204_tx_data_ready` The following signal in jesd204b_ed.sv is tapped: `jesd204_tx_int` The `txframe_clk` is used as the sampling clock for the SignalTap II. Check the following error in the AD9144 register: PRBS Error	The `jesd204_tx_data_valid` and `jesd204_tx_data_ready` signals are asserted. The PRBS Error bit in the AD9144 registers 0x14C and 0x14D are deasserted. The `jesd204_tx_int` signal is also deasserted.
TL.2	Verify the data transfer from digital to analog domain.	Enable sinewave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.	A monotone sinewave is observed on the oscilloscope.

Scrambling

With descrambler enabled, the transport layer test pattern checker at the DAC JESD core checks the data integrity of the scrambler in the FPGA.

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

Table 4. Scrambler Test Cases
Test Case	Objective	Description	Passing Criteria
SCR.1	Check the functionality of the scrambler using PRBS test pattern.	Enable descrambler at the DAC and scrambler at the TX JESD204B IP core. The signals that are tapped in this test case are similar to test case TL.1. Check the following error in the AD9144 register: PRBS Error	The `jesd204_tx_data_ready` and `jesd204_tx_data_valid` signals are asserted. The PRBS Error bit in the AD9144 registers 0x14C and 0x14D are deasserted.The `jesd204_tx_int` signal is also deasserted.
SCR.2	Verify the data transfer from digital to analog domain.	Enable descrambler at the DAC JESD core and scrambler at the TX JESD204B IP core. Enable sinewave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.	A monotone sinewave is observed on the oscilloscope.

Deterministic Latency (Subclass 1)

Figure below shows a block diagram of the deterministic latency test setup. The AD9516-1 clock generator on the AD9144 EVM provides periodic SYSREF pulses for both the DAC and JESD204B IP core. The period of SYSREF pulses is configured to two Local Multi Frame Clocks (LMFC). The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

Figure 4. Deterministic Latency Test Setup Block Diagram

The FPGA generates a 16-bit digital sample with a value of 8000 hexadecimal number at the transport layer. The most significant bit of this digital sample has a logic 1 and this bit is an output pin at the FPGA. This bit is probed at channel 1 of the oscilloscope. The DAC analog channel is probed at channel 2 of the oscilloscope. With two's complement value of 8000h, a pulse with the amplitude of negative full range is expected at channel 1 of the DAC analog. The time difference between the pulses at channel 1 (t0) and channel 2 (t1) is measured. This is the total latency of the JESD204B link, the DAC digital blocks, and the analog channel.

Table 5. Deterministic Latency Test Cases
Test Case	Objective	Description	Passing Criteria
DL.1	Measure the total latency.	Measure the time difference between the rising edge of pulses at oscilloscope channel 1 and 2.	The latency should be consistent.
DL.2	Re-measure the total latency after DAC power cycle and FPGA reconfiguration.	Measure the time difference between the rising edge of pulses at oscilloscope channel 1 and 2.	The latency should be consistent.

JESD204B IP Core and AD9144 Configurations

The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9144 device's configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9144 operating conditions.

The hardware checkout testing implements the JESD204B IP core with the following parameter configuration.

Table 6. Parameter Configuration
Configuration	Mode	Mode	Mode	Mode	Mode	Mode	Mode	Mode	Mode	Mode
LMF	841	842	442	244	421	422	222	124	211	112
HD	1	0	0	0	1	0	0	0	1	0
S	1	2	1	1	1	2	1	1	1	1
N	16	16	16	16	16	16	16	16	16	16
N’	16	16	16	16	16	16	16	16	16	16
CS	0	0	0	0	0	0	0	0	0	0
CF	0	0	0	0	0	0	0	0	0	0
DAC Sampling Clock (MHz)	983.04	983.04	491.52	245.76	983.04	983.04	491.52	245.76	983.04	491.52
FPGA Device Clock (MHz) ⁴	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76
FPGA Management Clock (MHz)	100	100	100	100	100	100	100	100	100	100
FPGA Frame Clock (MHz)	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76
FPGA Link Clock (MHz) ⁵	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76	245.76
Character Replacement	Enabled	Enabled	Enabled	Enabled	Enabled	Enabled	Enabled	Enabled	Enabled	Enabled
Data Pattern	PRBS-7 Sine ⁶ Single Pulse ⁷

⁴ The device clock is used to clock the transceiver.

⁵ The frame clock and link clock are derived from the device clock using an internal PLL.

⁶ The sinewave pattern is used in TL.2 and SCR.2 test cases to verify that the pattern generated in the FPGA transport layer is transmitted by the DAC analog channel.

⁷ The single pulse pattern is used in deterministic latency measurement test cases DL.1 and DL.2 only.

Test Results

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 7. Test Results
Test	L	M	F	Subclass	SCR	K	Lane rate (Mbps)	Sampling Clock (MHz)	Link Clock (MHz)	Results
1	8	4	1	1	0	32	9830.4	983.04	245.76	PASS with comments
2	8	4	1	1	1	32	9830.4	983.04	245.76	PASS with comments
3	8	4	2	1	0	16	9830.4	983.04	245.76	PASS with comments
4	8	4	2	1	1	16	9830.4	983.04	245.76	PASS with comments
5	8	4	2	1	0	32	9830.4	983.04	245.76	PASS with comments
6	8	4	2	1	1	32	9830.4	983.04	245.76	PASS with comments
7	4	4	2	1	0	16	9830.4	491.52	245.76	PASS
8	4	4	2	1	1	16	9830.4	491.52	245.76	PASS
9	4	4	2	1	0	32	9830.4	491.52	245.76	PASS
10	4	4	2	1	1	32	9830.4	491.52	245.76	PASS
11	2	4	4	1	0	16	9830.4	245.76	245.76	PASS
12	2	4	4	1	1	16	9830.4	245.76	245.76	PASS
13	2	4	4	1	0	32	9830.4	245.76	245.76	PASS
14	2	4	4	1	1	32	9830.4	245.76	245.76	PASS
15	4	2	1	1	0	32	9830.4	983.04	245.76	PASS
16	4	2	1	1	1	32	9830.4	983.04	245.76	PASS
17	4	2	2	1	0	16	9830.4	983.04	245.76	PASS
18	4	2	2	1	1	16	9830.4	983.04	245.76	PASS
19	4	2	2	1	0	32	9830.4	983.04	245.76	PASS
20	4	2	2	1	1	32	9830.4	983.04	245.76	PASS
21	2	2	2	1	0	16	9830.4	491.52	245.76	PASS
22	2	2	2	1	1	16	9830.4	491.52	245.76	PASS
23	2	2	2	1	0	32	9830.4	491.52	245.76	PASS
24	2	2	2	1	1	32	9830.4	491.52	245.76	PASS
25	1	2	4	1	0	16	9830.4	245.76	245.76	PASS
26	1	2	4	1	1	16	9830.4	245.76	245.76	PASS
27	1	2	4	1	0	32	9830.4	245.76	245.76	PASS
28	1	2	4	1	1	32	9830.4	245.76	245.76	PASS
29	2	1	1	1	0	32	9830.4	983.04	245.76	PASS
30	2	1	1	1	1	32	9830.4	983.04	245.76	PASS
31	1	1	2	1	0	16	9830.4	491.52	245.76	PASS
32	1	1	2	1	1	16	9830.4	491.52	245.76	PASS
33	1	1	2	1	0	32	9830.4	491.52	245.76	PASS
34	1	1	2	1	1	32	9830.4	491.52	245.76	PASS

Figure 5. Sinewave Output from DAC Analog Channel

Table 8. Deterministic Latency Test Results
Test	L	M	F	Subclass	SCR	K	Lane rate (Mbps)	Sampling Clock (MHz)	Link Clock (MHz)	Allowed Deviation (ns)	Total Latency Result (ns)
1	8	4	1	1	1	32	9830.4	983.04	245.76	2.54	PASS with comments (206.6-208.9)
2	8	4	2	1	1	16	9830.4	983.04	245.76	2.54	PASS with comments (214.6-216.9)
3	8	4	2	1	1	32	9830.4	983.04	245.76	2.54	PASS with comments (209.9-212.2)
4	4	4	2	1	1	16	9830.4	491.52	245.76	3.05	PASS with comments (300.7-302.9)
5	4	4	2	1	1	32	9830.4	491.52	245.76	3.05	PASS with comments (300.8-303.1)
6	2	4	4	1	1	16	9830.4	245.76	245.76	4.07	PASS (483.6-483.8)
7	2	4	4	1	1	32	9830.4	245.76	245.76	4.07	PASS (479.3-479.6)
8	4	2	1	1	1	32	9830.4	983.04	245.76	2.54	PASS with comments (210.8-212.9)
9	4	2	2	1	1	16	9830.4	983.04	245.76	2.54	PASS with comments (208.2-210.5)
10	4	2	2	1	1	32	9830.4	983.04	245.76	2.54	PASS with comments (209.6-211.9)
11	2	2	2	1	1	16	9830.4	491.52	245.76	3.05	PASS with comments (300.8-303.1)
12	2	2	2	1	1	32	9830.4	491.52	245.76	3.05	PASS with comments (298.6-300.8)
13	1	2	4	1	1	16	9830.4	245.76	245.76	4.07	PASS (483.3-483.5)
14	1	2	4	1	1	32	9830.4	245.76	245.76	4.07	PASS (477.5-477.8)
15	2	1	1	1	1	32	9830.4	983.04	245.76	2.54	PASS with comments (208.0-210.2)
16	1	1	2	1	1	16	9830.4	491.52	245.76	3.05	PASS with comments (301.3-303.5)
17	1	1	2	1	1	32	9830.4	491.52	245.76	3.05	PASS with comments (297.3-300.0)

Figure 6. Time Difference Between Pulses in Deterministic Latency Measurement for LMF = 422 Configuration

Test Results Comments

In each test case, the TX JESD204B IP core successfully initializes from CGS phase, ILA phase, and until user data phase.

Data integrity is checked at the DAC datapath layer using the PRBS-7 pattern. The datapath PRBS can verify that the AD9144 datapath receives and correctly decodes the data. The datapath PRBS can also verify these processes:

the JESD204B parameters of the transmitter and receiver matched
the lanes of the receiver are mapped appropriately
the lanes have been appropriately inverted, if necessary
the start-up routine has been implemented correctly

Sinewave is observed at all four analog channels when sinewave generators in the FPGA are enabled. The data integrity test is also carried out for different link resets, where the PRBS checker is reinitialized and the status is checked. It is observed that if the LMFC Var and LMFC Del registers at the DAC side are not correctly configured, then it leads to random PRBS test failures. Hence, these registers are fine-tuned by reading registers DYN_LINK_LATENCY_x (DAC register 0x302 and 0x303). By repeatedly power-cycling and taking this measurement, the minimum and maximum delays across power cycles can be determined and used to calculate LMFC Var and LMFC Del. For information on how to calculate these register values, refer AD9144 datasheet. Setting LMFC Del appropriately ensures that all the corresponding data samples arrive in the same LMFC period. Then, LMFC Var is written into the receive buffer delay (RBD) to absorb all link delay variation. This ensures that all data samples have arrived before reading. By setting these to fixed values across runs and devices, deterministic latency is achieved. The following table gives the calculated LMFC Var and LMFC Del for each mode. The same values are also programmed in the scripts corresponding to each mode.

S. No.	L	M	F	K	Lane rate (Mbps)	Sampling Clock (MHz)	Link Clock (MHz)	LMFC Var	LMFC Del
1	8	4	1	32	9830.4	983.04	245.76	0x6	0
2	8	4	2	16	9830.4	983.04	245.76	0x7	0
3	8	4	2	32	9830.4	983.04	245.76	0x7	0xE
4	4	4	2	16	9830.4	491.52	245.76	0x6	0
5	4	4	2	32	9830.4	491.52	245.76	0x7	0xC
6	2	4	4	16	9830.4	245.76	245.76	0x5	0x7
7	2	4	4	32	9830.4	245.76	245.76	0x6	0x16
8	4	2	1	32	9830.4	983.04	245.76	0x6	0x4
9	4	2	2	16	9830.4	983.04	245.76	0x7	0
10	4	2	2	32	9830.4	983.04	245.76	0x6	0x10
11	2	2	2	16	9830.4	491.52	245.76	0x6	0
12	2	2	2	32	9830.4	491.52	245.76	0x5	0x10
13	1	2	4	16	9830.4	245.76	245.76	0x5	0x7
14	1	2	4	32	9830.4	245.76	245.76	0x5	0x18
15	2	1	1	32	9830.4	983.04	245.76	0x6	0x4
16	1	1	2	16	9830.4	491.52	245.76	0x6	0
17	1	1	2	32	9830.4	491.52	245.76	0x4	0x12

Also, using normal equalization mode at the DAC to compensate for the insertion loss of up to 17.5 dB helps improve the data integrity test results. After these changes (LMFC registers and equalization), no data integrity issue is observed from the datapath layer of PRBS test at the DAC JESD core except in the modes LMF =841 and LMF=842. In these modes, the datapath PRBS fails, but very rarely. The PRBS test fails about 2-4 times out of 50 PRBS tests across different link resets. This behavior is not observed in any of the other modes. Hence these modes (LMF=841 & 842) are given a status of ‘PASS with comments’ in the test results table.

In deterministic latency test, there is consistent total latency across the JESD204B link and DAC analog channels. But in most of the LMF modes, about 2.2 ns mean variation in the DL is observed. For the latency to be deterministic, it is important that the SYSREF gets sampled at the same time at both the DAC and FPGA, and each SYSREF needs to be phase aligned at the same LMFC boundary.

Document Revision History

Table 9. Document Revision History
Date	Version	Changes
December 2015	2015.12.18	Initial release.