• RTL State Machine Control (supports Arria V, Cyclone V, Stratix V, and Arria 10 devices only)
• Nios II Control (supports Arria 10 devices only)

You can generate these JESD204B IP core design examples through the IP catalog in the Intel^® Quartus^® Prime Standard Edition software only.

The JESD204B IP core provides the capability of generating design examples for selected configurations.

Follow these steps to compile and test the design in hardware:

1. Launch the Intel^® Quartus^® Prime software and compile the design (Processing> Start Compilation).

   The timing constraints for the design example and the design components are automatically loaded during compilation.

2. Connect the development board to the host computer.
3. Configure the FPGA on the development board using the generated .sof file (Tools> Programmer).

   The Intel^® Quartus^® Prime version 15.1 only supports programming file generation for Arria 10 engineering devices. For more information on support for Arria 10 production devices, contact Intel.

For details on how to implement the JESD204B design example on the Arria 10 GX FPGA Development Kit, refer to Implementing the Design on the Development Kit.

The parameter values chosen for the presets belong to the group of supported JESD204B IP configurations for design example generation. You can select one of the presets available for your target device to quickly generate a design example without having to manually set each parameter in the IP tab and verifying that the parameter matches the supported configurations set. There are two preset settings available in the library:

• RTL State Machine Control example design
• Nios II Control example design

Follow the steps below to launch the design example GUI and generate the design example.

1. In the IP Catalog (Tools > IP Catalog), select the JESD204B IP core.
2. Specify an entity name and location for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Intel^® FPGA device family. Click OK.
3. In the parameter editor, click on the IP tab and set the JESD204B IP core parameters as per your specifications. If you want to pre-fill the parameters with the set of parameter values that result in a valid example design, use the presets in the Presets tab. Refer to Presets for more details.
4. In the parameter editor, click on the Example Design tab.
5. Under the Available Example Designs section, select the available designs. The options you can select are based on the design examples that are available.
   • None: No design example available that matches the IP parameters selected.
   • RTL State Machine Control: Design example has RTL state machine as control unit.
   • Nios II Control: Design example has Nios II processor as control unit. This option is available for Arria 10 devices only.
6. If the Select Design option under the Available Example Designs section displays None, the Generate generic example design selection appears. In the Generate generic example design list, select one of the options available to generate a generic design example.
   • No: No generic design example will be generated.
   • Generic RTL State Machine Control: Generic design example has RTL state machine as control unit.
   • Generic Nios Control: Generic design example has Nios II processor as control unit. This option is available for Arria 10 devices only.
   Note: The generic design example parameter selection may not match the parameters that you selected in the IP tab. You can modify the generated generic design example files to match your desired IP parameter settings.
7. Under the Example Design Files section, select the desired design example files. The options you can select are based on the design examples that are available.
   • Simulation: Generate simulation files.
   • Synthesis: Generate synthesis files.
8. Under the Generated HDL Format for Simulation section (only available if the Simulation option is checked), select the desired HDL format. The options you can select are based on the design examples that are available.
9. Under the Generated HDL Format for Synthesis section (only available if the Synthesis option is checked), select the desired HDL format. The options you can select are based on the design examples that are available.
10. Under the Target Development Kit section, select the development kit that the design example will target. The options you can select are based on the design example that are available.
    • None: Design example does not target any board. The target device is set to a default device and may not match your selected target device in the Quartus project.
    • Arria 10 GX FPGA Development Kit: Design example is targeted for Arria 10 GX FPGA development kit. This option is available for Arria 10 devices only. The target device is Arria 10 GX FPGA and may not match your selected target device in the Quartus project.
    Note: The hardware example design targets an Arria 10 ES3 device. It cannot function correctly on an Arria 10 production device.
11. Click the Generate Example Design button on the top right corner to generate the design example based on your settings.
    1. If the selected design example in step 5 is None, and the generate generic design example selection in step 6 is No, an error message is displayed and no design example will be generated.
    2. If the selected design example in step 5 is RTL State Machine Control or Nios II Control, the relevant design example is generated with the JESD204B parameters matching the JESD204B IP parameter settings in the IP tab.
    3. If the selected design example in step 5 is None, and the generate generic design example selection from Step 6 is Generic RTL State Machine Control or Generic Nios II Control, the relevant generic design example is generated with the pre-set JESD204B parameters. You can then modify the JESD204B parameters directly in the generated design files to match your desired parameter settings.

The design example files are generated in the folder that you specified when you clicked on Generate Example Design. This is a self-contained design example folder that is in the same directory that contains the generated IP files. All the files necessary to compile and run the design example, including an independently generated JESD204B IP core module that is separate from the core module generated from the IP tab is stored in this folder and its sub directories.

This design example with RTL state machine control unit is the legacy design example that was first released in Quartus II version 13.1. The design example has the following key features:

• Supports Arria V, Cyclone V, Stratix V, and Arria 10 devices.
• Purely hardware-implemented control path, no software control features.
• Lower FPGA core resource utilization compared to Nios II processor control unit design example.
• Available as a synthesizable design entity and a simulation model.

The design example entity consists of various components that interface with the JESD204B IP core to demonstrate the following features:

• single or multiple link configuration
• different LMF settings with scrambling and internal serial loopback enabled
• interoperability against diverse converter devices
• dynamic reconfiguration

The list below describes the mechanism of the design example architecture (with reference to the note numbers in the design example block diagram).

1. For multiple links, the JESD204B IP core is instantiated multiple times. For example, in 2x112 (LMF) configuration, two cores are instantiated, where each core is configured at LMF=112.
2. The number of pattern generator or pattern checker instances is equivalent to the parameter value of LINK. The data bus width per instance is equivalent to the value of FRAMECLK_DIV*M*S*N.
3. The number of transport layer instances is equivalent to the parameter value of LINK. The legal value of LINK is 1 and 2. The data bus width per instance is equivalent to the value of FRAMECLK_DIV*M*S*N. The test_mode = 0 signal indicates a normal operation mode, where the assembler takes data from the Avalon-ST source. Otherwise, the assembler takes data from the pattern generator.
4. The Avalon-ST interface data bus is fixed at 32-bit. The number of 32-bit data bus is equal to the number of lanes (L).
5. The number of lanes per converter device (L).
6. You can enable internal serial loopback by setting the rx_seriallpbken input signal. You can dynamically toggle this input signal. When toggled to 1, the RX path takes the serial input from the TX path internally in the FPGA. When toggled to 0, the RX path takes the serial input from the external converter device. During internal serial loopback mode, the assembler takes input from the pattern generator.
7. A single serial port interface (SPI) master instance can control multiple SPI slaves. The SPI master is a 4-wire instance. If the SPI slave is a 3-wire instance, use a bidirectional I/O buffer in between the master and slave to interface the 4-wire master to 3-wire slave.
8. The SPI protocol interface. All slaves share the same data lines (MISO and MOSI, or DATAIO). Each slave has its own slave select or chip select line (SS_n).
9. The PLL takes the device clock from an external clock chip as the input reference. The PLL generates two output clocks (utilizing two output counters from a single VCO). Clock 1 is the frame clock for the transport layer, pattern generator, and pattern checker. Clock 2 is the link clock for the transport and link layer.
10. The control unit implements a memory initialization file (MIF) method for configuring the SPI. Each MIF corresponds to a separate external converter per device or clock chip. For example, in a system that interacts with both DAC and ADC, two MIFs are needed—one each for DAC and ADC.
11. The PLL reconfiguration and transceiver reconfiguration controller instances are only required for run time reconfiguration of the data rate.

The RTL State Machine Control Unit design example for the JESD204B IP core consists of the following components:

• PLL
• PLL reconfiguration
• Transceiver reconfiguration controller
• Transceiver reset controller
• Pattern generator
• Pattern checker
• Assembler and deassembler (in the transport layer)
• SPI
• Control unit

The following sections describe in detail the function of each component.

Typically, the device clock is generated from an external converter or a clock device while the management clock (AVS clock) is generated from an on-board 100 MHz oscillator.

For instance, if the JESD204B IP core is configured at data rate of 6.144 Gbps, transceiver reference clock frequency of 153.6 MHz, and number of octets per frame (F) = 2, the example below indicates the PLL clock frequencies:

• device clock = transceiver reference clock frequency = 153.6 MHz
• link clock = 6144 / 40 = 153.6 MHz
• frame clock = 153.6 x 32 / (8 x 2) = 307.2 MHz

The PLL reconfiguration utilizes the ALTERA_PLL_RECONFIG IP core to implement reconfiguration logic to facilitate dynamic real-time reconfiguration of PLLs in Intel^® FPGA devices. You can use this megafunction IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA.

The design example uses the MIF approach to reconfigure the core PLL. The ALTERA_PLL_RECONFIG IP core has two parameter options—Enable MIF Streaming and Path to MIF file—for the MIF input. Turn on Enable MIF Streaming option and set the core_pll.mif as the value to Path to MIF file parameter.

The following PLL reconfiguration Avalon-MM operations occurs during data rate reconfiguration.

The transceiver reconfiguration controller allows you to change the device transceiver settings at any time. Any portion of the transceiver can be selectively reconfigured. Each portion of the reconfiguration requires a read-modify-write operation (read first, then write), in such a way that it modifies only the appropriate bits in a register and not changing other bits.

In the design example, MIF approach is used to reconfigure the ATX PLL and transceiver channel in the JESD204 IP core via the Transceiver Reconfiguration Controller. The number of reconfiguration interface is determined by number of lanes (L) + number of TX_PLL (different number of TX_PLL for bonded and non-bonded mode). Since the MIF approach reconfiguration for transceiver only supports non-bonded mode, the number of TX_PLL is equal to number of lanes. The number of reconfiguration interface = 2 x number of lanes (L).

The transceiver reconfiguration controller interfaces:

• MIF Reconfiguration Avalon-MM master interface—connects to the MIF ROM.
• Transceiver Reconfiguration interface—connects to the JESD204B IP core, which eventually connects to the native PHY.
• Reconfiguration Management Avalon-MM slave interface—connects to the control unit.

The following transceiver reconfiguration controller Avalon-MM operations are involved during data rate reconfiguration.

For Arria 10 devices, the only Avalon-MM operation is a direct write to the transceiver register through the reconfig_avmm_* interface at the JESD204B IP core. Every line in the MIF is DPRIO_ADDR[25:16]+ BIT_MASK[15:8]+ DATA[7:0]. The control unit maps the DPRIO_ADDR to reconfig_avmm_address and BIT_MASK + DATA to reconfig_avmm_data.

The transceiver reset controller uses the Altera's Transceiver PHY Reset Controller IP Core to ensure a reliable initialization of the transceiver. The reset controller has separate reset controls per channel to handle synchronization of reset inputs, hysteresis of PLL locked status, and automatic or manual reset recovery mode.

In this design example, the reset controller targets both the TX and RX channels. The TX PLL , TX Channel , and RX Channel parameters are programmable to accommodate single and multiple (2) JESD204B links.

The pattern generator can be a parallel PRBS, alternate checkerboard, or ramp wave generator. The data output bus width of the pattern generator is equivalent to the value of FRAMECLK_DIV × M × S × N.

For example, when M=2, S=1, N=16, F1/F2_FRAMECLK_DIV=1, the input or output data width equals to [31:0], with the following data arrangement:

• 0: {m1s0[31:16], m0s0[15:0]}
• 1: {m0s0[31:16], m1s0[15:0]}

PRBS generator circuits often consists of simple shift registers with feedback that serve as test sources for serial data links. The output sequence is not truly random but repeats after 2^X–1 bits, where X denotes the length of the shift register. Polynomial notation—which the polynomial order corresponds to the length of the shift register and the period of PRBS—provides a method of describing the sequence.

The output sequence of subsequent N-bits sample is generated by inverting the previous N-bits (counting from LSB to MSB) of the same data pattern at that clock cycle. The first N-bits sample from LSB of the data pattern on next clock cycle is generated by inverting the last N-bits sample on the MSB of the data pattern on current clock cycle.

The output sequence of subsequent N-bits sample is an increment by one of the previous N-bits sample (counting from LSB to MSB) in the same data pattern at that clock cycle. The first N-bits sample from LSB of the data pattern on next clock cycle is generated by an increment by one of the last N-bits sample on the MSB of the data pattern on current clock cycle.

The pattern checker can be either a parallel PRBS checker, alternate checkerboard checker, or ramp wave checker. The data input bus width of the pattern checker is equivalent to the value of FRAMECLK_DIV × M × S × N.

The pattern checker includes an ERR_THRESHOLD parameter to control the number of error tolerance allowed in the checker. The default value of this parameter is 1.

The pattern checker also includes a REVERSE_DATA parameter to control data arrangement at the input. The default value of this parameter is 0.

• 0—no data rearrangement at the input of the checker.
• 1—data rearrangement at the input of the checker.

The PRBS checker contains the same polynomial as in the PRBS generator. The polynomial is only updated when the enable signal is active, which indicates that the input data is valid. The feedback path is XOR'ed with the input data to do a comparison. The checker flags an error when it finds any single mismatch between polynomial data and input data.

The alternate checkerboard checker is implemented in the same way as in the alternate checkerboard generator. To do a comparison, an initial seed internally generates a set of expected data pattern result to XOR'ed with the input data. The seed is updated only when the enable signal is active, which indicates that the input data is valid. The checker flags an error when it finds any single mismatch between the expected data and input data.

The ramp wave checker is implemented in the same way as in the ramp wave generator. To do a comparison, an initial seed internally generates a set of expected data pattern result to XOR'ed with the input data. The seed is updated only when the enable signal is active, which indicates that the input data is valid. The checker flags an error when it finds any single mismatch between the expected data and input data.

The transport layer provides the following services to the application layer (AL) and the DLL:

• The assembler at the TX path:
  • maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
  • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during TX data streaming.
• The deassembler at the RX path:
  • maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon-ST interface).
  • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during RX data streaming.

The transport layer supports static configurations where before compilation, you can modify the configurations using the IP core's parameter editor in the Intel^® Quartus^® Prime software. To change to another configuration, you have to recompile the design. The following list describes the supported configurations for the transport layer:

• Data rate (maximum) = 12.5 Gbps (F1_FRAMECLK_DIV = 4 and F2_FRAMECLK_DIV = 2)
• L = 1–8
• F = 1, 2, 4, 8
• N = 12, 13, 14, 15, 16
• N' = 16
• CS = 0–3
• CF = 0
• HD = 0 (for F=2, 4, 8), 1 (for F=1)

• Tail bits padding block—pads incoming data (jesd204_tx_datain) with "0" if N < 16, so that the padded data is 16 bits per sample.
• Assembling block—arranges the resulting data bits in a specific way according to the mapping scheme (refer to figure).
• Multiplexing block—sends the multiplexed data to the DLL interface, determined by certain control signals from the TX control block.

• Tail bit dropping block—drops padded tail bits in the incoming data (jesd204_rx_link_datain).
• Deassembling block—rearranges the resulting data bits in a specific way according to the mapping scheme (refer to figure).
• Multiplexing block—sends the multiplexed data to the Avalon-ST interface, determined by certain control signals from the RX control block.

An external converter device with a SPI allows you to configure the converter for specific functions or operations through a structured register space provided inside the converter device. The SPI gives flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from the port. The memory is organized into bytes that can be further divided into fields.

The SPI communicates using two data lines, a control line, and a synchronization clock. A single SPI master can work with multiple slaves. The SPI core logic is synchronous to the clock input provided by the Avalon-MM interface. When configured as a master, the core divides the Avalon-MM clock to generate the SCLK output.

The first 16 bits are instruction data. The first bit in the stream is the read or write indicator bit. This bit goes high to indicate a read request. W1 and W0 represent the number of data bytes to transfer for either a read or write process. For implementation simplicity, W1 and W0 are always set at 0 in this design example. The subsequent 13 bits represent the starting address of the data sent. The last 8 bits are register data.

For a 32-bit SPI transaction, each SPI programming cycle needs to be preceded with a preselection byte. The preselection byte is typically used to forward the SPI command to the right destination. figure shows the timing diagram of a 32-bit SPI transaction.

In this design example, the SPI core is configured as a 4-wire master protocol to control three independent SPI slaves—ADC, DAC, and clock devices. The width of the receive and transmit registers are configured at 32 bits. Data is sent in MSB-first mode in compliance with the converter device default power up mode. The SPI clock (sclk) rate is configured at a frequency of the SPI input clock rate divided by 5. If the SPI input clock rate is 100 MHz (in the mgmt_clock domain), the sclk rate is 20 MHz. If the external converter device's SPI interface is a 3-wire protocol without both MOSI (master output, slave input) and MISO (master input, slave output) lines but with a single DATAIO pin, you can use the ALTIOBUF Megafunction IP core (configured with bidirectional buffer) with the SPI master to convert the MOSI and MISO lines to a single DATAIO pin. The DATAIO pin can be dynamically reconfigured as MOSI by asserting the output enable (oe) signal or as MISO by deasserting the oe signal. For implementation simplicity, you can directly connect the master MOSI pin to the slave DATAIO pin if read transactions are not required.

The control unit replaces the software-based Nios II processor to perform device configuration and initialization on the JESD204B duplex base core. This configuration and initialization process includes the transceivers, transport layer, pattern generator and checker, external converters (ADC/DAC), and clock devices over the SPI interface.

Each ROM holds the configuration data required to configure the external converter or clock devices for each SPI slave. A memory initialization file (MIF) contains the initial values for each address in the memory. Each memory block requires a separate file. You can create the MIF using the text editor tool in the Intel^® Quartus^® Prime software.

The initial values for each address and sequence is defined based on the requirement of the external converter and clock devices. The example above is based on 24-bit SPI write-only programming.

Table below lists the configuration that this design example supports. However, the design example generated by the Qsys system is always fixed at a data rate of 6144 Mbps and a limited set of configuration as shown in the table below. If your setting in the Qsys parameter editor does not match one of the LMF and bonded mode parameter values in Table, the design example is generated with the default values of LMF = 124.

The dynamic reconfiguration feature implements various reconfiguration controller modules such as PLL reconfiguration, Transceiver Reconfiguration Controller, SPI master, and JESD204B IP core Avalon-MM slave. These modules connect to the control unit through the Avalon-MM interface. You can control the reconfiguration using the reconfig, runtime_lmf, and runtime_datarate input ports exposed at control unit interface.

The MIF ROM content for maximum and downscale configuration:

• PLL MIF ROM—contains the PLL counter, charge pump, and bandwidth setting.
• JESD MIF ROM—contains the LMF information.
• PHY MIF ROM—contains the transceiver channel and PLL setting.
• ADC MIF ROM—contains the ADC converter setting.
• DAC MIF ROM—contains the DAC converter setting.
• CLK MIF ROM—contains the device clock setting.

You need to generate two MIF files for each reconfigurable IP core as shown in Figure 1 or Figure 2, and merge them into a single MIF file for each IP core. The following section shows the MIF file format.

Maximum Configuration MIF
WIDTH=32;
DEPTH=92;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0   :   00000000000000000000000000111110; -- START OF MIF
	1   :   00000000000000000000000000000100;
	2   :   00000000000000000000000100000001;
	3   :   00000000000000000000000000000011;
.
.
.
 42  :   00000000000000000000000000000010;
	43  :   00000000000000000000000000001000;
	44  :   00000000000000000000000001000000;
	45  :   00000000000000000000000000111111; -- END OF MIF

Downscale Configuration MIF

 46  :   00000000000000000000000000111110; -- START OF MIF
	47  :   00000000000000000000000000000100;
	48  :   00000000000000000000000100000001;
	49  :   00000000000000000000000000000011;
.
.
.
 88  :   00000000000000000000000000000010;
	89  :   00000000000000000000000000001000;
	90  :   00000000000000000000000001000000;
	91  :   00000000000000000000000000111111; -- END OF MIF
END;

Maximum TX PLL Configuration MIF
WIDTH=16;
DEPTH=186;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0    :   0000000000100001; -- Start of MIF opcode (TX_PLL, 6144Mbps)
	1    :   0000000000100010;
.
.
.
 10   :   0011000000000000;
	11   :   0000000000011111; -- End of MIF opcode

Maximum Channel Configuration MIF

 12   :   0000000000100001; -- Start of MIF opcode (Channel, 6144Mbps)
	13   :   0000000000000010;
.
.
.
 [88..91]  :   0000000000000000;
	92   :   0000000000011111; -- End of MIF opcode

Downscale TX PLL Configuration MIF

 93   :   0000000000100001; -- Start of MIF opcode (TX_PLL, 3072Mbps)
	94   :   0000000000100010;
.
.
.
 103  :   0011000000000000;
	104  :   0000000000011111; -- End of MIF opcode

Downscale Channel Configuration MIF

 105  :   0000000000100001; -- Start of MIF opcode (Channel, 3072Mbps)
	106  :   0000000000000010;
.
.
.
 [181..184]  :   0000000000000000;
	185  :   0000000000011111; -- End of MIF opcode
END;

xcvr_atx_pll_combined.mif

Maximum Configuration MIF

CONTENT BEGIN
	00    :   102FF71; -- Start of MIF
	01    :   103BF01;
	02    :   1047F04;
	03    :   1054700;
.
.
.
 10   :   11AFF00;
	11   :   11CE020;
	12   :   11DE020;
	13   :   3FFFFFF; -- End of MIF

Downscale Channel Configuration MIF

	14    :   102FF71; -- Start of MIF
	15    :   103BF01;
	16    :   1047F04;
	17    :   1054700;
.
.
.
 24   :   11AFF00;
	25   :   11CE020;
	26   :   11DE020;
	27   :   3FFFFFF; -- End of MIF
END;

xcvr_cdr_combined.mif

Maximum Configuration MIF

CONTENT BEGIN
	00    :   006DF02; -- Start of MIF
	01    :   007FF09;
	02    :   008FF04;
	03    :   00AFF01;
.
.
.
 76   :   173FF31;
	77   :   1741F0C;
	78   :   1753F13;
	79   :   3FFFFFF; -- End of MIF

Downscale Channel Configuration MIF

	7A    :   006DF02; -- Start of MIF
	7B    :   007FF09;
	7C    :   008FF04;
	7D    :   00AFF01;
.
.
.
 F0   :   173FF31;
	F1   :   1741F0C;
	F2   :   1753F13;
	F3   :   3FFFFFF; -- End of MIF
END;

Maximum Configuration MIF
WIDTH=16;
DEPTH=16;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0    :   0000000000000001; -- L            (maximum config)
	1    :   0000000000000001; -- M
	2    :   0000000000000001; -- F
.
.
.
 3    :   1111111111111111; -- End of MIF
 [4..7]  :   0000000000000000; 

Downscale Configuration MIF

 8    :   0000000000000000; -- L            (downscale config)
 9    :   0000000000000000; -- M
 10   :   0000000000000001; -- F
.
.
.
 11   :   1111111111111111; -- End of MIF
 [12..15]  :   0000000000000000; 
END;

Maximum Configuration MIF
WIDTH=32;
DEPTH=128;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0   :   10000100000000000001000001111100;  -- (Maximum Config)
	1   :   10000100000000000001010000000101;  
	2   :   10000100000000000001011000000101;  
	3   :   10000100000000000001110000000010;  
.
.
.
 28  :   10000001000000001111111100000001;  
	29  :   10000001000000000101111100010100;  
	30  :   11111111111111111111111111111111;  -- End of MIF
	[31..63] :   00000000000000000000000000000000;

Downscale Configuration MIF

 64  :   10000100000000000001000001111100;   -- (downscale config)
 65  :   10000100000000000001010000000101;
 66  :   10000100000000000001011000000101;
 67  :   10000100000000000001110000000010;
.
.
.
 92  :   10000001000000001111111100000001; 
 93  :   10000001000000000101111100010100;
 94  :   11111111111111111111111111111111;  -- End of MIF
 95..127]  :   00000000000000000000000000000000;
END;

To use the JESD204B IP core design example testbench, follow these steps:

1. Generate the design example simulation testbench. Refer to Generating the Design Example Simulation Model
2. Simulate the design example using simulator-specific scripts. Refer to Simulating the JESD204B IP Core Design Example

Generate this design by selecting the Nios II Control option in the Example Designs tab of the parameter editor. You can also generate a generic design by selecting the Generic Nios II Control option in the Generate generic example design selection. This design example has the following key features:

• Supports Arria 10 devices only.
• C-based software control flow implemented on a Nios II soft core processor.
• Available as synthesizable design entity only.
  Note: No simulation model is provided for this design. If you need a design example that has a simulation model, use the RTL State Machine Control design example.

• Qsys system
  • JESD204B subsystem
  • Nios II subsystem
  • Core PLL
  • PLL reconfiguration controller
  • Serial Port Interface (SPI) – master module
• Test pattern generator
• Test pattern checker
• Assembler and deassembler (in the transport layer)

The following sections describe in detail the function of each component.

The Qsys system instantiates both the JESD204B IP core data path and the Nios II subsystem control path.

The top level Qsys system, jesd204b_ed_qsys.qsys, instantiates the following modules:

• JESD204B subsystem
• Nios II subsystem
• Core PLL
• PLL reconfiguration controller
• SPI master

The main data path flows through the JESD204B subsystem. In the example design, the JESD204B IP core is configured in duplex mode with both TX and RX data paths. On the TX data path, user data flows from the transport layer through the JESD204B IP core base module via a 32-bit per transceiver lane Avalon Streaming (Avalon-ST) interface and out as serial data to the external converters via the JESD204B IP core PHY module. On the RX data path, serial data flows from the external converters (or from the TX data path, in internal serial loopback mode) to the JESD204B IP core PHY module and out from the JESD204B IP core base module to the transport layer via a 32-bit per transceiver lane Avalon-ST interface.

The control path is centered on the Nios II processor in the Nios II subsystem and connects to various peripherals via the Avalon Memory-Mapped (Avalon-MM) interface. A secondary control path from the SPI master module links out to the SPI configuration interface of external converters via a 4-wire SPI interconnect. The configuration of the external converters is done by writing configuration data from the Nios II processor to the SPI master module. The SPI master module handles the serial transfer of data to the SPI interface on the converter end via the 4-wire SPI interconnect.

The core PLL generates the link clock and frame clock for the system. During a data rate dynamic reconfiguration process, the core PLL is dynamically reconfigurable at run time via the PLL reconfiguration controller.

To view the top level Qsys system in Qsys, follow these steps:

1. Launch the Intel^® Quartus^® Prime software.
2. On the File menu, click Open.
3. Browse and select the jesd204b_ed_qsys.qsys file located in the project directory.
4. Click Open to view the Qsys system.

You can access the address mapping of the submodules in the top level Qsys project by clicking on the Address Map tab in the Qsys window.

The Qsys system supports multi-link scenarios (up to 16 links) using the existing address map. To add more links to the system, add more jesd204b_subsystem.qsys modules to the project, connect them to the jesd204b_subsystem Avalon-MM bridge, and adjust the address map accordingly. Bits 16-19 of the nios_subsystem-to-jesd204b_subsystem Avalon-MM bridge are reserved to support multi-links.

The JESD204B subsystem Qsys project, jesd204b_subsystem.qsys, instantiates the following modules:

• JESD204B IP core (altera_jesd204) configured in duplex, non-bonded mode (with TX and RX datapaths)
• Reset sequencer (altera_reset_sequencer)
• Transceiver PHY reset controller (altera_xcvr_reset_control)
• ATX PLL (altera_xcvr_atx_pll_a10)
• Avalon-MM bridge (altera_avalon_mm_bridge)

The grouping of modules into a single Qsys subsystem project facilitates easy implementation of multi-link capabilities. For every link that you implement, a jesd204b_subsystem.qsys project is instantiated in the top level Qsys project and assigned an address as described in the Address Map section of the Qsys System section. Each link can be reset and dynamically reconfigured independently.

The Nios II subsystem Qsys project, nios_subsystem.qsys ¹⁸, instantiates the following peripherals:

• Nios II processor (altera_nios2_gen2)
• On-chip memory (altera_avalon_onchip_memory2)—provides both instruction and data memory space
• Timer (altera_avalon_timer)—provides a general timer function for the software
• JTAG UART (altera_avalon_jtag_uart)—serves as the main communications portal between the user and the Nios II processor via the terminal console in Nios II SBT for Eclipse tool
• Avalon-MM bridges (altera_avalon_mm_bridge)—two Avalon-MM bridge modules; one to interface to the JESD204B subsystem and the other to interface to the Qsys components (core PLL reconfiguration controller and SPI master modules) in the top level Qsys project.
• PIO (altera_avalon_pio)—provides general input/output (I/O) access from the Nios II processor to the HDL components in the FPGA via two sets of 32-bit registers:
  • io_status—status registers input from the HDL components to the Nios II processor
  • io_control—control registers output from the Nios II processor to the HDL components

The tables below describe the signal connectivity for the io_status and io_control registers.

You can access the address map of the submodules in the Nios II subsystem by clicking on the Address Map tab in the Qsys window.

For the frame clock, when F=1 and F=2, the resulting frame clock value can easily exceed the capability of the core PLL to generate and close timing. The top level RTL file (jesd204b_ed.sv) defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly. For this example design, the F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. For example, the actual frame clock for a serial data rate of 6.144 Gbps and F = 1 is:

(6144/(10 × 1)) / F1_FRAMECLK_DIV = 614.4 / 4 = 153.6 MHz

You can use this IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA. The PLL reconfiguration controller connects to the Nios II processor via the Avalon-MM interconnect. The Nios II processor sends dynamic reconfiguration instructions to the controller during a dynamic data rate reconfiguration operation. By default, the software does not contain any dynamic reconfiguration features but you can use the Qsys system to implement such feature in the software.

This module uses the SPI protocol to facilitate the configuration of external converters (for example, ADC, DAC, external clock modules) via a structured register space inside the converter device. The SPI master module is connects to the Nios II processor via the Avalon-MM interconnect. By default, the software does not contain any external converter configuration features but you can use the Qsys system to implement the feature in the software.

For more details on the SPI master module, refer to chapter 5.

The transport layer provides the following services to the application layer (AL) and the DLL:

• The assembler at the TX path:
  • maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
  • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during TX data streaming.
• The deassembler at the RX path:
  • maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon-ST interface).
  • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during RX data streaming.

The transport layer has many customization options and you may modify the transport layer RTL to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the transport layer in the same way. By default, the software does not contain any dynamic reconfiguration features but you can use the Qsys system to implement such feature in the software.

For more details on the implementation of the transport layer in RTL and customization options, refer to chapter 5.

The test pattern generator has many customization options and you can modify the test pattern generator RTL to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. By default, the software does not contain any dynamic reconfiguration features but you can use the Qsys system to implement such feature in the software.

The test pattern checker is implemented in the top level RTL file, not in the Qsys project. The test pattern checker checks one of three patterns; parallel PRBS, alternate checkerboard, or ramp wave from the transport layer during test mode. The test pattern checker has many customization options and you may modify the test pattern checker RTL to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, the test pattern checker shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. By default, the software does not contain any dynamic reconfiguration features but you can use the Qsys system to implement such feature in the software.

The main reference clock for the design data path is the device_clk, which is supplied from an external source. The device_clk is the reference clock for the core PLL and the TX/RX transceiver reference clocks. The core PLL generates the link_clk and frame_clk from the device_clk. The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. The external source supplies a clock called the mgmt_clk to clock the control path of the design (the Nios II subsystem and any modules connected to the Nios II via the Avalon-MM bus interconnect).

The top level HDL file (jesd204b_ed.sv) includes system parameters that define the configuration of the example design as a whole. You can change the values in the HDL file after generation to customize to your desired configuration but the values must fall within the supported value ranges.

The JESD204B serial data, control, and configuration signal pins are assigned to FMC port A connector. To interoperate with your converter device, ensure that the pin assignments for the JESD204B serial data, control, and configuration ports are set correctly according your converter specifications. The global reset pin (global_rst_n) connects to the user PB0 push-button on the board. The control plane clock (mgmt_clk) is sourced from the on-board Si570 programmable oscillator. The Si570 clock output routes through a Si53301 clock buffer that allows you to select between the Si570 clock output and SMA input. Follow the instructions in the Programming the Device section to set the board settings correctly.

The example design is configured in internal serial loopback mode. Therefore, the JESD204B data path reference clock (device_clk) is sourced from an on-board clock source, the Si5338 programmable oscillator. In general, when interoperating with an external converter, the device_clk is sourced from the converter through the FMC connector. If this suits your configuration, modify the device_clk pin assignments accordingly to assign the pin to the FMC connector.

The software control flow allows you to perform the following tasks:

• System reset – ability to reset individual modules (core PLL, transceiver PHY, JESD204B base Avalon-MM interface, link clock domain, and frame clock domain) independently or in sequence.
• Initial and dynamic, real-time configuration of external converter devices via SPI interface.
• Dynamic reconfiguration of key modules in the design example subsystem (for example, JESD204B IP core base layer, transceiver PHY, core PLL).
• Error handling via interrupt service routines (ISR).
• Status register readback.
• Dynamic switchi