The 10/100/1000 Gbps Ethernet MAC only variation can serve as a bridge between your application and standard fast or gigabit Ethernet PHY devices.

The FPGA application implements the Ethernet MAC, the 1000BASE-X PCS, and an internal system using Ethernet connectivity. This internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an optical module is provided through an external SFP optical module. Certified 1.25 GBaud optical SFP transceivers are Finisar 1000BASE-SX FTLF8519P2BNL, Finisar 1000BASE-LX FTRJ-1319-3, and Avago Technologies AFBR-5710Z.

A 10/100/1000 Mbps Ethernet MAC and an internal system are implemented in the FPGA. The internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an Ethernet link is provided through a combined MII to an external PHY module. Certified 1.25 GBaud copper SFP transceivers are Finisar FCMJ-8521-3, Methode DM7041, and Avago Technologies ABCU-5700RZ.

For more information on how to install and use Intel FPGA IPs, refer to the Introduction to Intel FPGA IP Cores.

This walkthrough explains how to create a Triple-Speed Ethernet Intel^® FPGA IP design using Platform Designer in the Intel^® Quartus^® Prime software. After you generate a custom variation of the Triple-Speed Ethernet Intel^® FPGA IP, you can incorporate it into your overall project.

This walkthrough includes the following steps:

1. Creating a New Intel Quartus Prime Project
2. Generating a Design Example or Simulation Model
3. Simulating the System
4. Compiling the Triple-Speed Ethernet Intel FPGA IP Design
5. Programming an FPGA Device

You can now integrate your custom IP instance in your design, simulate, and compile. While integrating your IP instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

After successfully compiling your design, program the targeted Intel FPGA device with the Intel^® Quartus^® Prime Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer to the Device Programming section in volume 3 of the Intel^® Quartus^® Prime Handbook.

This chapter describes the parameters and how they affect the behavior of the IP. Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface.

The Triple-Speed Ethernet Intel^® FPGA IP includes the following functions:

• 10/100/1000 Ethernet MAC
• 1000BASE-X/SGMII PCS With Optional Embedded PMA
• Intel FPGA IEEE 1588v2

• Variations with internal FIFO buffers—supports only single port.
• Variations without internal FIFO buffers—supports up to 24 ports (except for Intel^® Arria^® 10, Intel^® Cyclone^® 10 GX, and Intel^® Stratix^® 10 devices) and the ports can operate at different speeds.
• Small MAC—provides basic functionalities of a MAC function using minimal resources.

  Refer to 10/100/1000 Ethernet MAC Versus Small MAC for a feature comparison between the 10/100/1000 Ethernet MAC and small MAC.

The MAC function supports the following Ethernet frames: basic, VLAN and stacked VLAN, jumbo, and control frames.

• Avalon^® streaming interface on the system side.
  • Avalon^® streaming sink port on transmit with the following properties:
    • Fixed data width, 8 bits, in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
    • Packet support using start-of-packet (SOP) and end-of-packet (EOP) signals, and partial final packet signals.
    • Error reporting.
    • Variable-length ready latency specified by the tx_almost_full register.
  • Avalon^® streaming source port on receive with the following properties:
    • Fixed data width of 8 bits in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
    • Backpressure is supported only in MAC variations with internal FIFO buffers. Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds.
    • Packet support using SOP and EOP signals, and partial final packet signals.
    • Error reporting.
    • Ready latency is zero in MAC variations without internal FIFO buffers. In MAC variations with internal FIFO buffers, the ready latency is two.
• Media independent interfaces on the network side—select MII, GMII, or RGMII by setting the Interface option on the Core Configuration page or the ETH_SPEED bit in the command_config register.
• Control interface—an Avalon^® memory-mapped slave port that provides access to 256 32-bit configuration and status registers, and statistics counters. This interface supports the use of waitrequest to stall the interconnect fabric for as many cycles as required.
• PHY management interface—implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers. This interface supports up to 32 PHY devices.

MAC variations without internal FIFO buffers implement the following additional interfaces:

• FIFO status interface—an Avalon^® streaming sink port that streams in the fill level of an external FIFO buffer. Only MAC variations without internal buffers implement this interface.
• Packet classification interface—an Avalon^® streaming source port that streams out receive packet classification information. Only MAC variations without internal buffers implement this interface.

• In MAC variations with internal FIFO buffers:
  • Cut-through mode—transmission starts when the level of the FIFO level hits the transmit section-full threshold.
  • Store and forward mode—transmission starts when a full packet is received.
    Note: To use the internal FIFO buffer in the store and forward mode, ensure that the internal FIFO buffer size is larger than the transmitted packet size. If the transmitted packet size is larger than the internal FIFO buffer size, the Triple-Speed Ethernet Intel^® FPGA IP locks up with no packet transmission. The lock-up of the IP can only be cleared through a hard reset to the IP.
• In MAC variations without internal FIFO buffers, transmission starts as soon as data is available on the Avalon^® streaming transmit interface.

• 46 bytes for basic frames
• 42 bytes for VLAN tagged frames
• 38 bytes for stacked VLAN tagged frames

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X ³² +X ²⁶ +X ²³ +X ²² +X ¹⁶ +X ¹² +X ¹¹ +X ¹⁰ +X ⁸ +X ⁷ +X ⁵ +X ⁴ +X ² +X ¹ +1

The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus transmitted in the following order: X31, X30, ..., X1, X0.

In half-duplex mode, the MAC function constantly monitors the line. Transmission starts only when the line has been idle for a period of 96 bit times and any backoff time requirements have been satisfied. In accordance with the standard, the MAC function begins to measure the IPG when the m_rx_crs signal is deasserted.

When the MAC function detects collision during transmission, it stops the transmission and sends a 32-bit jam pattern instead. A jam pattern is a fixed pattern, 0x648532A6, and is not compared to the CRC of the frame. The probability of a jam pattern being identical to the CRC is very low, 0.532%.

If the MAC function detects a collision while transmitting the preamble or start frame delimiter (SFD) field, it sends the jam pattern only after transmitting the SFD field, which subsequently results in a minimum of a 96-bit fragment.

If the MAC function detects a collision while transmitting the first 64 bytes, including the preamble and SFD fields, the MAC function waits for an interval equal to the backoff period and then retransmits the frame. The frame is stored in a 64-byte retransmit buffer. The backoff period is generated from a pseudo-random process, truncated binary exponential backoff.

The IEEE standard specifies that frames must be separated by an interpacket gap (IPG) of at least 96 bit times. The MAC function, however, can accept frames with an IPG of less than 96 bit times; at least 8-bytes and 6-bytes in RGMII/GMII (1000 Mbps operation) and RGMII/MII (10/100 Mbps operation) respectively.

The MAC function removes the preamble and SFD fields from valid frames.

• Unicast address—bit 0 of the destination address is 0.
• Multicast address—bit 0 of the destination address is 1.
• Broadcast address—all 48 bits of the destination address are 1.

  The MAC function always accepts broadcast frames. If promiscuous mode is enabled (PROMIS_EN bit in the command_config register = 1), the MAC function omits address filtering and accepts all frames.

• The primary address, configured in the registers mac_0 and mac_1
• The supplementary addresses, configured in the following registers: smac_0_0/smac_0_1, smac_1_0/smac_1_1, smac_2_0/smac_2_1 and smac_3_0/smac_3_1

  Otherwise, the MAC function discards the frame.

• 46 bytes for basic MAC frames
• 42 bytes for VLAN tagged frames
• 38 bytes for stacked VLAN tagged frames

When padding removal is turned off, complete frames including the padding are forwarded to the Avalon^® streaming receive interface.

FCS(X) = X ³² +X ²⁶ +X ²³ +X ²² +X ¹⁶ +X ¹² +X ¹¹ +X ¹⁰ +X ⁸ +X ⁷ +X ⁵ +X ⁴ +X ² +X ¹ +1

The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus received in the following order: X31, X30,..., X1, X0.

If the MAC function detects CRC-32 error, it marks the frame invalid by asserting the following signals:

• rx_err[2] in MAC variations with internal FIFO buffers.
• data_rx_error[1] in MAC variations without internal FIFO buffers.

The MAC function discards frames with CRC-32 error if the RX_ERR_DISC bit in the command_config register is set to 1.

For frames less than the required minimum length, the MAC function forwards the CRC-32 field to the user application if the CRC_FWD and PAD_EN bits in the command_config register are 1 and 0 respectively. Otherwise, the CRC-32 field is removed from the frame.

The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the different frame types:

• Basic frames—the value specified in the frm_length register
• VLAN tagged frames—the value specified in the frm_length register plus four
• Stacked VLAN tagged frames—the value specified in the frm_length register plus eight

To prevent FIFO buffer overflow, the MAC function truncates the frame if it is more than 11 bytes longer than the allowed maximum length.

For frames of a valid length, the MAC function continues to check the payload length if the NO_LGTH_CHECK bit in the command_config register is set to 0. The MAC function keeps track of the payload length as it receives a frame, and checks the length against the length/type field in basic MAC frames or the client length/type field in VLAN tagged frames. The payload length is valid if it satisfies the following conditions:

• The actual payload length matches the value in the length/type or client length/type field.
• Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.
• VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.
• Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding 1536.

If the frame or payload length is not valid, the MAC function asserts one of the following signals to indicate length error:

• rx_err[1] in MACs with internal FIFO buffers.
• data_rx_error[0] in MACs without internal FIFO buffers.

For MAC variations with internal FIFO buffers, the MAC function writes the frame to the internal receive FIFO buffers. For MAC variations without internal FIFO buffers, it forwards the frame to the Avalon^® streaming receive interface.

MAC variations without internal FIFO buffers do not support backpressure on the Avalon^® streaming receive interface. In this variation, if the receiving component is not ready to receive data from the MAC function, the frame gets truncated with error and subsequent frames are also dropped with error.

• Almost empty
• Almost full
• Section empty
• Section full

These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers. The FIFO buffer thresholds are configured via the registers.

• Remote device congestion—the receiving device experiences congestion and requests the MAC function to stop sending data.
• Receive FIFO buffer congestion—when the receive FIFO buffer is almost full, the MAC function sends a pause frame to the remote device requesting the remote device to stop sending data.
• Local device congestion—any device connected to the MAC function, such as a processor, can request the remote device to stop data transmission.

You can configure the MAC function to ignore pause frames by setting the PAUSE_IGNORE bit in the command_config register is set to 1.

For MAC variations with internal FIFO buffers, the MAC function generates an XOFF pause frame when the level of the FIFO buffer reaches the section-empty threshold (rx_section_empty). If transmission is in progress, the MAC function waits for the transmission to complete before generating the pause frame. The fill level of an external FIFO buffer is obtained via the Avalon^® streaming receive FIFO status interface.

When generating a pause frame, the MAC function fills the pause quanta bytes P1 and P2 with the value configured in the pause_quant register. The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers, and the destination address is set to a fixed multicast address, 01-80-C2-00-00-01 (0x010000c28001).

The MAC function automatically generates an XON pause frame when the FIFO buffer section-empty flag is deasserted and the current frame transmission is completed. The user application can trigger the generation of an XON pause frame by clearing the XOFF_GEN bit and signal, and subsequently setting the XON_GEN bit to 1 or asserting the xon_gen signal.

When generating an XON pause frame, the MAC function fills the pause quanta (payload bytes P1 and P2) with 0x0000 (zero quanta). The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers and the destination address is set to a fixed multicast address, 01-80-C2-00-00-01 (0x010000c28001).

In addition to the flow control mechanism, the MAC function prevents an overflow by truncating excess frames. The status bit, rx_err[3], is set to 1 to indicate such errors. The user application should subsequently discard these frames by setting the RX_ERR_DISC bit in the command_config register to 1.

The defined sequence is a stream of six consecutive 0xFF bytes followed by a sequence of 16 consecutive unicast MAC addresses. The unicast address is the address of the node to be awakened.

The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header, optional padding and CRC.

Intel recommends that you do not put a node to sleep if you disable magic packet detection.

Network transmission is disabled when a node is put to sleep. The receiver remains enabled, but it ignores all traffic from the line except magic packets to allow a remote agent to wake up the node. In the sleep mode, only etherStatsPkts and etherStatsOctets count the traffic statistics.

• Any multicast address
• A broadcast address
• The primary MAC address configured in the mac_0 and mac_1 registers
• Any of the supplementary MAC addresses configured in the following registers if they are enabled: smac_0_0, smac_0_1, smac_1_0, smac_1_1, smac_2_0, smac_2_1, smac_3_0 and smac_3_1

When the MAC function detects a magic packet, the WAKEUP bit in the command_config register is set to 1, and the etherStatsPkts and etherStatsOctets statistics registers are incremented.

Magic packet detection is disabled when the SLEEP bit in the command_config register is set to 0. Setting the SLEEP bit to 0 also resets the WAKEUP bit to 0 and resumes the transmit and receive operations.

When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and 1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the IP.

• Single channel core configuration—eccstatus[1:0] output ports.
• Multi-channel core configuration—eccstatus_<n>[1:0] output ports, where eccstatus_0[1:0] is for channel 0, eccstatus_1[1:0] for channel 1, and so on.

When you trigger a software reset, the MAC function sets the TX_ENA and RX_ENA bits in the command_config register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only disabled when the current frame transmission and reception complete.

• To trigger a hardware reset, assert the reset signal.
• To trigger a software reset, set the SW_RESET bit in the command_config register to 1. The SW_RESET bit is cleared automatically when the software reset ends.

Intel recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating speed or mode without changing other configurations, preserve the command_config register before performing the software reset and restore the register after the changing the MAC operating speed or mode.

To access each PHY device, write the PHY address to the MDIO register (mdio_addr0/1) followed by the transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the MDIO registers via the Avalon^® memory-mapped interface.

For more information about the registers of a PHY device, refer to the specification provided with the device.

For more information about the MDIO registers, refer to the MAC Configuration Register Space section.

• Gigabit Ethernet operation
• Programmable 10/100 Ethernet operation
• Programmable 10/100/1000 Ethernet operation

A technology specific clock driver is required to generate a clock centered with the GMII or RGMII data from the MAC. The clock driver can be a PLL, a delay line or a DDR flip-flop.

On the receive path, connect the clock provided by the PHY device (2.5 MHz, 25 MHz or 125 MHz) to the MAC clock, rx_clk. The PHY interface is connected to both the MII (active PHY signals) and GMII of the MAC function.

On the transmit path, standard programmable PHY devices operating in 10/100 mode generate a 2.5 MHz (10 Mbps) or a 25 MHz (100 Mbps) clock. In gigabit mode, the PHY device expects a 125-MHz clock from the MAC function. Because the MAC function does not generate a clock output, an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices. In 10/100 mode, the clock generated by the MAC to the PHY can be tri-stated.

During transmission, the MAC control signal eth_mode selects either MII or GMII. The MAC function asserts the eth_mode signal when the MAC function operates in gigabit mode, which subsequently drives the MAC GMII to the PHY interface. The eth_mode signal is deasserted when the MAC function operates in 10/100 mode. In this mode, the MAC MII is driven to the PHY interface.

The Intel FPGA 1000BASE-X/SGMII PCS function implements the functionality specified by IEEE 802.3 Clause 36. It does not support carrier extension, frame bursting, and low power idle features. The PCS function is accessible via MII (SGMII) or GMII (1000BASE-X/SGMII). The PCS function interfaces to an on- or off-chip SERDES component via the industry standard ten-bit interface (TBI).

You can configure the PCS function to include an embedded physical medium attachment (PMA) with a a serial transceiver or LVDS I/O and soft CDR. The PMA interoperates with an external physical medium dependent (PMD) device, which drives the external copper or fiber network. The interconnect between Intel FPGA and PMD devices can be TBI or 1.25 Gbps serial.

The PCS function supports the following external PHYs:

• 1000 BASE-X PHYs as is.
• 10BASE-T, 100BASE-T and 1000BASE-T PHYs if the PHYs support SGMII.

If the PCS function receives a frame from the MAC function with an error (gm_tx_err asserted during frame transmission), the PCS function encodes the error by inserting a /V/ character.

The comma detection function restarts the search for a valid comma character if the receive synchronization state machine loses the link synchronization.

A /V/ character is decoded and sent to the MAC function as frame error. The state machine decodes sequences other than /I/ /I/ (Idle) or /I/ /S/ (Start of Frame) as wrong carrier.

During frame reception, the de-encapsulation state machine checks for invalid characters. When the state machine detects invalid characters, it indicates an error to the MAC function.

When link synchronization is acquired, the link synchronization state machine counts the number of invalid characters received. The state machine increments an internal error counter for each invalid character received and incorrectly positioned comma character. The internal error counter is decremented when four consecutive valid characters are received. When the counter reaches 4, the link synchronization is lost.

The PCS function drives the led_link signal to 1 when link synchronization is acquired. This signal can be used as a common visual activity check using a board LED.

The PCS function drives the led_panel_link signal to 1 when link synchronization is acquired for the PCS operating in 1000 Base-X without auto negotiation and SGMII mode without auto negotiation.

The carrier sense state machine drives the mii_rx_crs and led_crs signals to 1 when it detects an activity. The led_crs signal can be used as a common visual activity check using a board LED.

When a collision happens, the collision detection state machine drives the mii_rx_col and led_col signals to 1. You can use the led_col signal as a visual check using a board LED.

In 1000BASE-X mode, the PCS function always operates in gigabit mode and data duplication is disabled.

In 100 Mbps mode, the transmit converter replicates each byte received by the PCS function 10 times. In 10 Mbps mode, the transmit converter replicates each byte transmitted from the MAC function to the PCS function 100 times.

In 100 Mbps mode, the receive converter transmits one byte out of 10 bytes received from the PCS function to the MAC function. In 10 Mbps mode, the receive converter transmits one byte out of 100 bytes received from the PCS function to the MAC function.

If the SGMII_ENA bit in the if_mode register is set to 0, the PCS function operates in 1000BASE-X. Otherwise, the operating mode is SGMII. The following sections describe the auto-negotiation process for each operating mode.

When simulating your design, you can disable auto-negotiation to reduce the simulation time. If you enable auto-negotiation in your design, set the link_timer time to a smaller value to reduce the auto-negotiation link timer in the simulation.

When the link_timer time expires, the PCS dev_ability register is advertised, with the ACK bit set to 0 for the link partner. The auto-negotiation state machine checks for three consecutive /C/ sequences received from the link partner.

The auto-negotiation state machine then sets the ACK bit to 1 in the advertised dev_ability register and checks if three consecutive /C/ sequences are received from the link partner with the ACK bit set to 1.

Auto-negotiation waits for the value configured in the link_timer register to ensure no more consecutive /C/sequences are received from the link partner. The auto-negotiation is successfully completed when three consecutive idle sequences are received after the link timer expires.

After auto-negotiation completes successfully, the user software reads both the dev_ability and partner_ability register and proceed to resolve priority for duplex mode and pause mode. If the design contains a MAC and PCS, the user software configures the MAC with a proper resolved pause mode by setting the PAUSE_IGNORE bit in command_config register. To disable pause frame generation based on the receive FIFO buffer level, you should set the rx_section_empty register accordingly.

Once auto-negotiation completes successfully, the ability advertised by the link partner device is available in the partner_ability register and the AUTO_NEGOTIATION_COMPLETE bit in the status register is set to 1.

The PCS function restarts auto-negotiation when link synchronization is lost and reacquired, or when you set the RESTART_AUTO_NEGOTIATION bit in the PCS control register to 1.

Possible application of SGMII auto-negotiation in MAC mode and PHY mode.

If the SGMII_ENA and USE_SGMII_AN bits in the if_mode register are 1, the PCS function is automatically configured with the capabilities advertised by the PHY device once the auto-negotiation completes.

If the SGMII_ENA bit is 1 and the USE_SGMII_AN bit is 0, the PCS function can be configured with the SGMII_SPEED and SGMII_DUPLEX bits in the if_mode register.

If the SGMII_ENA bit is 1 and the SGMII_AN_MODE bit is 1 (SGMII PHY Mode auto-negotiation is enabled) the speed and duplex mode resolution will be resolved based on the value that you set in the dev_ability register once auto negotiation is done. You should use set to the PHY mode if you want to advertise the link speed and duplex mode to the link partner.

On transmit, the SERDES must serialize tbi_tx_d[0], the least significant bit of the TBI output bus first and tbi_tx_d[9], the most significant bit of the TBI output bus last to ensure the remote node receives the data correctly, as illustrated in the following figure.

On receive, the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last, as illustrated in the following figure.

The serial loopback option is not supported in Cyclone^® IV devices with GX transceiver.

When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmit and the TBI receive interfaces are ignored. The management interface remains active and responds to management transactions from the MAC layer device.

For designs targeting devices other than Stratix V, you can export the power-down signals to implement your own power-down logic to efficiently use the transceivers within a particular transceiver quad. Turn on the Export transceiver powerdown signal parameter to export the signals.

In PCS variations with embedded PMA, assert the respective reset signals or the power-down signal to trigger a hardware reset. You must assert the reset signal subsequent to asserting the reset_rx_clk, reset_tx_clk, or gxb_pwrdn_in signal. The reset sequence is also initiated when the active-low rx_freqlocked signal goes low.

For more information about the rx_freqlocked signal and transceiver reset, refer to the transceiver handbook of the respective device family.

Assert the reset or gxb_pwrdn_in signals to perform a hardware reset on MAC with PCS and embedded PMA variation.

The Intel FPGA IEEE 1588v2 provides a timestamp for receiving and transmitting frames in the Triple-Speed Ethernet Intel^® FPGA IP designs. This feature consists of Precision Time Protocol (PTP). PTP is a layer-3 protocol that accurately synchronizes all real time-of-day clocks in a network to a master clock.

• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded serial PMA without FIFO buffer in full-duplex mode
• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded LVDS I/O without FIFO buffer in full-duplex mode
• 10/100/1000-Mbps MAC without FIFO buffer in full-duplex mode
• 10/100/1000-Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS without FIFO buffer in full-duplex mode

• Supports 4 types of PTP clock on the transmit datapath:
  • Master and slave ordinary clock
  • Master and slave boundary clock
  • End-to-end (E2E) transparent clock
  • Peer-to-peer (P2P) transparent clock
• Supports PTP message types:
  • PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
  • PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce, Management, and Signaling.
• Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath.
  • 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message or updates the correction field with residence time.
  • 2-step clock synchronization—The MAC function provides accurate timestamp and the related fingerprint for all PTP message.
• Supports the following PHY operating speed accuracy:
  • random error:
    • 10Mbps—NA
    • 100Mbps—timestamp accuracy of ± 5 ns
    • 1000Mbps—timestamp accuracy of ± 2 ns
  • static error—timestamp accuracy of ± 3 ns
• Supports IEEE 802.3, UDP/IPv4, and UDP/IPv6 transfer protocols for the PTP frames.
• Supports untagged, VLAN tagged, Stacked VLAN Tagged PTP frames, and any number of MPLS labels.
• Supports configurable register for timestamp correction on both transmit and receive datapaths.
• Supports Time-of-Day (ToD) clock that provides a stream of 64-bit and 96-bit timestamps.

• IEEE 802.3
• UDP/IPv4
• UDP/IPv6

The deterministic latency measurement methodology is introduced for Intel^® Stratix^® 10 E-tile devices. It is based on the concept of measuring the time when a given word is at the interface to the PMA and when that same word is at the FPGA core. The difference in time between these two events, when added to the PMA propagation delay, determines the total latency between the FPGA core and the serial pins. Such a calculation intrinsically includes all delays due to intermediate logic, FIFOs, and all other effects.

Even though this measurement is applicable for E-tile devices, Triple-Speed Ethernet only supports this feature for the 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2xTBI PCS and without internal FIFO enabled IP variant using Intel^® Stratix^® 10 E-tile devices, running at 1G speed. You must turn on Enable timestamping and Enable deterministic latency for E-tile device options to enable the DL feature.

• MII/GMII
• RGMII
• 10-bit Interface
• SGMII
• 1000BASE-X
• Management Data Input/Output (MDIO) for external PHY register configuration

When using the Triple-Speed Ethernet Intel^® FPGA IP with an external interface, you must understand the requirements and initialize the registers.

Register initialization mainly performed in the following configurations:

• External PHY Initialization using MDIO (Optional)
• PCS Configuration Register Initialization
• MAC Configuration Register Initialization

This section discusses the register initialization for the following examples of the Ethernet system using different MAC interfaces with recommended initialization sequences:

• Triple-Speed Ethernet System with MII/GMII or RGMII
• Triple-Speed Ethernet System with SGMII
• Triple-Speed Ethernet System with 1000BASE-X Interface

• 10/100/1000 Ethernet MAC Signals
• 10/100/1000 Multiport Ethernet MAC Signals
• 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
• 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals
• 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
• 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
• 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
• 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
• 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
• 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
• 1000BASE-X/SGMII PCS Signals
• 1000BASE-X/SGMII 2XTBI PCS Signals
• 1000BASE-X/SGMII PCS and PMA Signals