Intel FPGA SDK for OpenCL: Intel Arria 10 SoC Development Kit Reference Platform Porting Guide
Version Information
Updated for: |
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Intel® Quartus® Prime Design Suite 19.1 |
1. Intel FPGA SDK for OpenCL Intel Arria 10 SoC Development Kit Reference Platform Porting Guide
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of the Khronos Group™.
The Intel® FPGA SDK for OpenCL™ is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
1.1. Intel Arria 10 SoC Development Kit Reference Platform: Prerequisites
Prerequisites for the a10soc Reference Platform:
- An Intel Arria 10 SoC-based accelerator
card with working memory interfaces
Test these interfaces together in the same design using the same version of the Intel® Quartus® Prime Pro Edition software that you will use to develop your Custom Platform.
- Intel® Quartus® Prime Pro Edition software Version 19.3
- Designing with Logic Lock Plus regions
- Intel® SoC Embedded Design Suite Version 19.3
General knowledge prerequisites:
- FPGA architecture, including clocking, global routing, and I/Os
- High-speed design
- Timing analysis
- Platform Designer design, and Avalon® and AXI interfaces
- Tcl scripting
- Hard processor systems (HPS)
- DDR4 external memory
- Embedded Linux development
This document also assumes that you are familiar with the following Intel® FPGA SDK for OpenCL™ -specific tools and documentation:
- Custom Platform Toolkit and the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide
- Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
- Intel® FPGA SDK for OpenCL™ Cyclone V SoC Development Kit Reference Platform Porting Guide
1.2. Features of the Intel Arria 10 SoC Development Kit Reference Platform
The Intel® Arria® 10 SoC Development Kit Reference Platform targets a subset of the hardware features available in the Intel® Arria® 10 SoC Development Kit.

Features of the a10soc Reference Platform:
- OpenCL Host
The a10soc Reference Platform uses the Intel® SoC HPS as the host that connects to the FPGA fabric via HPS-to-FPGA (H2F) and FPGA-to-HPS (F2H) bridges.
- OpenCL Global Memory
The hardware provides two 1-gigabyte (GB) DDR4 SDRAM daughtercards that are mounted on the HiLo connectors (HPS Memory and FPGA Memory in Figure 1).
- FPGA Programming via Partial Reconfiguration (PR) over HPS lightweight bridge (Lw-bridge)
- Guaranteed Timing
The a10soc Reference Platform relies on the Intel® Quartus® Prime Pro Edition compiler to provide guaranteed timing closure. The timing-clean a10soc Reference Platform is preserved in the form of a precompiled post-fit netlist (that is, the base.qdb Intel® Quartus® Prime Partition Database File that is part of the base.qar Intel® Quartus® Prime Archive File). The Intel® FPGA SDK for OpenCL™ Offline Compiler imports this preserved post-fit netlist into each OpenCL kernel compilation.

1.3. Intel Arria 10 SoC Development Kit Reference Platform Board Variants
- a10soc—targets the Intel Arria 10 SoC Development Kit with one DDR4 memory. The DDR4 memory is shared between the HPS host and the FPGA.
- a10soc_2ddr—targets the Intel Arria 10 SoC Development Kit with two DDR4 memories. One DDR4 memory is an added FPGA memory, and the other DDR4 memory is shared between the HPS host and the FPGA.
To compile your OpenCL kernel for a specific board variant, include the -board=<board_name> option in your aoc command.
For example: aoc -board=a10soc_2ddr myKernel.cl
1.4. Contents of the Intel Arria 10 SoC Development Kit Reference Platform
File or Directory | Description |
---|---|
board_env.xml | An XML file that describes the Reference Platform to the Intel® FPGA SDK for OpenCL™ . |
hardware | Contains the
Intel®
Quartus® Prime project
templates for the two board variants. Each a10soc Reference Platform
board variant implements the entire OpenCL hardware system on a
given Intel Arria
10 SoC Development Kit. See Table 2 for a list of files in this directory. |
arm32 | Directory that contains the following:
|
File | Description |
---|---|
acl_kernel_interface_soc_pr.qsys | Platform Designer system that implements interface to kernel system in board system. |
base.qsf |
Intel®
Quartus® Prime Settings File for the
base project revision. To compile to base revision, add the -bsp-flow=base argument to aoc command (for example, aoc -bsp-flow=base myKernel.cl). Use this revision when porting the a10soc Reference Platform to your own Custom Platform. The Intel® Quartus® Prime Pro Edition software compiles this base project revision from source code. |
base.qar |
Intel®
Quartus® Prime
Archive File containing base.qdb, pr_base.id, and base.sdc. This file is generated by the scripts/post_flow_pr.tcl file during
base revision compile, and is used during import revision compilation.
|
board.qsys | Platform Designer system that implements the board interfaces (that is, the static region) of the OpenCL hardware system. |
board_spec.xml | XML file that provides the definition of the board hardware interfaces to the SDK. |
DMA_system.qsys | Platform Designer system that implements DMA between HPS memory and FPGA memory in the a10soc_2ddr board variant |
dual_port_splitter.qsys | Platform Designer system that splits requests on single slave to two channels. Used for utilizing two FPGA2SDRAM ports on HPS. |
flat.qsf |
Intel® Quartus® Prime Settings File for the flat project revision. This file includes all the common settings, such as pin location assignments, that are used in the other revisions of the project (that is, base and top). The base.qsf and top.qsf files include, by reference, all the settings in the flat.qsf file. The Intel® Quartus® Prime software compiles the flat revision with minimal location constraints. The flat revision compilation does not generate a base.qar file that you can use for future import compilations and does not implement the guaranteed timing flow. |
import_compile.tcl | Tcl script for the SDK-user compilation flow (that is, import revision compilation). |
opencl_bsp_ip.qsf |
Intel® Quartus® Prime Settings File that collects all the required .ip files in a unique location. During flat and base revision compilations, the board.qsys Platform Designer file is added to the opencl_bsp_ip.qsf file. |
quartus.ini | Contains any special Intel® Quartus® Prime software options that you need when compiling OpenCL kernels for the a10soc Reference Platform. |
top.qpf | Intel® Quartus® Prime Project File for the OpenCL hardware system. |
top.qsf | Intel® Quartus® Prime Settings File for the SDK-user compilation flow. |
top.sdc | Synopsys® Design Constraints File that contains board-specific timing constraints. |
top.v | Top-level Verilog Design File for the OpenCL hardware system. |
ip/freeze_wrapper.v | Verilog Design File that implements the freeze logic placed at outputs of the PR region. |
ip/acl_kernel_interface_soc_pr/<file_name> |
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the acl_kernel_interface_soc_pr component. You must provide both the acl_kernel_interface_soc_pr.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software. |
ip/board/<file_name> |
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the board system. You must provide both the board.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software. |
ip/DMA_system/<file_name> |
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the DMA_system component in a10soc_2ddr board variant. You must provide both the DMA_system.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software. |
ip/dual_port_splitter/<file_name> |
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the dual_port_splitter component. You must provide both the dual_port_splitter.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software. |
ip/irq_controller/<file_name> | IP that receives interrupts from the OpenCL kernel system and DMA_system, and sends single IRQ to the host. |
ip/mem_splitter_port/<file_name> | IP that splits requests across multiple channels on burst word boundary. |
scripts/base_write_sdc.tcl | Tcl script that the base revision compilation uses to generate the base.sdc file that contains all the constraints collected in the base revision compilation. The Intel® Quartus® Prime Pro Edition software uses the base.sdc file when compiling the import (top) revision. |
scripts/create_fpga_bin_pr.tcl | Tcl script that generates the fpga.bin file. The fpga.bin file contains all the necessary files for configuring the FPGA. |
scripts/post_flow_pr.tcl | Tcl script that implements the guaranteed timing closure flow. |
scripts/pre_flow_pr.tcl | Tcl script that executes before the invocation of the Intel® Quartus® Prime software compilation. Running the script generates the Platform Designer HDL for board.qsys and kernel_mem.qsys. It also creates a unique ID for the PR base revision (that is, static region). This unique ID is stored in the pr_base.id file. |
scripts/qar_ip_files.tcl | Tcl script that packages up base.qdb, pr_base.id and base.sdc during base revision compile. |
scripts/regenerate_cache.tcl | Tcl script that regenerates the BAK cache file in your temporary directory. |
1.5. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.0 to 17.1
File | Change |
---|---|
import_compiles.tcl | Updated the file for incremental and fast compile features. |
board_spec.xml | Updated the version from 17.0 to 17.1. |
quartus.ini | Added qhd_skip_pr_revision_type_check=on INI to the file. |
scripts/post_flow_pr.tcl | Updated the file to:
|
scripts/create_fpga_bin_pr.tcl | Added the Quartus version as part of fpga.bin. |
scripts/qar_ip_files.tcl | Updated the file to include:
|
scripts/regenerate_cache.tcl | Updated the file to include changes required to move bak_flow.tcl into Intel® FPGA SDK for OpenCL™ . |
scripts/bak_flow.tcl | Moved the file into Intel® FPGA SDK for OpenCL™ . |
scripts/helpers.tcl | Moved the file into Intel® FPGA SDK for OpenCL™ . |
board.qsys |
|
hw_mmd_constants.h | Increased the ACL_VERSIONID to 0xA0C7C1E2 due to the PR IP address change. |
base.qar | Updated the file with ACDS 17.1 static region. |
1.6. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.1.2 to 18.0
- Various clean up of import_compile.tcl, pre_flow_pr, post_flow_pr
- Clean up of old top_synth revision (migrated to new simplified PR flow)
- Fix for write .sdc, in base_write_sdc.tcl
- AOC no longer emits .qsys files, it emits just Verilog HDL
(kernel_system.v) and injects a .qip file into
project. Changes needed:
- Instantiate module kernel_system from kernel_system.v (in pr_region.v now)
- If you use add_pipe in board_spec.xml, instantiate pipeline registers in the BSP but within the PR region (see ip/kernel_mem and pr_region.v)
File | Change |
---|---|
base.qar | Updated with 18.0 static region. |
board_spec.xml | Updated version, static region used resources, removed addpipe parameter, which is no longer needed. |
top.qpf | Removed top_synth revision. |
flat.qsf | Removal of obsolete assignments. |
base.qsf | Removed Platform Designer flow. |
kernel_system_inst | pr_region_inst |
top.qsf | Simplified PR flow. |
opencl_bsp_ip.qsf | Removed Platform Designer flow. |
top.sdc | Removed Platform Designer flow. |
import_compile.tcl | Removed Platform Designer flow, simplified PR flow. |
ip/freeze_wrapper.v | Removed Platform Designer flow. |
scripts/base_write_sdc.tcl | Updated to correct base.sdc ordering. |
scripts/post_flow_pr.tcl | Updated for fast-compilation |
scripts/pre_flow_pr.tcl | Updated for fast-compile, removed Platform Designer flow, and cleaned up (moved some functions into OpenCL SDK). |
scripts/qar_ip_files.tcl | Do not package up opencl_bsp_ip.qsf. |
base.qar | Updated with 18.0 static region. |
Files added:
- kernel_mem.qsys
- ip/pr_region.v
- ip/kernel_mem/kernel_mem_mm_bridge_0.ip
- top_synth.qsf, which is obsolete because of simplified PR flow.
2. Developing an Intel Arria 10 SoC Custom Platform
Developing your Custom Platform requires in-depth knowledge of the contents in the following documents and tools:
- Intel® FPGA SDK for OpenCL™ Custom Platform User Guide
- Intel® FPGA SDK for OpenCL™ Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
- Contents of the SDK Custom Platform Toolkit
- Cyclone V SoC Development Kit Reference Platform Porting Guide
- Documentation for all the Intel® IP in your Custom Platform
- Intel® FPGA SDK for OpenCL™ Getting Started Guide
- Intel® FPGA SDK for OpenCL™ Programming Guide
In addition, you must independently verify all IP on your computing card (for example, DDR4 external memory).
2.1. Initializing an Intel Arria 10 SoC Custom Platform
- Copy the contents of the INTELFPGAOCLSDKROOT/board/a10soc directory (where INTELFPGAOCLSDKROOT points to the location of your Intel® FPGA SDK for OpenCL™ installation) to a directory that you own and rename the directory ( <your_custom_platform> ).
-
Choose one of the board variants in the
<your_custom_platform>/hardware
directory as the basis of your design.
The INTELFPGAOCLSDKROOT/board/a10soc directory includes the following board variants:
- a10soc—includes one DDR4 shared memory between the HPS host and the FPGA
- a10soc_2ddr—includes one DDR4 shared memory and one DDR4 memory for the FPGA
- Rename the directory of the chosen board variant to match the name of your FPGA board ( <your_custom_platform>/hardware/<board_name> ). Delete the other a10socdk board variant that you do not need.
- Modify the <your_custom_platform>/board_env.xml file so that the name and default fields match the changes you made in 1 and 3, respectively.
- Set the environment variable AOCL_BOARD_PACKAGE_ROOT variable to point to the location of your Custom Platform.
-
Invoke the command
aoc
-list-boards
to confirm that
the
Intel® FPGA SDK for OpenCL™ Offline Compiler displays the board
name in your Custom Platform.
> aoc -list-boards Board list: my_board
2.2. Modifying Your Intel Arria 10 SoC Custom Platform
- Instantiate or edit the HPS IP parameters.
-
Instantiate any controllers required (for example, memory
controllers, PR controllers and so on) and I/O channels, if required. You can
add the board interface hardware either as Platform Designer components in the board.qsys
Platform Designer system or as HDL in the top.v file.
The board.qsys file and the top.v file are in the <your_custom_platform>/hardware/<board_name> directory.
- Modify the <your_custom_platform>/hardware/<board_name>/flat.qsf file to use only the pin-outs and settings for your system.
- Update the offset addresses of controllers in the respective header files in <your_custom_platform>/arm32/drivers directory, if you modified any controllers in your design.
2.3. Integrating Your Intel Arria 10 SoC Custom Platform with the Intel FPGA SDK for OpenCL
- Update the <your_custom_platform>/hardware/<board_name>/board_spec.xml file. Ensure that there is at least one global memory interface, and all the global memory interfaces correspond to the exported interfaces from the board.qsys Platform Designer System File.
-
Use the -bsp-flow=flat attribute to compile the flat revision
corresponding to
<your_custom_platform>/hardware/<board_name>/flat.qsf
file without the partitions or Logic Locks.
Tip: Intel recommends to get a timing clean flat revision compiled before proceeding to the base revision compiles.
aoc -bsp-flow=flat boardtest.cl -o=bin/boardtest.aocx
- Use the -bsp-flow=base attribute to compile the base revision corresponding to <your_custom_platform>/hardware/<board_name>/base.qsf file.
-
Perform the steps outlined in the
INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/README.txt
file to compile the
INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl
OpenCL kernel source file.
The environment variable INTELFPGAOCLSDKROOT points to the location of the Intel® FPGA SDK for OpenCL™ installation.
- If compilation fails because of timing failures, fix the errors, or compile INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest.cl with different seeds. To compile the kernel with a different seed, include the -seed=<N> option in the aoc command (for example, aoc -seed=2 boardtest.cl ).
2.4. Changing the Device Part Number
Update the device part number in the following files within the <your_custom_platform>/hardware/<board_name> directory:
-
In the flat.qsf and
opencl_bsp_ip.qsf files:
- Change the device part number in the set global assignment -name DEVICE 10AS066N3F40E2SG QSF assignment.
- Update the necessary pin assignment changes.
- The updated device number will appear in the base.qsf and top.qsf files.
- In the board.qsys file, change all occurrences of 10AS066N3F40E2SG.
2.5. Modifying the Kernel PLL Reference Clock
- In the <your_custom_platform>/hardware/<board_name>/board.qsys file, update the REF_CLK_RATE parameter value on the kernel_clk_gen IP module.
- In the <your_custom_platform>/hardware/<board_name>/top.sdc file, update the create_clock assignment for kernel_pll_refclk.
2.6. Modifying the Hard Processor System
In the reference design, the HPS IP was instantiated with FPGA-to-HPS interface width set to "128-bit AXI", F2SDRAM port configuration set to "Port Configuration 3" and F2SDRAM0 and F2SDRAM2 enabled.
This instantiation was done to maximize kernel to HPS memory bandwidth. A custom IP module was instantiated between kernel memory interface and the two SDRAM ports to split kernel memory access across the ports.
2.7. Guaranteeing Timing Closure in the Intel Arria 10 SoC Custom Platform
-
Establish the floorplan of your design.
Important: Consider all design criteria outlined in the FPGA System Design section of the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.
- Ensure that the AOCL_BOARD_PACKAGE_ROOT environment variable points to your Custom Platform.
-
Compile several seeds of the
INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl
file until you generate a design that closes timing cleanly.
To specify the seed number, include the -seed=<N> option in your aoc command.
- Copy the base.qar file from the INTELFPGAOCLSDKROOT/board/a10soc/ directory into your Custom Platform.
-
Use the flat.qsf file in
the a10soc Reference Platform as references to determine the type of information
you must include in the flat.qsf file for
your Custom Platform.
The base.qsf and top.qsf files automatically inherit all the settings in the flat.qsf file. However, if you need to modify Logic Lock Plus region or PR assignments, only make these changes in the base.qsf file.
- Ensure that the environment variable CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 is not set.
- Run the boardtest_host executable.
2.8. Generating the base.qar Post-Fit Netlist for Your Intel Arria 10 SoC FPGA Custom Platform
The steps below represent a general procedure for regenerating the base.qar file:
- Port the system design and the flat.qsf file to your computing card.
- Ensure that the AOCL_BOARD_PACKAGE_ROOT environment variable points to your Custom Platform.
-
Compile the
INTELFPGAOCLSDKROOT/board/custom_platform_
toolkit/tests/boardtest/boardtest.cl kernel source file using the
base revision. Fix any timing failures and recompile the kernel until timing is
clean.
Attention: Add the -bsp-flow=base argument to the aoc command to generate a base.qar file during the kernel compilation.
- Copy the generated base.qar file (which contains the base.qdb and pr_base.id files) into your Custom Platform.
-
Using the default compilation flow, test the base.qdb file across several OpenCL™ design examples and confirm that the following
criteria are satisfied:
- All compilations close timing.
- The OpenCL design examples achieve satisfactory Fmax.
- The OpenCL design examples function on the accelerator board.
3. Building the Software and SD Card Image for the Intel Arria 10 SoC Development Kit Reference Platform
3.1. Compiling the Device Tree Blob
-
Run base revision compile (aoc -bsp-flow=base)
with your a10soc development kit BSP in the following location:
$INTELFPGAOCLSDKROOT/board/a10soc
- Start an Embedded Command Shell and navigate to the Quartus project directory from your base revision compile.
-
Invoke the following command to generate the .dts Device
Tree file, which is a text representation of the Device Tree:
sopc2dts --input board/board.sopcinfo \ --output a10soc.dts \ --board hps_a10_common_board_info.xml \ --board hps_a10_devkit_board_info.xml \ --board qsys_top_board_info.xml \ --bridge-removal all --clocks
The board.sopcinfo file is generated during the base revision compilation of your FPGA design. You may download the XML files from the Intel® Arria® 10 GHRD on Rocketboards.org.
Attention: Ensure that the name of the Intel® Arria® 10 Hard Processor System in your board.qsys file matches the name used in Intel® Arria® 10 GHRD project you are downloading the XML files from. At the time this document was written, the name of the Intel® Arria® 10 Hard Processor System in board.qsys and in Intel® Arria® 10 GHRD project was a10_hps.Create your copy of the Intel® Arria® 10 SoC BSP from the SDK, and rename the instance of the Intel® Arria® 10 Hard Processor System in board.qsys to a10_hps.
-
After you generate the .dts file, modify its contents by
performing the following tasks:
-
In the Device Tree (a10soc.dts), change the
compatible field setting to altr,
socfpga.
board_irq_ctrl_0: unknown@0x10000cfa0 { compatible = "altr,socfpga"; reg = <0x00000001 0x0000cfa0 0x00000004>, <0x00000001 0x0000cf90 0x00000004>; reg-names = "IRQ_Mask_Slave", "IRQ_Read_Slave"; interrupt-parent = <&a10_hps_arm_gic_0>; interrupts = <0 19 4>; interrupt-controller; #interrupt-cells = <1>; clocks = <&config_clk>; }; //end unknown@0x10000cfa0 (board_irq_ctrl_0)
Note:The compatible field setting in a10soc.dts must match the driver code in aclsoc.c. If the two strings do not match, the driver installation process does not allow the kernel to probe the device. As a result, the interrupt is not registered and the host code fails.
Code snippet in the aclsoc.c file:
static const struct of_device_id aclsoc_of_match[] = { { .compatible = "altr,socfpga", }, { /* end of list */ }, };
-
In the Device Tree (a10soc.dts), change the
compatible field setting to altr,
socfpga.
-
After you modify the .dts file and it is ready to probed
by the platform driver, compile the device tree blob by invoking the following
Device Tree Compiler command:
dtc -f -I dts -O dtb –o a10soc.dtb a10soc.dts
This command generates the a10soc.dtb file.
-
Rename the a10soc.dtb file to
socfpga_arria10_socdk_sdmmc.dtb.
The socfpga_arria10_socdk_sdmmc.dtb file is needed later in Building the SD Card Image.
- If you modify any of the HPS settings in the design, you must regenerate the uboot.
3.2. Compiling the Linux Kernel for the Intel Arria 10 SoC Development Kit
-
Review the GSRD Compiling Linux instructions at
the RocketBoards.org website for instructions on downloading and rebuilding the
Linux kernel source code.
For use with the Intel® FPGA SDK for OpenCL™ , determine which branch to download based on the release notes for the sdimage.img file that you download. For example, if the GSRD 18.1 sdimage.img file was created using Linux kernel v4.9.78 LTSi, look for branch socfpga-4.9.78-ltsi.
Specify your downloaded branch as the test branch name (test_branch). You can find the commands you need to run under Building Kernel & U-Boot Separately From Git Tree on the GSRD Compiling Linux page.
-
Add the following lines to the bottom of the arch/arm/configs/socfpga_defconfig file:
CONFIG_MEMORY_ISOLATION=y CONFIG_CMA=y CONFIG_DMA_CMA=y CONFIG_CMA_DEBUG=y CONFIG_CMA_SIZE_MBYTES=512 CONFIG_CMA_SIZE_SEL_MBYTES=y CONFIG_CMA_ALIGNMENT=8 CONFIG_CMA_AREAS=7
Note: The building process creates the arch/arm/configs/socfpga_defconfig file. This file specifies the settings for the socfpga default configuration.The CONFIG_CMA_SIZE_MBYTES configuration value sets the upper limit on the total number of physically contiguous memory available. You may increase this value if you require more memory.
- Run the make mrproper command to clean the current configuration.
-
Run the make ARCH=arm
socfpga_defconfig command.
ARCH=arm indicates that you want to configure the ARM architecture. socfpga_defconfig indicates that you want to use the default socfpga configuration.
-
Run the export
CROSS_COMPILE=arm-linux-gnueabihf- command.
This command sets the CROSS_COMPILE environment variable to specify the prefix of the desired tool chain.
-
Run the make ARCH=arm
zImage command. The resulting image is available in the
arch/arm/boot/zImage file.
This image file is used later in Building the SD Card Image.
3.3. Compiling the OpenCL Linux Kernel Driver
The driver source is available in the Intel® FPGA SDK for OpenCL™ installation directory. Compile the driver yourself on a host machine that has sudo and the most recent version of the SoC EDS.
- Copy the driver source from $INTELFPGAOCLSDKROOT/board/a10soc/arm32/driver/ to a new directory.
- Set the KDIR value in the driver Makefile to the directory containing the Linux kernel source files that you downloaded in Compiling the Linux Kernel for the Intel Arria 10 SoC Development Kit.
- In the new directory that contains the driver source files, run the make clean command.
-
Run the make command to
create the aclsoc_drv.ko file.
This file is used later in Building the SD Card Image.
The driver might need to be updated to work with newer version of the Linux kernel if you see the following message while building the kernel driver:aclsoc_cmd.c:165:14: error: too many arguments to function ‘get_user_pages_unlocked’ In file included from aclsoc_cmd.c:50:0
To update the driver, make the following changes to $INTELFPGAOCLSDKROOT/board/a10soc/arm32/driver/aclsoc_cmd.c:- Find the following code in
aclsoc_cmd.c:
ret = get_user_pages_unlocked(target_task, target_task->mm, start_page + got * PAGE_SIZE, num_pages - got, write, 1, p + got);
- Replace that code with the following
code:
ret = get_user_pages_remote(target_task, target_task->mm, start_page + got * PAGE_SIZE, num_pages - got, FOLL_WRITE|FOLL_FORCE, p + got, vma);
- Find the following code in
aclsoc_cmd.c:
3.4. Generating Full-Chip Programming File for SD Card Image
This .rbf file is used to program the Intel® Arria® 10 SoC FPGA during power up.
Follow one of the following methods to generate the socfpga.rbf file in a directory containing an aocx file for your Intel® Arria® 10 SoC custom platform:
- If your aocx file is compiled with flat or base revision,
execute the following
commands:
aocl binedit <.aocx> get .acl.fpga.bin .temp.fpga.bin aocl binedit .temp.fpga.bin get .acl.sof .temp.sof sof2flash --offset=0 --input="./.temp.sof" --output="./.temp_sof2rbf.flash" nios2-elf-objcopy -I srec -O binary "./.temp_sof2rbf.flash" "./socfpga.rbf" rm .temp.fpga.bin .temp.sof .temp_sof2rbf.flash
- If your aocx file is compiled with top revision, go to
the working directory of this aocx kernel and execute the
following commands:
sof2flash --offset=0 --input="./top.sof" --output="./.temp_sof2rbf.flash" nios2-elf-objcopy -I srec -O binary "./.temp_sof2rbf.flash" "./socfpga.rbf" rm .temp_sof2rbf.flash
After generating the socfpga.rbf file, place it in FAT32 partition of the flash card image.
3.5. Building the SD Card Image
3.5.1. Layout of the OpenCL Micro SD Card
Location | File Name | Description |
---|---|---|
Partition 1 | socfpga_arria10_socdk_sdmmc.dtb | The device tree blob that describes the peripherals available to the system. Refer to Compiling the Device Tree Blob for more information. |
socfpga.rbf |
The full-chip .rbf (Raw Binary file) file generated from Quartus compile. This is different from the PR .rbf file. Refer to Generating Full-Chip Programming File for SD Card Image for more details. |
|
zImage | The compressed kernel image. Refer to Recompiling the Linux Kernel for the Intel Arria® 10 SoC Development Kit for more information. | |
Partition 2 | Various rootfs files | Partition 2 is a Linux partition that contains the uncompressed
root file system (rootfs). You modify this partition in Creating the SD Card Image. |
Partition 3 | uboot_w_dtb-mkpimage.bin | Partition 3 must be of type a2. The Master Boot Record recognizes
the partition and then loads the uboot_w_dtb-mkpimage.bin bootloader from it. Note: The uboot_w_dtb-mkpimage.bin file
is written into the a3 partition.
Generating U-boot and device tree section in Arria 10 GSRD user manual or the Boot Tools User Guide chapter of the Intel SoC FPGA Embedded Design Suite User Guide describes how to create the uboot_w_dtb-mkpimage.bin file and provides information on the relevant tools. |
3.5.2. Creating the SD Card Image
You must modify the GSRD 18.1 sdimage.img file to support the Intel Arria 10 SoC BSP and run OpenCL applications.
Before you create the SD card image, download the GSRD 18.1 sdimage.tar.gz file from the following URL: https://rocketboards.org/foswiki/Documentation/GSRD181ReleaseNotes#Release_Contents.
Create the SD card partitions and their contents by following the instructions in the following sections:
- Partition 1: Creating Partition 1 of the SD Card Image.
- Partition 2 (rootfs): Creating Partition 2 of the SD Card Image.
- Partition 3: Creating Partition 3 of the SD Card Image.
3.5.2.1. Creating Partition 1 of the SD Card Image
To create partition 1 of the SD card image:
-
Mount the FAT32 partition (partition 1) in the
sdimage.img file as a loop-back device.
To mount a partition:
- Determine the byte start of the partition within the image with the
/sbin/fdisk -lu image_file
command.
For example, partition number 1 of type W95 FAT has a block offset of 2121728. With 512 bytes per block, the byte offset is 512 bytes x 2121728 = 1086324736 bytes.
- Identify a free loop device (for example, /dev/loop0) by typing the losetup -f command.
- Assign your flash card image to the loop block device by invoking the
losetup command.For example, if /dev/loop0 is the free loop device, issue the following command:
losetup /dev/loop0 image_file -o <byte offset>
- Mount the loop device.For example, if /dev/loop0 is the loop device and the mount point is /media/disk1, issue the following command:Within the image file, /media/disk1 is now a mounted FAT32 partition.
mount /dev/loop0 /media/disk1
- Determine the byte start of the partition within the image with the
/sbin/fdisk -lu image_file
command.
- Remove all files from the mounted directory, and copy socfpga_arria10_socdk_sdmmc.dtb, socfpga.rbf and zImage to the partition.
-
After you store all the necessary files onto the flash card image, run
the following commands:
sync umount /media/disk1 losetup -d /dev/loop0
3.5.2.2. Creating Partition 2 of the SD Card Image
To create partition 2 of the SD card image:
-
Mount partition 2 in the sdimage.img file as a
loop-back device.
To mount a partition:
- Determine the byte start of the partition within the image by invoking the /sbin/fdisk -lu image_file command.
- Identify a free loop device (for example, /dev/loop0) by typing the losetup -f command.
- Assign your flash card image to the loop block device by
invoking the losetup command.For example, if /dev/loop0 is the free loop device, issue the following command:
losetup /dev/loop0 image_file -o <byte offset>
- Mount the loop device.For example, if /dev/loop0 is the loop device and the mount point is media/disk2, issue the following command:Within the image file, media/disk2 is now mounted.
mount /dev/loop0 media/disk2
-
From the
Intel®
Download Center for FPGAs,
download and unpack the
Intel®
FPGA Runtime
Environment for
OpenCL*
Linux
Cyclone® V SoC TGZ
file:
To download and unpack the file:
- Go the Intel® Download Center for FPGAs page for the Intel® FPGA SDK for OpenCL™ at the following URL: http://fpgasoftware.intel.com/opencl/?edition=pro.
- Click the RTE tab, select Intel FPGA Runtime Environment for OpenCL Linux SoC TGZ, and click Download to download the file.
- Unpack the downloaded file (aocl-rte-<version>.arm32.tgz) to a directory that you own.
- Place the unpacked aocl-rte-<version>.arm32 directory into the /home/root/opencl_arm32_rte directory on partition 2 of the image file.
- Copy aclsoc_drv.ko to the /home/root/opencl_arm32_rte/board/a10soc/arm32/driver/ directory on partition 2 of the image file.
-
Create the init_opencl.sh file in the
/home/root directory with the following
content:
export INTELFPGAOCLSDKROOT=/home/root/opencl_arm32_rte export AOCL_BOARD_PACKAGE_ROOT=$INTELFPGAOCLSDKROOT/board/a10soc export PATH=$INTELFPGAOCLSDKROOT/bin:$PATH export LD_LIBRARY_PATH=$INTELFPGAOCLSDKROOT/host/arm32/lib:$LD_LIBRARY_PATH insmod $AOCL_BOARD_PACKAGE_ROOT/arm32/driver/aclsoc_drv.ko
The SDK user runs a source ./init_opencl.sh command to load the environment variables and the OpenCL* Linux kernel driver.
-
After you store all the necessary files onto the flash card image, run
the following commands:
sync umount media/disk2 losetup -d /dev/loop0
3.5.2.3. Creating Partition 3 of the SD Card Image
To create partition 3 of the SD card image:
-
Mount partition 3 in the sdimage.img file as a loop-back device.
To mount a partition:
- Determine the byte start of the partition within the image with the /sbin/fdisk -lu image_file command.
- Identify a free loop device (for example, /dev/loop0) by typing the losetup -f command.
- Assign your flash card image to the loop block device
by invoking the losetup command.For example, if /dev/loop0 is the free loop device, issue the following command:
losetup /dev/loop0 image_file -o <byte offset>
-
Generate the uboot_w_dtb-mkpimage.bin file:
- Run an OpenCL compilation with the -bsp-flow=base option.
- Generate U-boot and device tree according to the
instructions at the following URL:https://rocketboards.org/foswiki/Documentation/A10GSRDGeneratingUBootAndUBootDeviceTree
The instructions require the following exceptions or additional information in the Generating Bootloader section:
- Step 5: Do not browse to the folder
referenced. Browse to the hps_isw_handoff folder in the output
directory of your earlier -bsp-flow=base OpenCL compilation.
For an <OpenCL_file>.cl file, the folder is typically <OpenCL_file>/hps_isw_handoff.
- Step 9: The rbf_filename field is set to socfpga.rbf. Do not change this value. Leave the value as socfpga.rbf.
- Step 5: Do not browse to the folder
referenced. Browse to the hps_isw_handoff folder in the output
directory of your earlier -bsp-flow=base OpenCL compilation.
-
Update the uboot_w_dtb-mkpimage.bin file by following the instructions in
the Updating Individual Elements on the SD
card section of Creating and Updating the
SD Card page available at the following URL: https://rocketboards.org/foswiki/Documentation/A10GSRDCreatingAndUpdatingTheSDCardLTS
For example, sudo dd if=uboot_w_dtb-mkpimage.bin of=/dev/loop0 bs=64k seek=0.
-
Delete the loop device with the following commands:
sync losetup -d /dev/loop0
3.5.3. Guidelines on Imaging the Micro SD Card
General recommendations and resources for imaging the micro SD card:
- Use the Linux fdisk command to create,
delete, or modify existing partitions on the GSRD SD card image. Use the Linux dd command to write file systems to the existing partitions on
the GSRD SD card image.Important: To use these commands, you must have extensive Linux knowledge and have sudo on your machine.
- Rocketboards.org provides a python script that generates a .bin file. You can write this .bin file to the micro SD card. Refer to the Creating and Updating the SD Card section of the Arria 10 GSRD v17.1 User Manual for more information.
- Intel® provides the alt-boot-disk-util SD card boot utility to create SD boot images. For more information, refer to the SD Card Boot Utility chapter of the Intel SoC FPGA Embedded Design Suite User Guide.
The different partitions in the micro SD card are related to each other. For example, if the OpenCL .rbf file is not programmed onto the FPGA, the driver will not load. In addition, the socfpga.rbf file will not program the board when you boot it up if the .rbf file name does not match the label in the bootloader library. Before modifying the SD card image, consider whether the modification is necessary for your design.
3.6. Known Issues
- You cannot override the vendor and board names that the CL_DEVICE_VENDOR and CL_DEVICE_NAME strings of the clGetDeviceInfo() call reports, respectively.
- If the host allocates constant memory in the shared DDR system (that is,
HPS DDR) and it modifies the constant memory after kernel execution, the data in memory
might become updated. This issue arises because the FPGA core cannot snoop on CPU-to-HPS DDR
transactions.
To prevent subsequent kernel executions from accessing outdated data, implement one of the following workarounds:
- Do not modify constant memory after its initialization.
- If you require multiple __constant data sets, create multiple constant memory buffers.
- If available, allocate constant memory in the FPGA DDR on your accelerator board.
- The SDK utility on
ARM® only supports the program and diagnose utility commands. The
flash, install, and
uninstall utility commands are not applicable to the
Intel Arria®
10 SoC Development Kit for the following reasons:
- The install utility has to compile
the aclsoc_drv Linux kernel driver and enable it on
the SoC. The development machine has to perform the compilation; however, it already
contains Linux kernel sources for the SoC. The Linux kernel sources for the development
machine are different from those for the SoC. The location of the Linux kernel sources
for the SoC is likely unknown to the SDK user. Similarly, the uninstall utility is also unavailable to the Intel Arria® 10 SoC
Development Kit.
Also, delivering aclsoc_drv to the SoC board is challenging because the default distribution of the Intel Arria® 10 SoC Development Kit does not contain Linux kernel include files or the GNU Compiler Collection (GCC) compiler.
- The flash utility requires placing a .rbf file of an OpenCL design onto the FAT32 partition of the micro SD flash card. Currently, this partition is not mounted when the SDK user powers up the board. Therefore, the best way to update the partition is to use a flash card reader and the development machine.
- The install utility has to compile
the aclsoc_drv Linux kernel driver and enable it on
the SoC. The development machine has to perform the compilation; however, it already
contains Linux kernel sources for the SoC. The Linux kernel sources for the development
machine are different from those for the SoC. The location of the Linux kernel sources
for the SoC is likely unknown to the SDK user. Similarly, the uninstall utility is also unavailable to the Intel Arria® 10 SoC
Development Kit.
- When switching between the Intel® FPGA SDK for OpenCL™ Offline Compiler executable files (.aocx) that correspond to different board variants (that is, a10soc and a10soc_2ddr), you must use the SDK's program utility to load the .aocx file for the new board variant for the first time. If you simply run the host application using a new board variant but the FPGA contains the image from another board variant, a fatal error might occur.
- When you power up the board, it does not acquire an IP address by default. Invoke the ifup etho command to initiate IP address acquisition.
4. Intel FPGA SDK for OpenCL Intel Arria 10 SoC Development Kit Reference Platform Porting Guide Archives
Intel® Quartus® Prime Version | User Guide |
---|---|
19.1 | Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide |
18.1.2 | Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide |
18.0 | Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide |
17.1 | Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide |
17.0 | Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide |
5. Document Revision History for Intel FPGA SDK for OpenCL : Intel Arria 10 SoC Development Kit Reference Platform Porting Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.10.08 | 19.1 | Made the following bug fixes:
|
2019.04.01 | 19.1 |
|
2019.02.18 | 18.1.2 |
|
Date | Version | Changes |
---|---|---|
September 2018 | 2018.09.17 | Added Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.1.2 to 18.0 |
November 2017 | 2017.11.03 |
|
May 2017 | 2017.05.08 |
|
October 2016 | 2016.10.31 | Initial release. |