AN 805: Hierarchical Partial Reconfiguration of a Design on Intel Arria 10 SoC Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria 10 SoC Development Board
Hierarchical partial reconfiguration (HPR) is a special type of partial reconfiguration (PR), where you contain a PR region within another PR region. You can create multiple personas for both the child and parent partitions. You nest the child partitions within their parent partitions. Reconfiguring a child partition does not impact operation in the parent or static regions. Reconfiguring a parent partition does not impact the operation in the static region, but replaces the child partitions of the parent region with default child partition personas. This methodology is effective in systems where multiple functions time-share the same FPGA device resources.
- Allows run-time design reconfiguration
- Increases scalability of the design
- Reduces system down-time
- Supports dynamic time-multiplexing functions in the design
- Lowers cost and power consumption through efficient use of board space
- Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files.
Reference Design Requirements
- Intel® Quartus® Prime Pro Edition software version 17.1 for the design implementation.
- Intel® Arria® 10 SoC development kit for the FPGA implementation.
Reference Design Overview
Reference Design Files
The partial reconfiguration tutorial is available in the following location:
https://github.com/intel/fpga-partial-reconfig
- Click Clone or download.
- Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
- Navigate to the tutorials/a10_soc_devkit_blinking_led_hpr sub-folder to access the reference design.
File Name | Description |
---|---|
top.sv |
Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module. |
top_counter.sv | Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module. |
blinking_led.sdc |
Defines the timing constraints for the project. |
blinking_led.sv | In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3]. |
blinking_led.qpf |
Intel® Quartus® Prime project file containing the list of all the revisions in the project. |
blinking_led.qsf |
Intel® Quartus® Prime settings file containing the assignments and settings for the project. |
Reference Design Walkthrough
- Step 1: Getting Started
- Step 2: Creating a Child Level Sub-module
- Step 3: Creating Design Partitions
- Step 4: Allocating Placement and Routing Region for PR Partitions
- Step 5: Adding the Intel Arria 10 Partial Reconfiguration Controller IP Core
- Step 6: Defining Personas
- Step 7: Creating Revisions
- Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script
- Step 9: Running the Hierarchical Partial Reconfiguration Flow Script
- Step 10: Programming the Board
Step 1: Getting Started
- Create a directory in your working environment, a10_soc_devkit_blinking_led_hpr.
- Copy the downloaded tutorials/a10_soc_devkit_blinking_led_hpr/flat sub-folder to the directory, a10_soc_devkit_blinking_led_hpr.
- In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
- To compile the flat design, click Processing > Start Compilation.
Step 2: Creating a Child Level Sub-module
- Create a new design file, blinking_led_child.sv, and add the following lines of code to this
file:
`timescale 1 ps / 1 ps `default_nettype none module blinking_led_child ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_three_on ); localparam COUNTER_TAP = 23; reg led_three_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_three_on_r <= counter[COUNTER_TAP]; end endmodule
- Modify the blinking_led.sv file to
connect the led_two_on to bit 23 of the counter from the
static region, and instantiate the blinking_led_child
module. After modifications, your blinking_led.sv
file must appear as
follows:
`timescale 1 ps / 1 ps `default_nettype none module blinking_led( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); localparam COUNTER_TAP = 23; reg led_two_on_r; assign led_two_on = led_two_on_r; // The counter: always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP]; end blinking_led_child u_blinking_led_child ( .led_three_on (led_three_on), .counter (counter), .clock (clock) ); endmodule
- On modifying all the design files, recompile the project by clicking Processing > Start Compilation
Step 3: Creating Design Partitions
- Right-click the u_blinking_led_child
instance in the Project Navigator and click
Design Partition > Set as Design Partition. A design partition icon appears next to each instance that is set as a
partition.
Figure 3. Creating Design Partitions from Project Navigator
- To define the partition Type,
right-click the u_blinking_led_child instance in the
Hierarchy tab, click Design Partition > Reconfigurable. You can only define the partition Type after setting the instance as a partition.
The design partition appears on the Assignments View tab of the Design Partitions Window.Figure 4. Design Partitions Window
- Edit the partition name in the Design Partitions Window by
double-clicking the name. For this reference design, rename the partition name to pr_partition.
Note: When you create a partition, the Intel® Quartus® Prime software automatically generates a partition name, based on the instance name and hierarchy path. This default partition name can vary with each instance.
- Repeat steps 1 and 2 to assign reconfigurable design partitions to the u_blinking_led instance. Rename this partition to pr_parent_partition.
set_instance_assignment -name PARTITION pr_partition -to \ u_blinking_led|u_blinking_led_child set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \ u_blinking_led|u_blinking_led_child set_instance_assignment -name PARTITION pr_parent_partition -to u_blinking_led set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \ u_blinking_led
Step 4: Allocating Placement and Routing Region for PR Partitions
- Right-click the u_blinking_led_child instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region. The region appears on the Logic Lock Regions Window.
- Your placement region must enclose the blinking_led_child logic. Select the placement region by locating the node in
Chip Planner. Right-click the u_blinking_led_child region
name in the Project Navigator and click
Locate Node > Locate in Chip Planner.
Figure 5. Chip Planner Node Location for blinking_led
- In the Logic Lock Regions
window, specify the placement region co-ordinates in the Origin column. The origin corresponds to the lower-left corner of the
region. For example, to set a placement region with (X1
Y1) co-ordinates as (69 10), specify the
Origin as
X69_Y10. The
Intel®
Quartus® Prime software automatically
calculates the (X2 Y2) co-ordinates (top-right) for the
placement region, based on the height and width you specify.
Note: This tutorial uses the (X1 Y1) co-ordinates - (69 10), and a height and width of 20 for the placement region. Define any value for the placement region, provided that the region covers the blinking_led_child logic.
- Enable the Reserved and Core-Only options.
- Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
- Select Fixed with expansion for
the Routing type. Selecting this option
automatically assigns an expansion length of 1.
Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.
- Repeat steps 1 -6 for the u_blinking_led instance. The parent-level placement region must fully enclose
the corresponding child-level placement and routing regions, while allowing sufficient
space for the parent-level logic placement. This tutorial uses the (X1 Y1) co-ordinates - (66
7), a height of 47, and width of 26 for the placement region of the u_blinking_led instance.
Figure 6. Logic Lock Regions Window
set_instance_assignment -name PLACE_REGION "69 10 88 29" -to \ u_blinking_led|u_blinking_led_child set_instance_assignment -name RESERVE_PLACE_REGION ON -to \ u_blinking_led|u_blinking_led_child set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \ u_blinking_led|u_blinking_led_child set_instance_assignment -name ROUTE_REGION "68 9 89 30" -to \ u_blinking_led|u_blinking_led_child set_instance_assignment -name PLACE_REGION "66 7 112 32" -to u_blinking_led set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_blinking_led set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_blinking_led set_instance_assignment -name ROUTE_REGION "65 6 113 33" -to u_blinking_led
Step 5: Adding the Intel Arria 10 Partial Reconfiguration Controller IP Core
- Type Partial Reconfiguration in the IP catalog.
- To launch the IP Parameter Editor Pro window, select the Intel® Arria® 10 Partial Reconfiguration Controller IP core from the IP library, and click Add.
- In the New IP Variant
dialog box, type pr_ip as the file name and
click Create. Use the default
parameterization for pr_ip. Ensure that the
Enable JTAG debug mode and
Enable freeze interface options are
turned on, and Enable Avalon-MM slave
interface option is turned off.
Figure 7. Intel® Arria® 10 Partial Reconfiguration Controller IP Core Parameters
- Click Finish, and exit the parameter editor without generating the system. Intel® Quartus® Prime software creates the pr_ip.ip IP variation file, and adds the file to the blinking_led project.
- If you are copying the pr_ip.ip file from the hpr folder, manually edit the blinking_led.qsf file to include the following
line:
set_global_assignment -name IP_FILE pr_ip.ip
- Place the IP_FILE
assignment after the SDC_FILE assignments
(jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures
appropriate constraining of the Partial Reconfiguration IP core.
Note: To detect the clocks, the SDC file for the PR IP must follow any SDC that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or SDC files used to create these clocks in the QSF file for your Intel® Quartus® Prime project revision. For more information, refer to Timing Constraints section in the Partial Reconfiguration IP Core User Guide.
Updating the Top-Level Design
- To add the PR_IP instance to the
top-level design, uncomment the following code block in top.sv file:
pr_ip u_pr_ip ( .clk (clock), .nreset (1'b1), .freeze (freeze), .pr_start (1'b0), // ignored for JTAG .status (pr_ip_status), .data (16'b0), .data_valid (1'b0), .data_ready () );
- To force the output ports to logic 1 during reconfiguration, use the
freeze control signal output from PR_IP.
However, to observe the LED continue blinking from the parent PR partition while
PR programming the child partition, the freeze control signal does not turn off
the led_two_on. Ensure that the pr_led_two_on is directly assigned to led_two_on_w. led_three_on_w must choose between logic 1 and pr_led_three_on, based on the freeze signal.
Uncomment the following lines of
code:
assign led_two_on_w = pr_led_two_on; assign led_three_on_w = freeze ? 1'b1 : pr_led_three_on;
- To assign an instance of the default parent persona (blinking_led), update the top.sv file with the following block of
code:
blinking_led u_blinking_led ( .clock (clock), .counter (count_d), .led_two_on (pr_led_two_on), .led_three_on (pr_led_three_on) );
Step 6: Defining Personas
- Create four SystemVerilog files, blinking_led_child.sv, blinking_led_child_slow.sv, blinking_led_child_empty.sv, and blinking_led_slow.sv in your working directory for the five
personas.
Note: If you create the SystemVerilog files from the Intel® Quartus® Prime Text Editor, disable the Add file to current project option, when saving the files.
Table 2. Reference Design Personas File Name Description Code blinking_led_child.sv Default persona for the child-level design `timescale 1 ps / 1 ps `default_nettype none module blinking_led_child ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_three_on ); localparam COUNTER_TAP = 23; reg led_three_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_three_on_r <= counter[COUNTER_TAP]; end endmodule
blinking_led_child_slow.sv The LED_THREE blinks slower `timescale 1 ps / 1 ps `default_nettype none module blinking_led_child_slow ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_three_on ); localparam COUNTER_TAP = 27; reg led_three_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_three_on_r <= counter[COUNTER_TAP]; end endmodule
blinking_led_child_empty.sv The LED_THREE stays ON `timescale 1 ps / 1 ps `default_nettype none module blinking_led_child_empty ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_three_on ); // LED is active low assign led_three_on = 1'b0; endmodule
blinking_led_slow.sv The LED_TWO blinks slower. `timescale 1 ps / 1 ps `default_nettype none module blinking_led_slow( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); localparam COUNTER_TAP = 27; reg led_two_on_r; assign led_two_on = led_two_on_r; // The counter: always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP]; end blinking_led_child u_blinking_led_child( .led_three_on (led_three_on), .counter (counter), .clock (clock) ); endmodule
Step 7: Creating Revisions
The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.
Synthesis Revision | Implementation Revision |
---|---|
blinking_led_parent, blinking_led_default | blinking_led_pr_alpha |
blinking_led_parent, blinking_led_child_slow | blinking_led_pr_bravo |
blinking_led_parent, blinking_led_child_empty | blinking_led_pr_charlie |
blinking_led_parent_slow, blinking_led_child_slow | blinking_led_pr_delta |
blinking_led_parent_slow, blinking_led_child_empty | blinking_led_pr_emma |
Creating Implementation Revisions
- To open the Revisions dialog box, click Project > Revisions.
- To create a new revision, double-click <<new revision>>.
- Specify the Revision name as blinking_led_pr_alpha and select blinking_led for Based on Revision.
- Disable the Set as current revision option and click OK.
- Similarly, create blinking_led_pr_bravo, blinking_led_pr_charlie,
blinking_led_pr_delta, and blinking_led_pr_emma revisions, based on the blinking_led revision.
Note: Do not set the above revisions as current revision.

Creating Synthesis-Only Revisions
- In the Intel® Quartus® Prime software, click Project > Revisions.
- Create blinking_led_default revision based on blinking_led revision. Do not set this revision as current revision.
- Modify blinking_led_default.qsf file
to include the following
assignments:
set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_child set_global_assignment -name SYSTEMVERILOG_FILE
- Similarly, create blinking_led_child_slow, blinking_led_child_empty, blinking_led_parent, and blinking_led_parent_slow revisions based on blinking_led revision. Do not set these revisions as current revision.
- Update the blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, and blinking_led_parent_slow.qsf files with their corresponding TOP_LEVEL_ENTITY
and SYSTEMVERILOG_FILE
assignments:
##blinking_led_child_slow.qsf set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_child_slow set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child_slow.sv
##blinking_led_child_empty.qsf set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_child_empty set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child_empty.sv
##blinking_led_parent.qsf set_global_assignment -name TOP_LEVEL_ENTITY blinking_led set_global_assignment -name SYSTEMVERILOG_FILE blinking_led.sv set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child.sv
##blinking_led_parent_slow.qsf set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_slow set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_slow.sv set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child.sv
- To avoid synthesis errors, ensure that the synthesis revision files for
the child partitions do not contain any design partition, pin assignments, or Logic Lock region assignments. Also, the synthesis
revision files for the parent partitions must only contain design partition assignments
for the corresponding child partitions. Remove these assignments, if any, in the blinking_led_default.qsf, blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, and blinking_led_parent_slow.qsf
files:
#set_instance_assignment -name PARTITION pr_partition -to \ u_blinking_led|u_blinking_led_child #set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \ u_blinking_led|u_blinking_led_child #set_instance_assignment -name PLACE_REGION "69 10 88 29" -to \ u_blinking_led|u_blinking_led_child #set_instance_assignment -name RESERVE_PLACE_REGION ON -to \ u_blinking_led|u_blinking_led_child #set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \ u_blinking_led|u_blinking_led_child #set_instance_assignment -name ROUTE_REGION "68 9 89 30" -to \ u_blinking_led|u_blinking_led_child #set_instance_assignment -name PARTITION pr_parent_partition -to \ u_blinking_led #set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \ u_blinking_led #set_instance_assignment -name PLACE_REGION “66 7 112 32” -to \ u_blinking_led #set_instance_assignment -name RESERVE_PLACE_REGION ON -to \ u_blinking_led #set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \ u_blinking_led #set_instance_assignment -name ROUTE_REGION “65 6 113 33” -to \ u_blinking_led
- Include the following assignments in blinking_led_parent.qsf and blinking_led_parent_slow.qsf
files:
set_instance_assignment -name PARTITION pr_partition -to \ u_blinking_led_child set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \ u_blinking_led_child
- Verify that the blinking_led.qpf
file contains the following revisions, in no particular
order:
PROJECT_REVISION = "blinking_led" PROJECT_REVISION = "blinking_led_pr_alpha" PROJECT_REVISION = "blinking_led_pr_bravo" PROJECT_REVISION = "blinking_led_pr_charlie" PROJECT_REVISION = “blinking_led_pr_delta” PROJECT_REVISION = “blinking_led_pr_emma” PROJECT_REVISION = "blinking_led_default" PROJECT_REVISION = "blinking_led_child_slow" PROJECT_REVISION = "blinking_led_child_empty" PROJECT_REVISION = “blinking_led” PROJECT_REVISION = “blinking_led_slow”
Note: If you are copying the revision files from hpr folder, manually update the blinking_led.qpf file with the above lines of code.
Specifying Revision Type
- Partial Reconfiguration - Base
- Partial Reconfiguration - Persona Synthesis
- Partial Reconfiguration - Persona Implementation
Revision Name | Revision Type |
---|---|
blinking_led.qsf | Partial Reconfiguration - Base |
blinking_led_default.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_child_empty.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_child_slow.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_parent.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_parent_slow.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_pr_alpha.qsf | Partial Reconfiguration - Persona Implementation |
blinking_led_pr_bravo.qsf | Partial Reconfiguration - Persona Implementation |
blinking_led_pr_charlie.qsf | Partial Reconfiguration - Persona Implementation |
blinking_led_pr_delta.qsf | Partial Reconfiguration - Persona Implementation |
blinking_led_pr_emma.qsf | Partial Reconfiguration - Persona Implementation |
- Click Project > Revisions. The Revisions dialog box appears.
- Select blinking_led in the Revision Name column, and click Set Current.
- Click Apply. The blinking_led revision opens.
- To set the revision type for blinking_led, click Assignments > Settings > General.
- Select the Revision Type as Partial Reconfiguration - Base.
- Similarly, set the revision types for the other ten revisions, as
listed in the above table.
Note: You must set each revision as the current revision before assigning the revision type.
##blinking_led.qsf
set_global_assignment -name REVISION_TYPE PR_BASE
##blinking_led_default.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_child_slow.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_child_empty.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_pr_alpha.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
##blinking_led_parent.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_parent_slow.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_pr_bravo.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
##blinking_led_pr_charlie.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
##blinking_led_pr_delta.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
##blinking_led_pr_emma.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script
-
From the
Intel®
Quartus® Prime command shell, create a
flow template by running the following command:
quartus_sh --write_flow_template -flow a10_hier_partial_reconfig
Intel® Quartus® Prime generates the a10_hier_partial_reconfig/flow.tcl file. -
Rename the generated a10_hier_partial_reconfig/setup.tcl.example to a10_hier_partial_reconfig/setup.tcl, and
modify the script to specify your partial reconfiguration project details:
-
To define the name of the project, update the following
line:
define_project blinking_led
-
To define the base revision, update the following
line:
define_base_revision blinking_led
-
To define each of the partial reconfiguration
implementation revisions, along with the PR partition names and the
source revision that implements the revisions, update the following
lines:
############################################################################### # SETUP CONFIGURTION SCRIPT ############################################################################### # Define the name of the project. define_project blinking_led # Define the base revision name. This revision represents the static # region of the design define_base_revision blinking_led # Define each of the partial reconfiguration implementation revisions define_pr_impl_partition -impl_rev_name blinking_led_pr_alpha \ -partition_name pr_partition \ -source_rev_name blinking_led_default \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_alpha \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_parent \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_bravo \ -partition_name pr_partition \ -source_rev_name blinking_led_child_slow \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_bravo \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_alpha \ -source_partition pr_parent_partition \ -source_snapshot final define_pr_impl_partition -impl_rev_name blinking_led_pr_charlie \ -partition_name pr_partition \ -source_rev_name blinking_led_child_empty \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_charlie \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_alpha \ -source_partition pr_parent_partition \ -source_snapshot final define_pr_impl_partition -impl_rev_name blinking_led_pr_delta \ -partition_name pr_partition \ -source_rev_name blinking_led_child_slow \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_delta \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_parent_slow \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_emma \ -partition_name pr_partition \ -source_rev_name blinking_led_child_empty \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_emma \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_delta \ -source_partition pr_parent_partition
Note: All the revision projects must be in the same directory as blinking_led.qpf. Otherwise, update the flow script accordingly.
-
To define the name of the project, update the following
line:
Step 9: Running the Hierarchical Partial Reconfiguration Flow Script
To run the hierarchical partial reconfiguration flow script:
- Click Tools > Tcl Scripts. The Tcl Scripts dialog box appears.
- Click Add to Project, browse and select the a10_hier_partial_reconfig/flow.tcl.
-
Select the a10_hier_partial_reconfig/flow.tcl in the Libraries pane, and
click Run.
This script runs the synthesis for the three personas. Intel® Quartus® Prime generates a SRAM Object File (.sof), a Partial-Masked SRAM Object File (.pmsf), and a Raw Binary File (.rbf) for each of the personas.
quartus_sh -t a10_hier_partial_reconfig/flow.tcl -setup_script \ a10_hier_partial_reconfig/setup.tcl
Step 10: Programming the Board
- Connect the power supply to the Intel® Arria® 10 SoC development board.
- Connect the USB Blaster cable between your PC USB port and the USB Blaster port on the development board.
To run the design on the Intel® Arria® 10 SoC development board:
- Open the Intel® Quartus® Prime software and click Tools > Programmer.
- In the Programmer, click Hardware Setup and select USB-Blaster.
- Click Auto Detect and select the device, 10AS066N3.
- Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the three FPGA chips on the board.
- Select the 10AS066N3 device, click Change File and load the blinking_led_pr_alpha.sof file.
- Enable Program/Configure for blinking_led_pr_alpha.sof file.
- Click Start and wait for the progress bar to reach 100%.
- Observe the LEDs on the board blinking at the same frequency as the original flat design.
- To program only the child PR region, right-click the blinking_led_pr_alpha.sof file in the Programmer and click Add PR Programming File.
- Select the blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file.
- Disable Program/Configure for blinking_led_pr_alpha.sof file.
- Enable Program/Configure for blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] blinks at the same rate, and LED[3] blinks slower.
- To program both the parent and child PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
- Select the blinking_led_pr_delta.pr_parent_partition.rbf file.
- Click Start. On the board, observe that LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, both LED[2] and LED[3] blink slower.
- Repeat the above steps to dynamically re-program just the child PR region, or both the parent and child PR regions simultaneously.
Modifying an Existing Persona
For example, to cause the blinking_led_child_slow persona to blink even slower:
- In the blinking_led_child_slow.sv file, modify the COUNTER_TAP parameter from 27 to 28.
-
To re-synthesize and re-implement this persona, you must
recompile all the synthesis-only revisions and implementation revisions affected
by the change. Modify the setup.tcl script to include the
following lines:
define_project blinking_led define_base_revision blinking_led define_pr_impl_partition -impl_rev_name blinking_led_pr_bravo \ -partition_name pr_partition \ -source_rev_name blinking_led_child_slow \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_bravo \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_alpha \ -source_partition pr_parent_partition \ -source_snapshot final define_pr_impl_partition -impl_rev_name blinking_led_pr_delta \ -partition_name pr_partition \ -source_rev_name blinking_led_child_slow \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_delta \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_delta \ -source_partition pr_parent_partition \ -source_snapshot final
Note: When defining the pr_parent_parition for blinking_led_pr_delta revision, you import the final snapshot of that persona for implementation. As a result, the implementation of the parent partition logic remains the same, while modifying and implementing the corresponding child partition.This command re-synthesizes the blinking_led_child_slow synthesis revision, and then runs the PR implementation compile using blinking_led_pr_bravo. -
To perform compilation of the synthesis-only revisions, run the following
command:
quartus_sh -t a10_hier_partial_reconfig/flow.tcl -setup_script \ a10_hier_partial_reconfig/setup.tcl -all_syn
This command does not recompile the base revision.
-
To perform compilation of the implementation revisions, run the following
command:
quartus_sh -t a10_hier_partial_reconfig/flow.tcl -setup_script \ a10_hier_partial_reconfig/setup.tcl -all_impl
This command does not recompile the base revision.
- Follow the steps in Step 10: Programming the Board to program the resulting RBF file into the FPGA.
Adding a New Persona to the Design
For example, to define a new child persona for blinking_led_parent_slow, that turns led_three off:
- Copy blinking_led_child_empty.sv to blinking_led_chdild_off.sv.
- In the blinking_led_child_off.sv file, modify the assignment, assign led_three_on = 1'b0; to assign led_three_on = 1'b1;. Ensure you change the module name from blinking_led_child_empty to blinking_led_child_off .
-
Create a new synthesis revision, blinking_led_child_off, by following the steps in Creating Synthesis-Only Revisions.
Note: The blinking_led_child_off revision must use the blinking_led_child_off.sv file.
- Create a new implementation revision, blinking_led_pr_foxtrot, by following the steps in Creating Implementation Revisions.
-
Update the a10_hier_partial_reconfig/setup.tcl file to define the new PR
implementation:
define_pr_impl_partition -impl_rev_name blinking_led_pr_foxtrot \ -partition_name pr_partition \ -source_rev_name blinking_led_child_off \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_foxtrot \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_delta \ -source_partition pr_parent_partition \ -source_snapshot final
-
Compile just this new synthesis and implementation revision by
running the following command:
quartus_sh –t a10_hier_partial_reconfig/flow.tcl –setup_script \ a10_hier_partial_reconfig/setup.tcl –all_syn quartus_sh -t a10_hier_partial_reconfig/flow.tcl -setup_script \ a10_hier_partial_reconfig/setup.tcl -all_impl
For complete information on hierarchical partial reconfiguration for Intel® Arria® 10 devices, refer to Creating a Partial Reconfiguration Design in Volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.
Document Revision History
Document Version | Software Version | Changes |
---|---|---|
2017.11.06 |
17.1.0 |
|
2017.05.08 |
17.0.0 |
Initial release of the document |