AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

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ID 683607
Date 8/24/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Intel® Quartus® Prime Software Guidelines 4. Device Guidelines 5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines
2. Overview x
2.1. Available Device Options and Ordering Part Numbers
3. Intel® Quartus® Prime Software Guidelines x
3.1. Design Migration 3.2. Intel® Quartus® Prime Software Patch Compatibility 3.3. Related Intel® Quartus® Prime Software Error Messages
4. Device Guidelines x
4.1. Device Configuration Guidelines 4.2. GPIO and LVDS Guidelines 4.3. Transceiver Guidelines 4.4. Error Message for Design Exceeding Maximum Transceiver Bandwidth
4.2. GPIO and LVDS Guidelines x
4.2.1. I/O Resource Comparison Between Standard OPN and IOL OPN Devices 4.2.2. Design Migration 4.2.3. Error Message for > 700 Pins Utilization
4.3. Transceiver Guidelines x
4.3.1. Transceiver Bandwidth Calculation
1. Introduction
2. Overview
3. Intel® Quartus® Prime Software Guidelines
4. Device Guidelines
5. Document Revision History for AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite 21.1
This document provides design guidelines specific to Intel® Stratix® 10 I/O Limited (IOL) FPGAs designated by ordering part numbers (OPN) ending with -NL. I/O Limited FPGAs limit transceiver utilization such that the one-way aggregate bandwidth is ≤499 Gbps and GPIO utilization to ≤700 I/O pins.

Customers may find these devices useful where export restrictions constrain the usage of FPGAs with transceiver and I/O utilization above those limits. Unless otherwise specified, Intel® Stratix® 10 I/O Limited FPGAs behave identically to standard Intel® Stratix® 10 FPGAs.

This document is based on Intel® Quartus® Prime software version 21.1.

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