JESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide
JESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide
Intel provides a design example of the JESD204B Intel® FPGA IP targeting Intel® Cyclone® 10 GX devices. Generate the JESD204B design example through the IP catalog in the Intel® Quartus® Prime Pro Edition software.
JESD204B Intel Cyclone 10 GX FPGA IP Design Example Quick Start Guide
The JESD204B IP core provides the capability of generating design examples for selected configurations.
Directory Structure
Directory/File | Description |
---|---|
ed_sim | The folder that contains simulation testbench files |
ed_sim/testbench/models | The folder that contains the testbench and source files |
ed_sim/testbench/setup_scripts | The folder that contains the test flow setup scripts |
ed_sim/testbench/pattern | The folder that contains the source files for the pattern generator/checker |
ed_sim/testbench/transport_layer | The folder that contains the source files for the transport layer |
ed_sim/testbench/aldec | The folder that contains the test flow run scripts for Riviera-PRO™ simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/cadence | The folder that contains the test flow run scripts for NCSim simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/xcelium | The folder that contains the test flow run scripts for Xcelium® Parallel simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/mentor | The folder that contains the test flow run scripts for ModelSim® simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/synopsys/vcs | The folder that contains the test flow run scripts for VCS® simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/synopsys/vcsmx | The folder that contains the test flow run scripts for VCS® MX simulator. Also serves as the working directory for the simulator. |
ed_synth | The folder that contains design example synthesizable components |
ed_synth/ip | The folder that contains Platform Designer-instantiated IP modules |
ed_synth/altjesd_ed_qsys_<data path> | The folder that contains Platform Designer-generated modules from the jesd204_ed_qsys_<data path>.qsys system |
ed_synth/altjesd_ss_<data path> | The folder that contains Platform Designer-generated modules from the altjesd_ss_<data path>.qsys system |
ed_synth/pattern | The folder that contains the source files for the pattern generator/checker |
ed_synth/transport_layer | The folder that contains the source files for the transport layer |
altera_jesd204b_ed_<data path>.qpf altera_jesd204b_ed_<data path>.qsf |
Intel® Quartus® Prime project and settings files |
altjesd_ed_qsys_<data path>.qsys | Platform Designer top level system |
altjesd_ss_<data path>.qsys | Platform Designer subsystem |
altera_jesd204b_ed_<data path>.sv | Top level HDL source file |
altera_jesd204_ed_<data path>.sdc | Top level design constraints file |
ed_synth/system_console | The folder that contains all files necessary to run scripts in System Console (See Design Example Files for more details on folder content.) |
*.v | Miscellaneous source files |
ip_sim | The folder that contains the simulation script to generate the JESD204B IP core Verilog/VHDL simulation model. |
Generating the Design
To generate the design example from the IP parameter editor:
- Create a project targeting device family and select the desired device.
- In the IP Catalog, locate and double-click Interface Protocols > JESD > JESD204B Intel® FPGA IP . The IP parameter editor appears.
- Specify a top-level name and the folder for your custom IP variation.. Click OK.
-
Select a design from the Presets
library
by double-clicking the desired preset. When you select a
design, the system automatically populates the IP parameters for the
design.
Note: If you select another design, the settings of the IP parameters change accordingly.
-
You can customize the preset parameter values according to
your specifications. Under the IP tab,
specify the JESD204B IP core parameters for your
design.
Note: The JESD204B IP core supports a limited range of parameter combinations. Refer to the Supported Configurations section for more details. If you specify an unsupported combination of parameters, the Available Example Designs automatically selects None as the default.
-
Under the Example
Design tab, specify the design example parameters as described
in Design Example Parameters.
Note: To generate the design example for hardware testing on selected Intel development kits, select the appropriate target development kit from the Target Development Kit drop down box.
- Click Generate Example Design.
Design Example Parameters
Parameter | Options | Description |
---|---|---|
Available Example Designs | None (Default) | No design examples selected. |
System Console Control | Design example with System Console control. | |
Example Design Files | Simulation | Generate simulation fileset. |
Synthesis | Generate synthesis fileset. | |
Generated HDL Format for Simulation | Verilog (Default) | Verilog HDL format for entire simulation fileset. |
VHDL | VHDL Platform Designer generated top-level wrapper file set. | |
Generated HDL Format for Synthesis | Verilog (Default) | Verilog HDL format for synthesis fileset. |
Example Design Customizations | Generate 3-wire SPI module | Check to enable 3-wire SPI interface instead of 4-wire SPI interface. |
Target Development Kit | None (Default) | No target development kit selected. |
Cyclone GX FPGA Development Kit | Design example targets Intel® Cyclone® 10 GX FPGA Development Kit |
Simulating the Design
To simulate the design, perform the following steps:
- Change the working directory to <example_design_directory> /ed_sim/testbench/<Simulator>.
-
In the command line, run the simulation script. The table below
shows the commands to run the supported simulators.
Simulator Command Riviera-PRO™ do run_tb_top.tcl NCSim sh run_tb_top.sh ModelSim® do run_tb_top.tcl VCS® / VCS® MX sh run_tb_top.sh Xcelium® Parallel sh run_tb_top.sh The simulation ends with messages that indicate whether the run was successful or not. Refer to Simulation Message and Description table in Testbench for more information on messages reported by the simulation flow.
Compiling and Testing the Design
Perform the following steps to compile the design and program the development board:
-
Launch the
Intel®
Quartus® Prime software
and compile the design (Processing > Start Compilation).
The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
- Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
-
Launch the Clock
Control application that is included with the development board,
and set the clock settings according to the selected data rate.
Note: Refer to the Intel® Cyclone® 10 GX FPGA Development Kit documentation for more information on using the Clock Control application.
Table 3. Clock Setting Clock Name Clock Frequency device_clk Select the frequencies in the PLL/CDR Reference Clock Frequency drop down menu of the IP parameter editor.1 mgmt_clk 100 MHz Figure 4. Clock Control GUI SettingThis example shows the clock control GUI setting for 6.144 Gbps data rate. - If you are performing external FMC loopback test, affix the FMC loopback card to the FMC port connector.
- Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.
Board Connectivity
Refer to the instructions in Generating the Design.
Port Name | Port Description | Board Component | Component Description |
---|---|---|---|
global_rst_n | Global reset | S8 | User PB0 push-button |
device_clk | Reference clock input | U64 | Si5332 clock generator (OUT1) |
mgmt_clk | Control clock | U64 | Si5332 clock generator (OUT6) |
tx_serial_data | TX serial data | J7 | FMC connector |
rx_serial_data | RX serial data | J7 | FMC connector |
Hardware Test for System Console Control Design Example
- Launch the System Console tool from Intel® Quartus® Prime (Tools > System Debugging Tools > System Console).
- In the TCL Console command prompt, type get_service_paths master to print a list of devices connected to your JTAG chain.
-
Open the main.tcl Tcl script located in
the System Console directory in any text
editor of your choice and locate the following line.
set master_index [expr {$master_list_length - <your offset>}]
- Adjust the master_index offset as necessary to reflect your JTAG chain configuration such that the master_index always points to the Intel® Cyclone® 10 GX device and save the file.
-
In the TCL Console
command prompt, navigate to the system_console directory (cd
system_console) and execute the main.tcl script (source
main.tcl). Your TCL
Console window should resemble the following figure.
Figure 5. Source main.tcl
-
Type start_basic_test
at the command prompt to execute the link setup and test procedure.
This procedure executes a set of instructions to set up the pattern generator and checker to transmit and check PRBS pattern, configure the JESD204B IP PHY internal serial loopback mode and report link status.The following figure illustrates the expected result from a successful link setup and test.Figure 6. Successful Test in the System Console
-
In the event that the test fails due to a lane deskew error,
use the rbd_offset procedure (described
in the following table) to offset the default RBD setting. Refer to the
JESD204B
Intel® FPGA IP User Guide for
more details on using the RBD offset.
Table 5. Procedures in the main.tcl System Console Script . The table describes useful procedures in the main.tcl that may be helpful in debugging. Procedure Values Description get_service_paths {master} Reports all devices that are connected to the JTAG chain. Use this information to set the master index to point to the Intel® Cyclone® 10 GX device get_master_index N/A Set the targeted device master index. Use get_service_paths master to determine the offset of the Intel® Cyclone® 10 GX device in the JTAG chain, and edit the offset in this procedure accordingly. start_basic_test N/A Main procedure that sets up link serial loopback mode, pattern generator and checker test mode, pulses sysref and reports link status reset N/A Global reset force_link_frame_reset {0,1} 0: Deassert link and frame resets
1: Assert and hold link and frame resets
Note: Link and frame clock domains should be held in reset while writing to JESD204B IP CSRsloopback {0,1} 0: Disable internal serial loopback
1: Enable internal serial loopback
set_testmode {alt, ramp, prbs} alt: Set pattern generator and checker to alternate pattern
ramp: Set pattern generator and checker to ramp pattern
prbs: Set pattern generator and checker to PRBS pattern
rbd_offset {integer} Adjust RBD offset value to eliminate RX lane deskew error. sysref N/A Single pulse sysref read_status_pio N/A Read status PIO registers. PIO status configuration:
Bit 0 — Core PLL locked
Bit 1 — TX transceiver ready
Bit 2 — RX transceiver ready
Bit 3 — Pattern checker mismatch error
Bit 4 — TX link error (use read_err_status procedure to report error description)
Bit 5 — RX link error (use read_err_status procedure to report error description)
read_err_status N/A Read JESD204B IP error status registers. Refer to the JESD204B IP register maps for detailed description of status registers. clear_err_status N/A Clear JESD204B IP error status registers read_rx_status0 N/A Read JESD204B IP rx_status0 register. Refer to the JESD204B IP register maps for detailed description of status registers read_tx_status0 N/A Read JESD204B IP tx_status0 register. Refer to the JESD204B IP register maps for detailed description of status registers. read_rx_syncn_sysref_ctrl N/A Read JESD204B IP syncn_sysref_ctrl register. Refer to the JESD204B IP register maps for detailed description of status registers wait_seconds {integer} Wait for {integer} seconds wait_minutes {integer} Wait for {integer} minutes
Design Example Detailed Description
Features
This design example has the following key features:
- System Console using Tcl script control mechanism
- Synthesis and simulation flows
- Configurable transport layer and pattern generator and checker modules
- Power-on self test with the following configurable test patterns:
- Alternating
- Ramp
- PRBS
- Supports simplex (RX only, TX only) and duplex (both RX and TX) data path modes
- Supports option for 3-wire SPI
Hardware and Software Requirements
Intel uses the following hardware and software to test the example designs:
- Intel® Quartus® Prime Pro Edition software
- Intel® Cyclone® 10 GX FPGA Development Kit
Supported Configurations
JESD204B IP Parameters | Values |
---|---|
Wrapper Options | Both Base and Phy |
Data Path |
|
JESD204B Subclass | 1 |
Data Rate |
Any valid value2 |
PCS Option |
|
Bonding Mode |
|
PLL/CDR Reference Clock Frequency | Any valid value |
Enable Bit Reversal and Byte Reversal | Any valid value |
Enable Transceiver Dynamic Reconfiguration |
Any valid value |
L |
|
M |
|
Enable manual F configuration |
|
F |
|
N | Integer, range 12 – 16 |
N’ |
|
S | Any valid value |
K | Any valid value |
Enable Scramble (SCR) | Any valid value |
CS | Integer, range 0 – 3 |
CF | 0 |
High Density User Data Format (HD) |
|
Enable Error Code Correction (ECC_EN) | Any valid value |
Presets
Standard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs. Select the presets at the lower right window in the parameter editor shown in Figure 3.
The presets are applicable for JESD204B IP configurations that generate design examples. You can select one of the presets available for your target device to quickly generate a design example without having to set each parameter in the IP tab and verify that the specified parameters match the supported configurations. You can manually change any of the IP and example design parameters in the Platform Designer user interface after selecting a preset. However, you must ensure that your parameter selection falls within the supported configuration ranges detailed in Supported Configurations for design example to generate successfully.
JESD204B IP Parameters | Preset 1 JESD204B Example Design (LMF = 222, 6.144 Gbps) |
Preset 2 JESD204B Example Design (LMF = 888, 6.144 Gbps) |
---|---|---|
Wrapper Options | Both Base and Phy | Both Base and Phy |
Data Path | Duplex | Duplex |
JESD204B Subclass | 1 | 1 |
Data Rate | 6144 Mbps | 6144 Mbps |
PCS Option | Enabled Hard PCS | Enabled Hard PCS |
Bonding Mode | Non-bonded | Non-bonded |
PLL/CDR Reference Clock Frequency | 153.6 MHz | 153.6 MHz |
Enable Bit Reversal and Byte Reversal | No | No |
Enable Transceiver Dynamic Reconfiguration | No | No |
L | 2 | 8 |
M | 2 | 8 |
Enable manual F configuration | No | Yes |
F | 2 | 8 |
N | 16 | 12 |
N’ | 16 | 12 |
S | 1 | 5 |
K | 16 | 32 |
Enable Scramble (SCR) | No | No |
CS | 0 | 0 |
CF | 0 | 0 |
High Density User Data Format (HD) | 0 | 0 |
Enable Error Code Correction (ECC_EN) | No | No |
Design Components
The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.
-
Platform Designer system
- JESD204B subsystem
- JTAG to Avalon master bridge
- Parallel I/O (PIO)
- ATX PLL
- Core PLL
- PLL reconfiguration module (For transceiver dynamic reconfiguration enabled mode only)
- Serial Port Interface (SPI)—master module
- Test pattern generator (For duplex and simplex TX data path only)
- Test pattern checker (For duplex and simplex RX data path only)
- Assembler—TX transport layer (For duplex and simplex TX data path only)
- Deassembler—RX transport layer (For duplex and simplex RX data path only)
Platform Designer System Component
The Platform Designer system instantiates the JESD204B IP core data path and supporting peripherals.
The top level Platform Designer system instantiates the following modules:
-
Platform Designer system
- JESD204B subsystem
- JTAG to Avalon master bridge
- Parallel I/O (PIO)
- ATX PLL
- Core PLL
- Serial Port Interface (SPI)—master module
The following are the key features of the top level Platform Designer system:
- Supports System Console control design example
- Supports 3 data path types:
- Duplex—Both TX and RX data paths present
- Simplex TX—Only TX data path present
- Simplex RX—Only RX data path present
- Supports transceiver dynamic reconfiguration enabled
mode:
- When enabled, connects the JTAG to Avalon master bridge module to the following interfaces:
- Transceiver PHY reconfiguration interface
- ATX PLL reconfiguration interface
- Core PLL reconfiguration controller
- When disabled, reconfiguration interfaces not present in design example
- When enabled, connects the JTAG to Avalon master bridge module to the following interfaces:
- The JESD204B subsystem, PLL reconfiguration controller, ATX PLL dynamic reconfiguration interface, parallel I/O and SPI master modules are connected to the JTAG to Avalon master bridge (System Console control) via the Avalon Memory-Mapped (Avalon-MM) interface.
- JTAG to Avalon master bridge provides a link to the user via System Console. You can control the behavior of the design example via Tcl scripts executed in the System Console interface.
- TX data path flow:
- Input: 32-bit per transceiver lane Avalon Streaming (Avalon-ST) input from assembler (TX transport layer)
- Output: TX serial data
- RX data path flow:
- Input: RX serial data from either external converter source or internal serial loopback
- Output: 32-bit per transceiver lane Avalon Streaming (Avalon-ST) output to deassembler (RX transport layer)
- SPI master module links out to the SPI configuration interface of external converters via a 3- or 4-wire SPI interconnect (depending on Generate 3-Wire SPI Module setting).
- SPI master module handles the serial transfer of configuration data to the SPI interface on the converter end
- The ATX PLL generates the serial clock for clocking the TX serial
data
- ATX PLL module generated for duplex and simplex TX data path only
- ATX PLL reconfiguration interface only present when transceiver dynamic reconfiguration option is enabled.
- When present, ATX PLL reconfiguration interface connects to the JTAG to Avalon master bridge (System Console control) module via the Avalon Memory-Mapped (Avalon-MM) interface.
- The core PLL generates the following clocks for the system:
- Link clock
- Frame clock

JESD204B Subsystem in Platform Designer
The JESD204B subsystem instantiates the following modules:
- JESD204B Intel® FPGA IP core
- Reset sequencer
- Transceiver PHY reset controller
- Avalon-MM bridge
JESD204B IP Core
The generated design example is a self-contained system with its own JESD204B IP core instantiation that is separate from the IP core that is generated from the IP tab. The JESD204B IP base core and PHY layer connect to System Console through the Avalon-MM interconnect. The JESD204B IP core uses three separate Avalon-MM ports:
- Base core TX data path—For dynamic reconfiguration of the TX CSR parameters
- Base core RX data path—For dynamic reconfiguration of the RX CSR parameters
- PHY layer—For dynamic reconfiguration of transceiver PHY CSR
You can dynamically change the configuration of the JESD204B IP core base and PHY layers through TCL scripts using the System Console.
The structure of the design example varies depending on the values of these JESD204B IP core parameters:
- Data path:
- Duplex—Both TX and RX data paths and CSR interfaces present
- TX only—Only TX data path and CSR interface present
- RX only—Only RX data path and CSR interface present
- Transceiver dynamic
reconfiguration mode:
- When enabled, transceiver PHY reconfiguration interface is present in the design example and connected the JTAG to Avalon master bridge (System Console control) module.
- When disabled, transceiver PHY reconfiguration interface not present in design example.
Reset Sequencer
The reset sequencer is a standard Platform Designer component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:
- Core PLL reset—resets the core PLL
- Transceiver reset—resets the JESD204B IP core PHY module
- TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs
- TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer
- TX/RX frame reset—resets the TX/RX transport layer, upstream and downstream modules
The reset sequencer has hard and soft reset options. The hard reset port connects to the global reset input pin in the top level design. The soft reset is activated via Avalon-MM interface by TCL scripts (System Console control). When you assert a hard or soft reset, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.
Transceiver PHY Reset Controller
The transceiver PHY reset controller is a standard Platform Designer component in the IP Catalog standard library. This module takes the transceiver PHY reset output from the reset sequencer and generates the proper analog and digital reset sequencing for the transceiver PHY module.
Avalon-MM Bridge
All the Avalon-MM submodules in the JESD204B subsystem are connected via Avalon-MM interconnect to a single Avalon-MM bridge. This bridge is the single interface for Avalon-MM communications into and out of the subsystem.
JESD204B Subsystem Address Map
Access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window.

JTAG to Avalon Master Bridge
The JTAG to Avalon master bridge is a standard Platform Designer component in the IP Catalog standard library. This module provides a connection between a host system and the Platform Designer system via the respective physical interfaces; JTAG on the host system end and Avalon-MM on the Platform Designer system end. Host systems can initiate Avalon Memory-Mapped (Avalon-MM) transactions by sending encoded streams of bytes via JTAG interface. The module supports reads and writes, but not burst transactions.
Parallel I/O
Parallel I/O (PIO) modules provide general input/output (I/O) access from the Avalon master (JTAG to Avalon master bridge). There are two sets of 32-bit PIO registers:
- Status registers—input from the HDL components to the Avalon master
- Control registers—output from the Avalon master to the HDL components
The registers are assigned in the top level HDL file (io_status for status registers, io_control for control registers). The tables below describe the signal connectivity for the status and control registers.
Bit | Signal |
---|---|
0 | Core PLL locked |
1 | TX transceiver ready (for duplex and simplex TX data path only) |
2 | RX transceiver ready (for duplex and simplex RX data path only) |
3 | Test pattern checker data error (for duplex and simplex RX data path only) |
4 | TX link error (for duplex and simplex TX data path only) |
5 | RX link error (for duplex and simplex RX data path only) |
Bit | Signal |
---|---|
0 | RX serial loopback enable (for duplex data path only) |
30 | Global reset |
31 | Sysref |
ATX PLL
The ATX PLL is a standard Platform Designer component in the IP Catalog standard library. This module supplies a low-jitter serial clock to the transceiver PHY module. The reference clock input to the ATX PLL comes from an external source. If the transceiver dynamic reconfiguration option is selected during design example generation, the ATX PLL has an Avalon-MM interface that connects to the Avalon master (JTAG to Avalon master bridge for System Console control via the Avalon-MM interconnect and can receive configuration instructions from the Avalon master.
For simplex TX variant, the frequency selection in the PLL/CDR Reference Clock Frequency drop-down list in the JESD204B IP parameter editor is disabled. The design example generates the ATX PLL with the reference clock frequency of either:
- Hard PCS: data_rate/20
- Soft PCS: data_rate/40
Refer to Changing the Data Rate or Reference Clock Frequency for more information about modifying the ATX PLL reference clock frequency to suit your application.
For duplex variant, the ATX PLL reference clock frequency shares the frequency with the CDR reference clock. You must select the frequency from the PLL/CDR Reference Clock Frequency drop-down list in the IP parameter editor.
For the ATX PLL reference clock frequencies supported range, refer to the Intel® Cyclone® 10 GX Device Datasheet.
Core PLL
The core PLL uses an external clock input as its reference clock to generate two derivative clocks from a single VCO:
- Link clock
- Frame clock
Clock | Formula | Description |
---|---|---|
Link Clock | Serial data rate/40 | The link clock clocks the JESD204B IP core link layer and the link interface of the transport layer. |
Frame Clock | Serial data rate/(10 × F) | The frame clock clocks the transport layer, test pattern generators and checkers, and any downstream modules in the FPGA core fabric. |
For the frame clock, when the F parameter is 1 or 2, the resulting frame clock frequency can easily exceed the capability of the core PLL to generate and close timing. The top level RTL file, (altera_jesd204_ed_<data path>.sv), defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly.
For this design example, F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. As an example, the actual frame clock for a serial data rate of 10 Gbps and F = 1 is:
(10000/(10 × 1)) / F1_FRAMECLK_DIV = 1000 / 4 = 250 MHz
Frame Clock and Link Clock Relationship
The frame clock and link clock are synchronous. For the derived F mode, the ratio of link_clk period to frame_clk period is given by this formula:
link_clk period to frame_clk period ratio = 32xL/(MxSxN')
F Parameter | fTXframe(txframe_clk frequency) | fRXframe(rxframe_clk frequency) |
---|---|---|
1 | fTXlinkx(4/F1_FRAMECLK_DIV) | fRXlinkx(4/F1_FRAMECLK_DIV) |
2 | fTXlinkx(2/F2_FRAMECLK_DIV) | fRXlinkx(2/F2_FRAMECLK_DIV) |
4 | fTXlink | fRXlink |
8 | fTXlink/2 | fRXlink/2 |
SPI Master
The SPI master module is a standard Platform Designer component in the IP Catalog standard library. This module uses the SPI protocol to facilitate the configuration of external converters (for example, ADC, DAC, external clock modules) via a structured register space inside the converter device. The SPI master has an Avalon-MM interface that connects to the Avalon master (JTAG to Avalon master bridge) via the Avalon-MM interconnect and can receive configuration instructions from the Avalon master.
This module is configured to a 4-wire, 24-bit width interface. If the Generate 3-Wire SPI Module option is selected, an additional module is instantiated to convert the 4-wire output of the SPI master to 3-wire.
For more details on the SPI master module, refer to the JESD204B Intel® FPGA IP User Guide.
Transport Layer
The transport layer in the design example consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is instantiated in the top level RTL file, not in the Platform Designer project.
The transport layer provides the following services to the application layer (AL) and the data link layer (DLL):
- Assembler at the TX path:
- Maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
- Reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during TX data streaming.
- Deassembler at the RX path:
- Maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon-ST interface).
- Reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during RX data streaming.
The transport layer has many customization options and you can modify the transport layer RTL to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core.
For more details on the implementation of the transport layer in RTL and customization options, refer to the JESD204B Intel® FPGA IP User Guide.
Test Pattern Generator
The test pattern generator generates either a parallel PRBS, alternate checkerboard, or ramp wave, and sends it to the transport layer during test mode. The test pattern generator is implemented in the top level RTL file, not in the Platform Designer project.
You can modify the test pattern generator RTL match your specifications. Furthermore, for parameters like M, S, N, and test mode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core, affects the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR.
Test Pattern Checker
The test pattern checker checks either a parallel PRBS, alternate checkerboard, or ramp wave from the transport layer during test mode and outputs an error flag if there are any data mismatches. The test pattern checker is implemented in the top level RTL file, not in the Platform Designer project.
You can modify the test pattern checker RTL to match your specifications. Furthermore, for parameters like M, S, N, and test mode, the test pattern checker shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core, affects the test pattern checker in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR.
Clocking Scheme
The main reference clock for the design example is device_clk. This clock must be supplied from an external source. The device_clk is the reference clock for the core PLL, ATX PLL and the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from device_clk. The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon-MM interfaces of Platform Designer components.
Clock | Description | Source | Modules Clocked |
---|---|---|---|
device_clk | Reference clock for the core PLL, ATX PLL and RX transceiver PHY | External | Core PLL, ATX PLL, RX transceiver PHY |
link_clk | Link layer clock | device_clk | JESD204B IP core link layer, transport layer link interface |
frame_clk | Frame layer clock | device_clk | Transport layer, test pattern generator and checker, downstream modules |
mgmt_clk | Control plane clock | External | Avalon-MM interfaces |
Simulation
Execute the simulation by running the relevant simulation run scripts in the supported simulator environment. The following table shows the simulators supported along with the relevant run scripts.
Simulators | Simulation Directory | Run Script |
---|---|---|
Riviera-PRO™ | /testbench/aldec/ | run_tb_top.tcl |
NCSim | /testbench/cadence/ | run_tb_top.sh |
ModelSim® | /testbench/mentor/ | run_tb_top.tcl |
VCS® | /testbench/synopsys/vcs/ | run_tb_top.sh |
VCS® MX | /testbench/synopsys/vcsmx/ | run_tb_top.sh |
Xcelium® Parallel | /testbench/xcelium/ | run_tb_top.sh |
The design generates the simulation results which include the transcript or log files in the relevant simulation directory.
Testbench
The simulation design-under-test (DUT) is the generated design example which includes a synthesizable pattern generator and checker. The figures below show the testbench block diagram for simplex and duplex options.
The simulation flow replaces the JTAG to Avalon master bridge module in the Platform Designer system of the System Console Control design example with the Avalon-MM master bus functional model (BFM). This BFM enables a testbench to send Avalon-MM read/write commands to the design example registers to mimic the functionality of System Console.
The testbench provided in the simulation flow (/testbench/models/tb_top.sv) executes the following steps:
- Reset DUT.
- Initialize BFM.
- Execute Avalon-MM commands to initialize the DUT in the following mode:
- Internal serial loopback mode (for duplex option only)
- Pattern generator/checker set to PRBS pattern
- Wait for DUT to initialize to user mode.
- Report JESD204B link status.
When simulation ends, the following messages are shown at end.
Message | Description |
---|---|
Pattern Checker(s): Data error(s) found! | Pattern mismatch errors found on the pattern checker |
Pattern Checker(s): OK! | No errors found on the pattern checker |
Pattern Checker(s): No valid data found! | No valid data received by pattern checker |
JESD204B Tx Core(s): Tx link error(s) found! | Link errors reported by JESD204B IP TX |
JESD204B Tx Core(s): OK! | No link errors reported by JESD204B IP TX |
JESD204B Rx Core(s): Rx link error(s) found! | Link errors reported by JESD204B IP RX |
JESD204B Rx Core(s): OK! | No link errors reported by JESD204B IP RX |
TESTBENCH_PASSED: SIM PASSED! | Overall simulation passed |
TESTBENCH_FAILED: SIM FAILED! | Overall simulation failed |
Design Example Files
There are two flows for the design example: simulation and synthesis.
Design Example Flow | Directory |
---|---|
Simulation | <your project>/ed_sim |
Synthesis | <your project>/ed_synth |
The following tables list the important folders and files for simulation and synthesis.
File Type | File/Folder | Description |
---|---|---|
Run script files | /testbench/aldec/run_tb_top.tcl | TCL run script for Riviera-PRO™ simulator |
/testbench/cadence/run_tb_top.sh | Shell run script for NCSim simulator | |
/testbench/mentor/run_tb_top.tcl | TCL run script for ModelSim® simulator | |
/testbench/synopsys/vcs/run_tb_top.sh | Shell run script for VCS® simulator | |
/testbench/synopsys/vcsmx/run_tb_top.sh | Shell run script for VCS® MX simulator | |
/testbench/xcelium/run_tb_top.sh | Shell run script for Xcelium® simulator | |
Source files | /testbench/models/altjesd_ed_qsys_<data path>.qsys | Top level Platform Designer system project |
/testbench/models/altjesd_ss_<data path>.qsys | JESD204B subsystem Platform Designer system project | |
/testbench/models/ip/ | IP folder containing instantiated IP modules | |
/testbench/models/altera_jesd204_ed_<data path>.sv | Top level HDL | |
/testbench/models/tb_top.sv | Top level testbench | |
/testbench/spi_mosi_oe.v | Output buffer HDL | |
/testbench/switch_debouncer.v | Switch debouncer HDL | |
/testbench/pattern/ | Folder containing the test pattern generator and checker HDL | |
/testbench/transport_layer | Folder containing assembler and de-assembler HDL. |
File Type | File/Folder | Description |
---|---|---|
Intel® Quartus® Prime project files | altera_jesd204_ed_<data path>.qpf | Intel® Quartus® Prime project file |
altera_jesd204_ed_<data path>.qsf | Intel® Quartus® Prime settings file | |
Source files | altera_jesd204_ed_<data path>.sv | Top level HDL |
altera_jesd204_ed_<data path>.sdc | Synopsys® Design Constraints (SDC) file containing all timing/placement constraints | |
transport_layer/ | Folder containing assembler and de-assembler HDL | |
pattern/ | Folder containing the test pattern generator and checker HDL | |
spi_mosi_oe.v | Output buffer HDL | |
switch_debouncer.v | Switch debouncer HDL | |
altjesd_ed_qsys_<data path>.qsys | Top level Platform Designer system project | |
altjesd_ss_<data path>.qsys | JESD204B subsystem Platform Designer system project |
Registers
Refer to the JESD204B RX Address Map and Register Definitions and JESD204B TX Address Map and Register Definitions for the list of registers.
Signals
Signal | Clock Domain | Direction | Description |
---|---|---|---|
Clocks and Resets | |||
mgmt_clk | — | Input |
Reference clock for all peripherals connected via Avalon-MM interconnect. |
global_rst_n | mgmt_clk | Input |
Global reset signal from the push button. This reset is an active low signal and the deassertion of this signal is synchronous to the rising-edge of mgmt_clk. |
Signal |
Clock Domain |
Direction |
Description |
Serial Data | |||
rx_serial_data[LINK*L-1:0] | device_clk | Input |
Differential high speed serial input data. The clock is recovered from the serial data stream. |
tx_serial_data[LINK*L-1:0] | device_clk | Output |
Differential high speed serial output data. The clock is embedded in the serial data stream. |
Signal |
Clock Domain |
Direction |
Description |
JESD204B | |||
sysref_out | mgmt_clk | Output |
SYSREF signal for JESD204B Subclass 1 implementation. |
sync_n_out | link_clk | Output |
Indicates a SYNC_N from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting. |
tx_link_error | link_clk | Output | Error interrupt from JESD204B IP core indicating TX link error |
rx_link_error | link_clk | Output | Error interrupt from JESD204B IP core indicating RX link error |
Signal |
Clock Domain |
Direction |
Description |
Avalon- ST User Data | |||
avst_usr_din[LINK*TL_DATA_BUS_WIDTH-1:0] | frame_clk | Input | TX data from the Avalon-ST source interface. The
TL_DATA_BUS_WIDTH is determined by the following formulas:
|
avst_usr_din_valid[LINK-1:0] | frame_clk | Input |
Indicates whether the data from the Avalon-ST source interface to the transport layer is valid or invalid.
|
avst_usr_din_ready[LINK-1:0] | frame_clk | Output |
Indicates that the transport layer is ready to accept data from the Avalon-ST source interface.
|
avst_usr_dout[LINK*TL_DATA_BUS_WIDTH-1:0] | frame_clk | Output | RX data to the Avalon-ST sink interface. The
TL_DATA_BUS_WIDTH is determined by the following formulas:
|
avst_usr_dout_valid[LINK-1:0] | frame_clk | Output |
Indicates whether the data from the transport layer to the Avalon-ST sink interface is valid or invalid.
|
avst_usr_dout_ready[LINK-1:0] | frame_clk | Input |
Indicates that the Avalon-ST sink interface is ready to accept data from the transport layer.
|
avst_patchk_data_error [LINK-1:0] | frame_clk | Output |
Output signal from pattern checker indicating a pattern check error. |
Signal |
Clock Domain |
Direction |
Description |
SPI | |||
spi_MISO 5 | spi_SCLK | Input |
Input data from external slave to the master. |
spi_MOSI 5 | spi_SCLK | Output |
Output data from the master to the external slaves. |
spi_SDIO 6 | spi_SCLK | Input/Output | Output data from the master to external slave. Input data from external slave to master |
spi_SCLK | mgmt_clk | Output |
Clock driven by the master to slaves, to synchronize the data bits. |
spi_SS_n[2:0] | spi_SCLK | Output |
Active low select signal driven by the master to individual slaves, to select the target slave. Defaults to 3 bits. |
Customizing the Design Example
Modifying the JESD204B IP Core Parameters
Perform the following instructions to modify the JESD204B IP core parameters post-generation:
- Open the generated design example project in the Intel® Quartus® Prime software.
- Open the altjesd_ss_<data path>.qsys system in Platform Designer.
- In the System Contents tab, double-click the altjesd_<data path> module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core.
-
Modify the parameters of the JESD204B IP core module as per your system specifications. When
you are done, save the Platform Designer system
(File > Save).
Note: The JESD204B IP core and transport layer imposes certain limits on the values that can be entered as parameters. Refer to the JESD204B Intel® FPGA IP User Guide for a complete listing of the legal parameter values.
- Click the Generate HDL to generate the HDL files needed for Intel® Quartus® Prime compilation.
- After the HDL generation is completed, click the Finish to save your settings and exit Platform Designer.
- You have to manually change the system parameters in the top level RTL file to match the parameters that you set in the Platform Designer project, if applicable. Open the top level RTL file (altera_jesd204_ed_<data path>.sv) in any text editor of your choice.
- Modify the system parameters at the top of the file to match the new JESD204B IP core settings in the Platform Designer project, if applicable.
- Save the file and compile the design in Intel® Quartus® Prime software as per the instructions in the Compiling and Testing the Design.
Changing the Data Rate or Reference Clock Frequency
When changing the data rate or reference clock frequency, you must consider the following:
- The relationships between the serial data rate, link clock, and frame clock as described in the JESD204B Intel® FPGA IP User Guide.
- Change the PLL output clock settings according to Table 11.
- Take note when changing the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factor parameters in the top level RTL file altera_jesd204_ed_<data path>.sv for cases when F=1 or F=2. These parameters further divide-down the frame clock frequency requirement so the resulting clock frequency is within bounds of timing closure for the FPGA core fabric.
The frame clock and the link clock for the following cases share the same frequency:
- F=1—the default parameter value for F1_FRAMECLK_DIV=4
- F=2—the default parameter value for F2_FRAMECLK_DIV=2
- F=4
Perform the following instructions to modify the JESD204B IP core parameters post-generation:
- Open the generated design example project in the Intel® Quartus® Prime software.
- Open the top level altjesd_ed_qsys_<data path>.qsys in the Platform Designer.
- In the System Contents tab, right-click the altjesd_ss_<data path> module and select Drill into Subsystem. This opens the altjesd_ss_<data path>.qsys Platform Designer subsystem.
- Double-click the altjesd_<data path> module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core.
- Change the Data rate and PLL/CDR Reference Clock Frequency values to meet your system requirements.
- Modify the clock frequency values of the device_clk, link_clk, frame_clk and mgmt_clk clock source modules as necessary to meet your system requirements. Double-click the clock source module to bring up the parameters editor and change the Clock frequency value as necessary. Ensure that the values match the clock frequency values that you have entered for the other modules above.
- Navigate back to the top level altjesd_ed_qsys_<data path>.qsys hierarchy.
-
Double-click the xcvr_atx_pll_0 module to bring up the parameters editor for the
ATX PLL module.
This is the module that generates the serial clock for the TX transceiver PHY.
-
Under the PLL subtab,
locate the Output Frequency group and
change the PLL output frequency and
PLL integer reference clock frequency
values to meet your system requirements.
The PLL output frequency is half of the PLL output data rate. Ensure that the data rate and PLL reference clock values match the parameters that you entered into the JESD204B IP core module.
-
Double-click the core_pll module to bring up the parameters editor for the core
PLL module.
This is the module that generates the link_clk and frame_clk clocks that clock the core components.
-
Under the PLL subtab,
change the Reference Clock Frequency
value in the General group to meet your
system requirements.
Ensure that the reference clock frequency value matches the ones set for the JESD204B IP core and ATX PLL modules.
-
Change the
outclk0
group settings (which correspond to the
link_clk)
and
outclk1
group settings (which correspond to the
frame_clk)
where necessary.
Ensure that the link_clk and frame_clk values satisfy the frequency requirements as described in the JESD204B IP Core User Guide.
- Modify the clock frequency values of the device_clk, , link_clk, frame_clk and mgmt_clk clock source modules as necessary to meet your system requirements. Double-click the clock source module to bring up the parameters editor and change the Clock frequency value as necessary. Ensure that the values match the clock frequency values that you have entered for the other modules in earlier steps.
- Click the Generate HDL button to generate the HDL files needed for Intel® Quartus® Prime compilation.
- After the HDL generation is completed, click the Finish to save your Platform Designer settings and exit the Platform Designer window.
- If the frame_clk settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or F2_FRAMECLK_DIV values are changed, change the parameters in the top level design file, altera_jesd204_ed_<data path>.sv.
-
Modify the clock constraints in the SDC constraints file
(altera_jesd204_ed_<data
path>.sdc) to reflect your new clock frequency
values, if applicable. The following constraints should be modified:
create_clock -name device_clk -period <clock period value in ns> [get_ports device_clk] create_clock -name mgmt_clk -period <clock period value in ns> [get_nodes mgmt_clk]
- Save the file and compile the design in Intel® Quartus® Prime software as per the instructions in the Compiling and Testing the Design.
Document Revision History for the JESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.05.07 | 18.0 | Initial release. |