Intel provides a design example of the JESD204B Intel^® FPGA IP targeting Intel^® Cyclone^® 10 GX devices. Generate the JESD204B design example through the IP catalog in the Intel^® Quartus^® Prime Pro Edition software.

The JESD204B IP core provides the capability of generating design examples for selected configurations.

This design example has the following key features:

• System Console using Tcl script control mechanism
• Synthesis and simulation flows
• Configurable transport layer and pattern generator and checker modules
• Power-on self test with the following configurable test patterns:
  • Alternating
  • Ramp
  • PRBS
• Supports simplex (RX only, TX only) and duplex (both RX and TX) data path modes
• Supports option for 3-wire SPI

Intel uses the following hardware and software to test the example designs:

• Intel^® Quartus^® Prime Pro Edition software
• Intel^® Cyclone^® 10 GX FPGA Development Kit

Standard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs. Select the presets at the lower right window in the parameter editor shown in Figure 3.

The presets are applicable for JESD204B IP configurations that generate design examples. You can select one of the presets available for your target device to quickly generate a design example without having to set each parameter in the IP tab and verify that the specified parameters match the supported configurations. You can manually change any of the IP and example design parameters in the Platform Designer user interface after selecting a preset. However, you must ensure that your parameter selection falls within the supported configuration ranges detailed in Supported Configurations for design example to generate successfully.

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

• Platform Designer system
  • JESD204B subsystem
  • JTAG to Avalon master bridge
  • Parallel I/O (PIO)
  • ATX PLL
  • Core PLL
  • PLL reconfiguration module (For transceiver dynamic reconfiguration enabled mode only)
  • Serial Port Interface (SPI)—master module
• Test pattern generator (For duplex and simplex TX data path only)
• Test pattern checker (For duplex and simplex RX data path only)
• Assembler—TX transport layer (For duplex and simplex TX data path only)
• Deassembler—RX transport layer (For duplex and simplex RX data path only)

The Platform Designer system instantiates the JESD204B IP core data path and supporting peripherals.

The top level Platform Designer system instantiates the following modules:

• Platform Designer system
  • JESD204B subsystem
  • JTAG to Avalon master bridge
  • Parallel I/O (PIO)
  • ATX PLL
  • Core PLL
  • Serial Port Interface (SPI)—master module

The following are the key features of the top level Platform Designer system:

• Supports System Console control design example
• Supports 3 data path types:
  • Duplex—Both TX and RX data paths present
  • Simplex TX—Only TX data path present
  • Simplex RX—Only RX data path present
• Supports transceiver dynamic reconfiguration enabled mode:
  • When enabled, connects the JTAG to Avalon master bridge module to the following interfaces:
    • Transceiver PHY reconfiguration interface
    • ATX PLL reconfiguration interface
    • Core PLL reconfiguration controller
  • When disabled, reconfiguration interfaces not present in design example
• The JESD204B subsystem, PLL reconfiguration controller, ATX PLL dynamic reconfiguration interface, parallel I/O and SPI master modules are connected to the JTAG to Avalon master bridge (System Console control) via the Avalon Memory-Mapped (Avalon-MM) interface.
• JTAG to Avalon master bridge provides a link to the user via System Console. You can control the behavior of the design example via Tcl scripts executed in the System Console interface.
• TX data path flow:
  • Input: 32-bit per transceiver lane Avalon Streaming (Avalon-ST) input from assembler (TX transport layer)
  • Output: TX serial data
• RX data path flow:
  • Input: RX serial data from either external converter source or internal serial loopback
  • Output: 32-bit per transceiver lane Avalon Streaming (Avalon-ST) output to deassembler (RX transport layer)
• SPI master module links out to the SPI configuration interface of external converters via a 3- or 4-wire SPI interconnect (depending on Generate 3-Wire SPI Module setting).
• SPI master module handles the serial transfer of configuration data to the SPI interface on the converter end
• The ATX PLL generates the serial clock for clocking the TX serial data
  • ATX PLL module generated for duplex and simplex TX data path only
  • ATX PLL reconfiguration interface only present when transceiver dynamic reconfiguration option is enabled.
  • When present, ATX PLL reconfiguration interface connects to the JTAG to Avalon master bridge (System Console control) module via the Avalon Memory-Mapped (Avalon-MM) interface.
• The core PLL generates the following clocks for the system:
  • Link clock
  • Frame clock

The JESD204B subsystem instantiates the following modules:

• JESD204B Intel^® FPGA IP core
• Reset sequencer
• Transceiver PHY reset controller
• Avalon-MM bridge

JESD204B Subsystem Address Map

Access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window.

Figure 11.  JESD204B Subsystem Address Map

Parallel I/O (PIO) modules provide general input/output (I/O) access from the Avalon master (JTAG to Avalon master bridge). There are two sets of 32-bit PIO registers:

• Status registers—input from the HDL components to the Avalon master
• Control registers—output from the Avalon master to the HDL components

The registers are assigned in the top level HDL file (io_status for status registers, io_control for control registers). The tables below describe the signal connectivity for the status and control registers.

The ATX PLL is a standard Platform Designer component in the IP Catalog standard library. This module supplies a low-jitter serial clock to the transceiver PHY module. The reference clock input to the ATX PLL comes from an external source. If the transceiver dynamic reconfiguration option is selected during design example generation, the ATX PLL has an Avalon-MM interface that connects to the Avalon master (JTAG to Avalon master bridge for System Console control via the Avalon-MM interconnect and can receive configuration instructions from the Avalon master.

For simplex TX variant, the frequency selection in the PLL/CDR Reference Clock Frequency drop-down list in the JESD204B IP parameter editor is disabled. The design example generates the ATX PLL with the reference clock frequency of either:

• Hard PCS: data_rate/20
• Soft PCS: data_rate/40

Refer to Changing the Data Rate or Reference Clock Frequency for more information about modifying the ATX PLL reference clock frequency to suit your application.

For duplex variant, the ATX PLL reference clock frequency shares the frequency with the CDR reference clock. You must select the frequency from the PLL/CDR Reference Clock Frequency drop-down list in the IP parameter editor.

For the ATX PLL reference clock frequencies supported range, refer to the Intel^® Cyclone^® 10 GX Device Datasheet.

The core PLL uses an external clock input as its reference clock to generate two derivative clocks from a single VCO:

• Link clock
• Frame clock

For the frame clock, when the F parameter is 1 or 2, the resulting frame clock frequency can easily exceed the capability of the core PLL to generate and close timing. The top level RTL file, (altera_jesd204_ed_<data path>.sv), defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly.

For this design example, F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. As an example, the actual frame clock for a serial data rate of 10 Gbps and F = 1 is:

(10000/(10 × 1)) / F1_FRAMECLK_DIV = 1000 / 4 = 250 MHz

link_clk period to frame_clk period ratio = 32xL/(MxSxN')

The SPI master module is a standard Platform Designer component in the IP Catalog standard library. This module uses the SPI protocol to facilitate the configuration of external converters (for example, ADC, DAC, external clock modules) via a structured register space inside the converter device. The SPI master has an Avalon-MM interface that connects to the Avalon master (JTAG to Avalon master bridge) via the Avalon-MM interconnect and can receive configuration instructions from the Avalon master.

This module is configured to a 4-wire, 24-bit width interface. If the Generate 3-Wire SPI Module option is selected, an additional module is instantiated to convert the 4-wire output of the SPI master to 3-wire.

For more details on the SPI master module, refer to the JESD204B Intel^® FPGA IP User Guide.

The transport layer in the design example consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is instantiated in the top level RTL file, not in the Platform Designer project.

The transport layer provides the following services to the application layer (AL) and the data link layer (DLL):

• Assembler at the TX path:
  • Maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
  • Reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during TX data streaming.
• Deassembler at the RX path:
  • Maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon-ST interface).
  • Reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during RX data streaming.

The transport layer has many customization options and you can modify the transport layer RTL to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core.

For more details on the implementation of the transport layer in RTL and customization options, refer to the JESD204B Intel^® FPGA IP User Guide.

The test pattern generator generates either a parallel PRBS, alternate checkerboard, or ramp wave, and sends it to the transport layer during test mode. The test pattern generator is implemented in the top level RTL file, not in the Platform Designer project.

You can modify the test pattern generator RTL match your specifications. Furthermore, for parameters like M, S, N, and test mode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core, affects the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR.

The test pattern checker checks either a parallel PRBS, alternate checkerboard, or ramp wave from the transport layer during test mode and outputs an error flag if there are any data mismatches. The test pattern checker is implemented in the top level RTL file, not in the Platform Designer project.

You can modify the test pattern checker RTL to match your specifications. Furthermore, for parameters like M, S, N, and test mode, the test pattern checker shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core, affects the test pattern checker in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR.

The main reference clock for the design example is device_clk. This clock must be supplied from an external source. The device_clk is the reference clock for the core PLL, ATX PLL and the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from device_clk. The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon-MM interfaces of Platform Designer components.

Execute the simulation by running the relevant simulation run scripts in the supported simulator environment. The following table shows the simulators supported along with the relevant run scripts.

The design generates the simulation results which include the transcript or log files in the relevant simulation directory.

The simulation design-under-test (DUT) is the generated design example which includes a synthesizable pattern generator and checker. The figures below show the testbench block diagram for simplex and duplex options.

The simulation flow replaces the JTAG to Avalon master bridge module in the Platform Designer system of the System Console Control design example with the Avalon-MM master bus functional model (BFM). This BFM enables a testbench to send Avalon-MM read/write commands to the design example registers to mimic the functionality of System Console.

The testbench provided in the simulation flow (/testbench/models/tb_top.sv) executes the following steps:

1. Reset DUT.
2. Initialize BFM.
3. Execute Avalon-MM commands to initialize the DUT in the following mode:
   • Internal serial loopback mode (for duplex option only)
   • Pattern generator/checker set to PRBS pattern
4. Wait for DUT to initialize to user mode.
5. Report JESD204B link status.

When simulation ends, the following messages are shown at end.

Refer to the JESD204B RX Address Map and Register Definitions and JESD204B TX Address Map and Register Definitions for the list of registers.