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Notes
1. Verilog HDL Basics
1.1. Course Outline
2. Verilog Overview
2.1. What is Verilog?
2.2. Verilog History
2.3. Verilog HDL Terminology
2.4. Behavior Modeling
2.5. Structural Modeling
2.6. More Terminology
2.7. RTL Synthesis
2.8. Typical RTL Synthesis & RTL Simulation Flows
3. Module Structure
3.1. Verilog - Basic Modeling Structure
3.2. Verilog HDL Model: Demonstration Example
3.3. Module and Port Declaration
3.4. Verilog-2001 & later Module/Port Declaration
3.5. Data Types
3.6. Net Data Type
3.7. Variable Data Types
3.8. Module Instantiation
3.9. Connecting Module Instantiation Ports
3.10. Port Connection Rules
3.11. Parameter
3.12. Assigning Values - Numbers
3.13. Numbers
3.14. Arithmetic Operators
3.15. Bitwise Operators
3.16. Reduction Operators
3.17. Relational Operators
3.18. Equality Operators
3.19. Logical Operators
3.20. Shift Operators
3.21. Miscellaneous Operators
3.22. Operator Precedence
4. Making Assignments
4.1. Continuous Assignment Statements
4.2. Procedural Assignment Blocks
4.3. Initial Block
4.4. Always Block
4.5. Always Block - Example
4.6. Two Types of Procedural Assignments
4.7. Blocking vs. Nonblocking Assignments
4.8. Blocking vs. Nonblocking Assignments
4.9. Blocking/Nonblocking Rule of Thumb
4.10. Two Types of RTL Processes
4.11. Behavioral Statements
4.12. if-else Statements
4.13. case Statement
4.14. Two Other Forms of case Statements
4.15. Forever and Repeat Loops
4.16. While Loop
4.17. For Loop
4.18. Synchronous vs. Asynchronous
4.19. Clock Enable
4.20. Functional Counter
4.21. Functions and Tasks
4.22. Function Definition - Multiplier
4.23. Function Invocation - MAC
4.24. Task Example
4.25. Functions vs. Tasks
5. Verilog Modelsim Demonstration
6. Class Summary
7. Reference Material
8. Learn More Through Technical Training
9. Give us your feedback
10. Thank You
Verilog HDL Basics
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