Webcast: Accelerating Design Development Time with Hard Floating-Point DSP Blocks in FPGAs

FPGAs are great for fixed-point digital signal processing (DSP) implementations. Unfortunately, the same cannot be said for floating point. To efficiently perform floating-point operations on FPGAs, you have to either convert your floating-point algorithm to fixed point in hardware, or use a soft floating-point implementation.

Convert from floating point to fixed point, and your development time increases drastically from the process. Use soft floating-point implementation and you save some of that time, but use up precious logic space and get lower performance.

Altera’s solution to this problem: hard DSP floating-point blocks integrated in FPGAs. Find out how this technology breakthrough in Arria® 10 and Stratix® 10 devices can help you achieve the highest performance and save months of development time.

Watch this 15-minute webcast for:

  • An overview of current floating-point implementation challenges
  • An introduction to Altera’s hard floating-point DSP blocks
  • An overview of how you can achieve unprecedented DSP performance, designer productivity, and logic efficiency

Related Resources

Technical White Paper: Understanding Peak Floating-Point Performance Claims

Read this white paper to:

  • Compare the floating-point performance of DSPs, graphics processing
    units (GPUs), and FPGAs
  • Learn about the challenges of determining the performance of traditional
    FPGA floating-point implementations
  • Examine the applicability of competitive floating-point performance claims