Intel® Stratix® 10 MX FPGA is the essential multi-function accelerator for high-performance computing (HPC), data center, virtual networking functions (NFV), and broadcast applications. These devices combine the programmability and flexibility of Intel® Stratix® 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The Intel® Hyperflex™ FPGA Architecture enables high-performance core fabric that can efficiently utilize the bandwidth from the in-package memory tile. The DRAM memory tile is physically connected to the FPGA using Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology.

Family Variants

All Intel® Stratix® 10 MX Variants

Learn more about all device variations and how specifications compare.

View overview table

Benefits

Expanded Memory Hierarchy

Higher Memory Bandwidth

 

Intel® Stratix® 10 MX devices offer 10X more bandwidth versus current discrete memory solutions such as DDR4 SDRAM. Traditional DDR4 DIMMs provide ~21 GBps bandwidth while 1 HBM2 tile provides up to 256 GBps.

 

Intel® Stratix® 10 MX devices integrate up to two HBM2 devices in a single package, enabling a maximum memory bandwidth of up to 512 GBps.

Lower Power and Optimum Performance/Watt

Intel® Stratix® 10 MX devices integrate HBM2 memory next to the core fabric. The interconnect between the core fabric and memory is significantly shorter, which reduces the amount of power traditionally spent driving long PCB traces. The traces are unterminated and there is reduced capacitive loading, which results in lower I/O current consumption. The net result is lower system power and optimum performance per watt.

Smaller Form Factor and Ease of Use

Because the Intel® Stratix® 10 MX package contains integrated memory components, the PCB design has reduced routing complexity. This implementation enables a smaller form factor and a simple usage model. The net result is a highly flexible, scalable solution that is easy to use.

Enhanced Embedded SRAM

Intel® Stratix® 10 MX devices offer fast path, low-latency on-chip memory through embedded SRAM (eSRAM). eSRAM supplements already existing block RAM. eSRAM features include:

  • Higher Bandwidth: 11.25X more aggregate (read and write) bandwidth relative to discrete QDR IV-10661
  • Lower Power: 2.6X total lower power compared to discrete QDR IV (Watts/Gbps)1
  • Ease of Use: Direct fabric interface, no controller needed, reduced consumption of M20K blocks
  • Reduced Board Cost and Complexity: 
    • Reduced PCB congestion and layer count
    • Helps replace or minimize the need for discrete QDR
    • Zero EMIF I/O consumption
  • Ideal for applications requiring highest levels of random transaction rates (RTR)

Features

Heterogeneous 3D SiP Transceiver Tiles

Path to data rates up to 56 Gbps

Learn more

Floating-Point Digital Signal Processing

Up to 10 tera floating-point operations per second (TFLOPS) of IEEE 754 compliant single precision floating-point (DSP) throughput

Learn more

Secure Device Manager

Intel® Stratix® 10 MX devices integrate HBM2 memory next to the core fabric.

Learn more

Hyperflex™ FPGA Architecture

Delivers 2X the clock frequency performance and up to 70% lower power compared to previous-generation, high-end Intel® FPGAs.1

Learn more

Applications

Documentation and Support


Find technical documentation, videos, and training courses for your Intel® Stratix® 10 MX FPGA designs.

Product and Performance Information

1

Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.