Intel® FPGA Part Number Format

Select an Intel programmable device name to see its associated part number format (described in the tables below).

For information on all part number formats, reference the Product Catalog (PDF).

Code Explanation
AG

Family Signature

A group of Intel programmable logic devices (PLDs) with the same fundamental architecture.

F

Family Variant

This value differentiates the different varieties of the same basic configuration.

A

Specification

The values for the specification group are A: No HPS, B: HPS, C: No HPS + Crypto, D: HPS + Crypto.

014

Logic Density

The logic density value list how many elements were used in this device. The values are: 006: 573k logic elements, 008: 764k logic elements, 012: 1178K logic elements, 014: 1437k logic elements, 019: 1918K logic elements, 022: 2208K logic elements, 023: 2308K logic elements, 027: 2692K logic elements.

R24A

Package Codes

The package can be one of the following values: R16A: Rectangular 1546 balls, R19A: Rectangular 1935 balls, R22A: Rectangular 2280 balls, R24A: Rectangular 2486 balls, R24B: Rectangular 2486 balls, R24C: Rectangular 2340 balls, R25A: Rectangular 2581 balls, R29A: Rectangular 2957 balls, R31A: Rectangular 3184 balls, R31B: Rectangular 3184 balls, R31C: Rectangular 3184 balls.

3

Transceiver Speed Grade

Transceivers are the “backbone” that receive and transmit large amounts of data traffic. This value is noted with 1 being the fastest, 2 being medium, and 3 being the slowest transmission speed.

E

Operating Temperature

There are two basic operating temperatures that device may operate at, E: Extended (0 C to 100 C) or I: Industrial (-40 C to 100C).

3V

Fabric Core Speed / Power

There are multiple Speed/Power settings: 1 Fastest – 4 Slowest, Power: V: Standard Power, (VID), E: Low Power (VID), F: Low Static Power (Fixed), X: Lowest Power (VID).

αα

Optional Suffix

Optional suffixes that are available: Rn: Engineering Sample Revision, Blank: Production (RoHS6).

Code Explanation
1S

Family Signature

A group of Intel programmable logic devices (PLDs) with the same fundamental architecture.

G

Family Variant

This value differentiates the different varieties of the same basic configuration. In this case, this variant specifies the specific variety of Stratix technology in use.

280

Logic Density

The number of logic elements used. A logic element is the smallest unit of logic used in the architecture.

L

SIP Tile Configuration

SIP technology allows integration of multiple dies in a single package. Multiple transceiver dies are available for use Intel® Stratix® 10 FPGA devices, these are the LH, or E-tiles. L-tile contains transceiver channels capable of data rates up to 26.6 Gbps. H-tile contains transceiver channels capable of data rates up to 28.3 Gbps. E-tile contains transceiver channels capable of data rates up to 57.8 Gbps PAM4 or 28.9 Gbps NRZ.

N

Transceiver Count

Multiple counts are available using Stratix technology. The transceiver count number indicates what the technology use for this version of Stratix is. The options are H: 24N: 48S: 72U: 96, and Y: 144.

2

Transceiver Speed Grade

1 being the fastest and 3 being the slowest transmission speed.

F

Package Type

The only option for package type currently is F: Fine line BGA.

43

Package Code

The package code is 35: 1,152 pins, 35 X 35 mm, 43: 1,760 pins, 42.5 X 42.5 mm, 50: 2,397 pins, 50 X 50 mm, 55: 2,912 pins, 55 X 55mm.

E

Operating Temperature

There are three basic operating temperatures that device may operate at, C: Commercial (25C to 85C), E: Extended (0C to 100C), or I: Industrial (-40C to 100C).

2

FPGA Fabric Speed Grade

The Fabric Speed grade is represented by a value from 1 to 3.  (1 = Fast 3= Slow).

V

Power Profile

This value may be V: Standard PowerL: Low Power, or X: Extreme Low Power.

G

Package Material

This indicates package material is G: RoHS 6.

S1

Optional Suffix

The optional Suffix is Characters 17 and 18 Engineering Sample S(n) or Advanced Security AS.

Prefixes

Part Number Prefix Codes

To find out which devices are available in a particular device family, or to find out more about a particular device, check the specific device's datasheet.

Part Number Prefix Device Family
EP1K ACEX®
EP20K (see EP20KxxxC) APEX™ 20K
EPC Configuration
EPF FLEX®
EPM Intel® MAX®
EPxxx

Classic

note: xxx = any three numbers

5M MAX® V
EP1AGX Arria® GX (with transceivers)
EP2AGX Arria II GX (with transceivers)
EP1C Intel® Cyclone®
EP1M Mercury™
EP1S Stratix®
EP1SGX Stratix® GX (with transceivers)
EP20KxxxC

APEX™ 20KC

note: xxx = any three numbers

EP2A APEX™ II
EP2C Cyclone® II
EP2S Stratix® II
EP2SGX Stratix® II GX (with transceivers)
EP3C Cyclone® III
EP3SL Stratix® III L (logic enhanced)
EP3SE Stratix® III E (DSP/memory enhanced)
EP4CE Cyclone® IV (enhanced)
EP4CGX Cyclone® IV GX (with transceivers)
EP4SE

Stratix® IV E (enhanced)

note: EP4SE, EP4SGX, EP2AGX, and EP4CGX devices use package sizes in place of pin counts in part number.

EP4SGX

Stratix® IV GX (with transceivers)

note: EP4SE, EP4SGX, EP2AGX, and EP4CGX devices use package sizes in place of pin counts in part number.

EP4S40/100 Stratix® IV GT (with transceivers)
EPM MAX® II, MAX IIG (lower power), MAX IIZ (zero power)
EPXA Excalibur™
5SGX Stratix® V GX (with 12.5-Gbps transceivers)
5SGS Stratix® V GS (with 12.5-Gbps transceivers and high DSP capability)
5SGT Stratix® V GT (with 28-Gbps transceivers)
5SE Stratix® V E with up to 1,100K LEs
5CGX Cyclone® V GX (with 3.125-Gbps transceivers)
5CGT Cyclone V GT (with 5.0-Gbps transceivers)
5CE Cyclone® V E with up to 301K LEs
HC4GX HardCopy IV GX (with transceivers)
HC4E HardCopy IV E
HC3 HardCopy III
HC2 HardCopy II

Package Codes

Package codes are the same in all part number formats. Immediately following the package code is the pin count. For example, a 780-pin count FineLine BGA package type would be represented by F780.

For the EP4SE, EP4SGX, EP2AGX, and EP4CGX FPGA families, the package code is not followed by the pin count, but by the package dimensions. The translation from the pin count to the package dimension is provided in the 'Package Size and Pin Count' section.

Package Type Codes

5SGX, 5SGS, 5SGT, 5SE, 5CE, EP4SE, EP4SGX, EP2AGX, EP4CE, and EP4CGX devices use package sizes in place of pin counts.

Code Package Type
B Ball-grid array
D Ceramic dual in-line package
E Plastic enhanced quad flat pack
F FineLine BGA package
G Ceramic pin-grid array
H Hybrid FineLine BGA package
L Plastic J-lead chip carrier
M Micro FineLine BGA package
N Quad flat no-lead
P Plastic dual in-line package
Q Plastic quad flat pack
R Power quad flat pack
S Small outline integrated circuit
T Thin quad flat pack
U Ultra FineLine BGA package

Package Size and Pin Count

Package Size and Pin Count Codes

Translation from the pin count to the package dimension.

Package Size Pin Count
U17 U358
F25 F572
F29 F780
F35 F1152
F40 F1517
F43 F1760
F45 F1932
H29 H780
H35 H1152
N11 QFN148

Temperature Codes

Temperature Codes

Temperature codes are the same for all part number formats.

Code Explanation
C Commercial temperature range (0 to 85°C)
I Industrial temperature range (-40 to 100°C)
A Automotive temperature range (-40 to 125°C)

Speed Grades

Intel MAX and Classic devices use the speed grade to indicate the delay in nanoseconds (ns) through a macrocell in the device. For example, a MAX device with a -10 speed grade has a delay of 10 ns through a macrocell. Devices with low speed grade numbers run faster than devices with high speed grade numbers.

Intel® Stratix® series, Intel® Cyclone® series, MAX® II, MAX IIG, MAX IIZ, FLEX®, ACEX®, APEX™, Mercury™, and Excalibur™ devices use the speed grade to indicate the relative performance of the device. Devices with low speed grade numbers run faster than devices with high speed grade numbers. For example, a Stratix® III FPGA with a three speed grade is the fastest available Stratix III FPGA.

Suffixes

Suffix Codes

Suffixes are optional letters at the end of a part number that specify certain device features. Not all suffixes are available with all part numbers.

Code Explanation
A Aluminum process
C Device shipped in a carrier
DX FLEX EPF10K100 devices with PLLs
ES Engineering sample
F Fixed programming algorithm (for use with in-circuit testers)
H Special dry-packing shipment option for MAX® 7000 devices
L Stratix® III: 0.9-V core voltage
N RoHS compliant
P Special PCI-compliant MAX devices
T Classic devices: Permanently set in turbo (high-speed) mode - MAX 7000 devices: Special timing parameters (see datasheet for details)
V 5.0-V tolerant inputs
X PLLs in APEX™ and FLEX 10KE devices
Z Low-power FLASHLOGIC devices (discontinued)