Nios® II Processor Benefits

Nios® II embedded processors provide an ideal embedded solution offering flexibility, high performance, low cost, and a long life cycle. 

Flexibility

The World's Most Versatile Processor

With the perfect fit of CPUs, peripherals, memory interfaces, and custom hardware peripherals to meet the unique demands of every new design cycle, Nios®II processors offer you tremendous flexibility where you need it:

  • Optimized family of CPUs—Choose from among several Nios® II CPUs, each one optimized for a specific price/performance point, and all supported by the same software tool chain.
  • Customizable peripheral set—Using the Intel® Quartus® Prime software and embedded peripherals, you create the exact set of peripherals, memories, and I/O circuitry needed for any application, including configurations not available in off-the-shelf processors.
  • Choice of target silicon—Intel offers a wide range of FPGAs, covering a wide range of cost/performance needs. Nios® II processors support all of Intel's mainstream FPGAs.
  • Performance scalability—Boost software performance using hardware accelerators, custom instructions, and of course multi-processor systems. Now Intel even offers tools for automated acceleration.

A major challenge facing embedded developers is selecting a processor that best fits the application without overspending for performance or sacrificing features. There are hundreds of processors available, from many suppliers, each with a different set of peripherals, memories, interfaces, and performance characteristics. Inevitably, you wind up either paying too much (to ensure that you don't miss the mark on features or performance) or getting less than you need (to avoid overspending on features or performance that your application doesn't need).

Long Life Cycle

Nios® II processors can help product developers to maximize their return on a product by providing life cycle benefits at every stage of a product's life, including:

  • Getting the product to market quickly
  • Adding features and reducing costs to stay in the market longer
  • Avoiding costly processor obsolescence and premature market exit

Nios® II processors offer unique benefits at each stage of a product's life.

Development

Time-to-Market Benefits—FPGAs offer very fast time-to-market due to their programmability. Many common design errors can be fixed quickly with simple changes to the FPGA design. Nios® II processor systems take advantage of this flexibility and further accelerate time to market by offering complete development kits, numerous reference designs, and powerful hardware design tools. It also offers software design tools, such as the Nios® II Integrated Development Environment (IDE).

Being first to market can often mean shipping a less-complete product than desired. FPGA-based systems using a Nios® II processor offer the unique advantage of being able to update hardware features to products already deployed in the field, the same way software is updated. This solves several problems:

  • Extends product life, allowing the hardware to be feature-filled over time
  • Reduces the risk of using hardware that is based on emerging (or changing) standards
  • Simplifies hardware bug fixes and eliminates the need for product returns and rework

Creating a Competitive Advantage—A competitive advantage based on a common hardware platform is hard to maintain. Create a significant barrier to entry and/or competitive advantage for your product. by creating a system using one or more Nios® II processors, hardware accelerators, custom instructions, and custom-tailored peripherals.

Introduction and Growth

The introduction and growth stages are marked by a fast increase in sales and the move to profitability through volume production and cost reductions. Product engineers have long used FPGAs to enable a short ramp-up to full production, but Intel's new generation of low-cost FPGAs lets you keep the same design flow throughout the production process, from prototyping all the way to volume shipping.

Additionally, the versatile Nios® II processors give embedded developers the flexibility to add hardware features or accelerators, even late in the development stage. This is to boost performance and add features that will help to insulate your product from the competition.

Maturity and Decline

Cost Reduction—At this stage, the market is no longer growing; the key issues are cost pressures from the competition. Intel offers an ASIC license for the Nios® II processor, peripherals, and switch fabric interconnect for designs that need to migrate to standard cell-based ASIC designs. Contact your local Intel representative for details.

 

Processor Obsolescence—To accommodate a diverse customer base, embedded processor vendors offer a range of configuration choices within a processor family. However, many of these processor variants are obsoleted earlier than the rest of the family. Savvy designers realize that the soft Nios® II processors aren't subject to the same market pressures as hard processors. Nios® II processor designers have a perpetual license to create and deploy Nios® II processor-based designs in Intel FPGAs, so even if the underlying FPGA hardware changes, the investment in application software is preserved.

The low minimum-quantity purchasing flexibility that Intel offers for its FPGAs is a great relief to product managers looking to maximize the life span and return on a product. Decline of a market is inevitable, but a product can certainly phase out gracefully.

You can buy Intel® devices online.

Low Cost

Intel's Nios® II embedded processor provides phenomenal cost flexibility, allowing you to choose the exact set of processors, peripherals, memory, and interfaces that you need for your application, without paying for features that you don’t need. As a designer, you have to find ways to reduce development and component costs to meet your design specifications and deadlines. The Nios® II processor gives you the cost flexibility to meet these requirements.

Feature Description
Low-Cost Processor Core Utilize the fewest possible logic and memory resources with the Nios® II/e "economy" core, the absolute lowest cost Nios® II processor.
Greater System-Level Integration Create exact-fit systems by combining one or more CPUs with the exact set of peripherals, memory, and I/O interfaces, greatly reducing board cost, complexity, and power consumption.
Cost-Optimized FPGA Combine the Nios® II/e core with a low-cost Cyclone® III FPGA and consume as little as 25 cents of the Cyclone® III device's cost. This will leave plenty of logic for implementing functions previously handled by external devices. Learn more about Intel Cyclone® series.
Cost-Efficient Acceleration Boost software performance in a cost-efficient way by offloading performance-critical software functions to hardware accelerators in the FPGA.
Low-Cost Tools and Development Kits Download the Nios® II Embedded Design Suite and evaluate the tools and processor for free today. Then, you can purchase a low-cost development kit that includes everything you need to create complete on-chip microprocessor systems. Learn more about Nios® II development kits
Royalty-Free License Pay no royalties for Nios® II processors implemented in Intel® FPGAs. Learn more about Nios® II development kits

High Performance

Intel Nios® II processors give you the ultimate flexibility to achieve the exact performance required for your embedded design, without overpaying for high clock frequency, power-hungry off-the-shelf processors. Additionally, Nios® II processors help you avoid last-minute hand-tuning of assembly language code, giving you configurable performance features that can be designed in as needed.

Feature Description Get Details
High-Performance Processor Core Optimized for performance-critical applications, the Nios® II/f "fast" core has a 6-stage pipeline, dynamic branch prediction, instruction and data cache, and 250+ MHz performance. High-performance FPGAs, such as those in the Stratix® III device family, give the Nios® II/f core enough performance for many core processing tasks. Intel Stratix® Series FPGAs
Multi-High-performance FPGAs Use multicore systems to scale a system's performance or to divide software applications into simpler tasks. The Nios® II Embedded Design Suite (EDS) includes support for creating customized multicore systems. Nios® II processors, combined with extremely high-density FPGAs such as those in the Stratix® III device family, are ideal for creating high-performance multiprocessor applications.

Creating Multiprocessor Nios® II Systems Tutorial (PDF)

Intel Stratix® Series FPGAs

High-Bandwidth Bus Structure Automatically generate an Avalon® interconnect fabric to support any system that you build by using the SOPC Builder system generation tool. This tool allows you to generate high-throughput systems that support simultaneous multiple master/slave connections, direct memory access (DMA) channels, and on-chip data buffers.

Avalon® switch fabric features

Avalon® Interface Specification(PDF)

Custom Instructions Accelerate time-critical software algorithms by adding custom instructions to the Nios® II instruction set. Nios® II Custom Instruction User Guide (PDF)
Fast Configurable On-Chip Memory Create fixed low-latency on-chip memory buffers for performance-critical applications.

Cache & Tightly-Coupled Memory (PDF) in the Nios® II Software Developer’s Handbook

Using Nios® II Tightly Coupled Memory Tutorial (PDF)

Flexible Processing With FPGAs

Traditionally, embedded developers have had limited options for accelerating performance near the end of a design cycle, including buying a faster processor or hand-tuning assembly language subroutines. While both options can be effective, the trade-offs they bring are too large to ignore. What designer wants to add cost or increase power usage? Who wants hand-optimized assembly code that is tied closely to a specific processor architecture?

Nios® II processors are the right choice if:

  • Your application is too large and complex to develop and debug and still meet the schedule
    • Create a multiprocessor Nios® II system with a few mouse clicks and partition your code into two smaller, simpler applications. You will meet timing, validate your application, and be shipping product in no time.
  • Your application does not meet your timing requirements
    • Nios® II developers can add a custom instruction or hardware accelerator to selectively boost only the bottle-neck routine.

FPGAs and Nios® II processors give you a whole new toolbox of performance features, as well as many options for reducing risk in embedded design.

JTAG Debug Module

The Nios® II processor architecture supports a Joint Test Action Group (JTAG) debug module that provides on-chip emulation features to control the processor remotely from a host PC. PC-based software debugging tools, such as the Nios® II Embedded Design Suite (EDS), communicate with the JTAG debug module and enable designers to do the following:

  • Downloading programs to memory
  • Starting and stopping execution
  • Setting breakpoints and watchpoints
  • Analyzing registers and memory
  • Collecting real-time execution trace data

The debug module connects to the JTAG circuitry built into all Intel® FPGAs (shown in Figure 1) and connects to the host PC via a download cable, such as the Intel USB BlasterTM cable (included in the Nios® II development kits) or a third-party system analyzer probe.

Software developers can access the core from a host software such as the Nios® II EDS (included in all Nios® II development kits) or through an integrated design environment (IDE) and debugger from Intel's embedded software tools partners.

Customers requiring a more advanced set of debugging features can upgrade to a third-party probe solution.

More information regarding the JTAG debug module and software debugging using the Nios® II IDE is available on the Nios® II processor handbook.

 

Hardware Acceleration

Need to boost performance? No problem. Hardware acceleration is as easy as using an FPGA's programmable logic to offload and accelerate tasks that are typically implemented in application software.

Read on to learn more about accelerating software in FPGAs.

Custom Instructions

Similar to hardware accelerators, custom instructions allow Nios® II processor designers to increase system performance by offloading portions of the software code to hardware functions. Custom instructions, however, are implemented within the processor boundary, extending the CPU instruction set to accelerate time-critical software.

The configurable nature of Nios® II processors enables designers to integrate custom logic directly into the arithmetic logic unit (ALU). Custom instructions let developers optimize software inner loops for applications such as digital signal processing (DSP), packet header processing, and computationally intensive applications. This reduces complex operational sequences to a single instruction implemented in hardware.

Using custom instructions, designers can optimize their system performance in a way not possible with traditional off-the-shelf processors. The Platform Designer (formerly Qsys) provides a graphical user interface that developers can use to easily import their own hardware design files to create custom instructions that are automatically integrated into the Nios® II processor.

Nios® II processor custom instructions provide:

  • Up to 256 user-defined instructions
  • Fixed and variable-cycle operation
  • User-logic import wizard
  • C and assembly language software macros

Nios® II Processor Cores

Nios® II Processor Variants

Used by more designers than any other soft processor in the world, Nios® II embedded processors remain the industry-standard processor for FPGA design. The Nios® II family of embedded processors currently consists of three processor cores that implement a common instruction set architecture, each optimized for a specific price/performance point, and all supported by the same software tool chain.

Designers can choose from the following cores:

  • Nios® II/f: fast
  • Nios® II/e: economy

For technical detail on the Nios® II processor cores, refer to the Nios® II Core Implementation Details chapter of the Nios® II Processor Reference Handbook.

Note: The Nios® II/s core is only available with the Nios® II Classic product. A core with the same configuration can now be created by selecting the /f core and configuring the appropriate options. 

Nios® II/f "Fast"

Intel specifically designed the Nios® II/f “fast” processor for high performance. With performance over 300 MIPS* (*Dhrystones 2.1 benchmark), it is optimal for performance-critical applications as well as applications with large amounts of code and data, such as running a full-featured operating system.

The Nios® II/f core is supported by the Nios® II Embedded Design Suite (EDS), including the Eclipse-based Nios® II Integrated Development Environment (IDE).

The Nios® II/f core features:

  • Memory management unit (MMU)
  • Memory protection unit (MPU)
  • External vectored interrupt controller
  • Advanced exception support
  • Separate instruction and data caches (512 bytes to 64 KB)
  • Access to up to 4 GB of external address space
  • Optional tightly-coupled memory for instructions and data
  • Six-stage pipeline to achieve maximum MIPS* (*Dhrystones 2.1 benchmark) per MHz
  • Single-cycle hardware multiply and barrel shifter
  • Hardware divide option
  • Dynamic branch prediction
  • Up to 256 custom instructions and unlimited hardware accelerators
  • JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

The Nios® II/f core provides additional functionality and performance when targeting Intel® device families with digital signal processing (DSP) blocks. In this case, the Nios® II/f core provides hardware multiply circuitry that achieves single-cycle multiply operations. The multiply unit also functions as a single-cycle barrel shifter. The Nios® II/f core provides optional divide circuitry that accelerates divide operations.

For the highest performance, implement the Nios® II/f core in Intel's highest performance FPGAs.

Nios® II/e "Economy"

Intel specifically designed the Nios® II/e "economy" processor cores to use the fewest FPGA logic and memory resources.It is now offered free for both Nios® II Classic and Nios® II Gen2 processors. No license is required with the Intel Quartus® Prime software and Intel Quartus® development software version 9.1 and later. The Nios® II/e core has higher performance but is in the same cost class as a typical 8051 architecture, achieving over 30 DMIPS at up to 200 MHz. It is using fewer than 700 logic elements (LEs).

The core is supported by the Nios® II Embedded Design Suite (EDS), including the Eclipse-based Nios® II Integrated Development Environment (IDE).

The free Nios® II/e core features:

  • Up to 2 GB of external address space 
  • JTAG debug module
  • Complete processors in fewer than 700 LEs
  • Optional debug enhancements
  • Up to 256 custom instructions

The Nios® II/e core is optimal for cost-sensitive applications, such as those found in the automotive, industrial, and consumer markets. This core is often paired with Intel's low-cost FPGAs.

Nios® II/s "Standard"

The Nios® II/s core is only available with the Nios® II Classic product. A core with the same configuration can now be created by selecting the /f core and configuring the appropriate options. The Nios® II/s "standard" processor core was orginally created to implement a smaller processor core without a significant trade-off in software performance. The Nios® II/s core (or equivalent /f configuration) is optimal for cost-sensitive, medium-performance applications, including those with large amounts of code and/or data. For example, systems running a full featured operating system.

The core is supported by the Nios® II Embedded Design Suite (EDS), including the Eclipse-based Nios® II Integrated Development Environment (IDE).

The Nios® II/s core features:

  • Instruction cache
  • Up to 2 GB of external address space
  • Optional tightly coupled memory for instructions
  • 5-stage pipeline
  • Static branch prediction
  • Hardware multiply, divide, and shift options
  • Up to 256 custom instructions
  • JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

The Nios® II/s core provides additional functionality and performance when targeting Intel device families with DSP blocks. In this case, the Nios® II/s core provides hardware multiply circuitry that achieves 3-cycle multiplication operations. The multiply unit also functions as a barrel shifter.