Cyclone® V FPGAs provide the industry's lowest system cost and power, along with performance levels you need to differentiate your high-volume applications. Choose from the following variants:
Cyclone® V FPGAs continue the Intel® Cyclone® device family tradition of an unprecedented combination of low power, high functionality, and low cost. The Cyclone V FPGA now includes an optional integrated hard processor system (HPS) – consisting of processors, peripherals, and memory controller – with the FPGA fabric using a high-bandwidth interconnect backbone. The combination of the HPS with Intel's 28 nm low-power FPGA fabric provide the performance and ecosystem of an applications-class ARM processor with the flexibility, low cost, and low power consumption of the Cyclone V FPGAs.
The Cyclone V FPGA core architecture comprises the following:
All of these logic resources are interconnected through a highly flexible clocking network, with over 30 global clock trees and a power-optimized version of Intel's high-performance MultiTrack routing architecture.
Cyclone V FPGAs provide flexible interface support with up to 12 5-Gbps transceivers on the left side of the die. The logic and routing core fabric is surrounded by I/O elements and PLLs, as shown in Figure 1. Cyclone V devices have two to eight PLLs. The I/O elements support 840 MHz LVDS and 800 Mbps of external memory bandwidth. These I/O elements provide support for all mainstream differential and single-ended I/O standards including 3.3 V LVTTL at up to 16-mA drive strength.
Cyclone V FPGAs include hard intellectual property (IP) blocks, such as an ARM-based HPS, up to two PCI Express* (PCIe*) hard IP blocks, and up to two hardened multiport memory controllers. The hardened PCIe block supports widths up to four lanes for Gen1 and four lanes for Gen2
To protect your valuable IP investments, Cyclone V FPGAs also provide the most comprehensive design protection available in FPGAs, including 256 bit Advanced Encryption Standard (AES) bitstream encryption, JTAG port protection, internal oscillator, zeroization (active clear), and cyclic redundancy check (CRC) features.
The multiport memory controller hard intellectual property (IP) block brings a new level of productivity and time-to-market advantage. The advanced features for supporting command and data reordering significantly increases the efficiency of your DRAM interface. The multiport memory controller eases timing closure and reduces I/O count by allowing up to six functions to share a single memory device, therefore saving PCB space and increasing bus efficiency. As a result, you save time, system cost, and power.
The multiport memory controller IP supports the following features:
The multiport memory controller consists of two major blocks as shown in Figure 1:
The multiport front end provides the following arbitration and reordering features:
The PHY interface on the multiport memory controller offers the following calibration features for data sequencing and timing control:
The multiport memory controller hard IP in the Cyclone® V FPGA supports DDR3 SDRAM, DDR2 SDRAM, and LPDDR2 (single-rank support only). The Cyclone V FPGA also supports the soft memory controllers for the memory interfaces mentioned.
Intel has taken significant steps to reduce power in Cyclone V FPGAs including
The combination of increased integration and a low-power Cyclone V FPGA results in significant system-level benefits for a variety of applications:
Intel makes power estimation and analysis from design concept through implementation easy, with the most accurate and complete power management design tools in the industry. Intel offers the following power estimation and analysis resources:
When designing, you can use the early power estimator (EPE) during the design concept phase and the power analyzer during the design implementation phase. The EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization. The power models in the EPE are correlated to silicon, ensuring an accurate estimation of your design's power consumption.
The power analyzer is a far more detailed power analysis tool that uses actual design placement and routing, logic configuration, and simulated waveforms to estimate dynamic power very accurately. The power analyzer, in aggregate, provides approximately 10-percent accuracy when used with accurate design information. Intel® Quartus® Prime software power models are correlated to silicon measurements based on over 5,000 test configurations per circuit.
Throughout the design process the Power Management Resource Center provides useful information regarding power, thermal management, and power supply management.
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area tradeoffs have been automated within the register transfer level (RTL) through the place-and-route design flow. Intel has taken a leadership position in bringing power optimization into the design flow. Intel® Quartus® Prime software optimization tools automatically use the Cyclone V architecture capabilities to reduce power further, resulting in up to 10 percent lower total power consumption when enabled.
The Intel® Quartus® Prime software optimization has many automatic power optimizations that are transparent to you but provide optimal utilization of FPGA architecture details to minimize power, including:
Although the HPS and the FPGA can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM AMBA AXI bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly, HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to six FPGA masters can share the HPS SDRAM controller with the processor. Additionally, the processor can be used to configure the FPGA fabric under program control via a dedicated 32 bit configuration port.
Not all low-cost transceivers are created equally. Intel's Cyclone® V FPGA family has a flexibility that helps you fully utilize all available transceiver resources and keep designs in a smaller and lower cost device. The Cyclone V FPGAs provide the most flexibility in implementing independent protocols, implementing proprietary protocols with hardened building block, all at the lowest power possible.
By providing the market's lowest cost, lowest power FPGAs, Intel's Cyclone V FPGA family extends the Cyclone FPGA series. Intel's transceiver leadership is re-affirmed with actual shipment of working transceiver I/O within an FPGA design. Watch the video below to see Cyclone V FPGAs in action.
The Cyclone V FPGA series offers two variants to meet your design needs, the Cyclone V GX FPGAs with transceivers up to 3.125 G and Cyclone V GT FPGAs with transceivers up to 6.144 G.
Key Transceiver Features
Figure 1 shows the block diagram of the Cyclone V FPGA transceivers, both