Both GX and E device architectures include highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals.

Table 1. Cyclone® IV GX FPGA Family Overview

Device EP4CGX15 EP4CGX22 EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 EP4CGX150
Logic elements (LEs) 14,400 21,280 29,440 49,888 73,920 109,424 149,760
M9K memory blocks 60 84 120 278 462 610 720
Embedded memory (Kbits) 540 756 1,080 2,502 4,158 5,490 6,480
18 bit x 18 bit multipliers 0 40 80 140 198 280 360
PCI Express* (PCIe*) hard IP block 1 1 1 1 1 1 1

Phase-locked loops (PLLs) (Includes both general-purpose and multi-purpose PLLs (GPLL + MPLL))

3 4 4 8 8 8 8
Transceiver I/Os 2 4 4 8 8 8 8
Maximum user I/Os 72 150 290 310 310 475 475
Maximum differential channels 25 64 109 140 140 216 216

Table 2. Cyclone® IV E FPGA Family Overview

Device EP4CE6 EP4CE10 EP4CE15 EP4CE22 EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115
LEs 6,272 10,320 15,408 22,320 28,848 39,600 55,856 75,408 114,480
M9K memory blocks 30 46 56 66 66 126 260 305 432
Embedded memory (Kbits) 270 414 504 594 594 1,134 2,340 2,745 3,888
18-bit x 18-bit multipliers 15 23 56 66 66 116 154 200 266
PLLs 2 2 4 4 4 4 4 4 4
Maximum user I/Os 179 179 343 153 532 532 374 426 528
Maximum differential channels 66 66 137 52 224 224 160 178 230

Note:

  1. All Cyclone® IV E devices are available in two Vcc variants:.

Table 3. Cyclone® IV GX Device Packages and Maximum User I/Os

  F169 F169 F324 F324 F484 F484 F672 F672 F896 F896

Device/Package

(mm x mm)

1.0 mm

14 x 14

1.0 mm

14 x 14

1.0 mm

19 x 19

1.0 mm

19 x 19

1.0 mm

23 x 23

1.0 mm

23 x 23

1.0 mm

27 x 27

1.0 mm

27 x 27

1.0 mm

31 x 31

1.0 mm

31 x 31

 

I/Os XCVRs I/Os XCVRs I/Os XCVRs I/Os XCVRs I/Os XCVRs
EP4CGX15 72 2
EP4CGX22 72 2 150 4
EP4CGX30 72 2 150 4 290 4
EP4CGX50 290 4 310 8
EP4CGX75 290 4 310 8
EP4CGX110 270 4 393 8 475 8
EP4CGX150 270 4 393 8 475 8

Note:

  1. All packages are wire bond packages and come in both leaded and RoHS-compliant options

Table 4. Cyclone® IV E Device Packages and Maximum User I/Os

  E144 M164 M256 U256 F256 F324 U484 F484 F780
Device/Package

22 x 22 mm 

0.5 mm

8 x 8 mm 

0.5 mm

9 x 9 mm 

0.5 mm

14 x 14 mm 

0.8 mm

17 x 17 mm 

1.0 mm

19 x 19 mm 

1.0 mm

19 x 19 mm 

0.8 mm

23 x 23 mm 

1.0 mm

29 x 29 mm 

1.0 mm

EP4CE6 91 179 179

EP4CE10 91 179

179

EP4CE15 81 89 165 165 165 343
EP4CE22 79 153 153
EP4CE30 193 328 532
EP4CE40 193 328 328 532
EP4CE55 324 324 374
EP4CE75 292 292 426
EP4CE115 280 528

Note:

  1. All packages are wire bond packages and come in both leaded and RoHS-compliant options

Table 5. cTemperature Speed Grades for the Cyclone® IV GX FPGA Family

  F169 F324 F484 F672 F896
Device/Package

1.0 mm

14 x 14 mm

1.0 mm

19 x 19 mm

1.0 mm

23 x 23 mm

1.0 mm

27 x 27 mm

1.0 mm

31 x 31 mm

EP4CGX15 -6, -7, -8
EP4CGX22 -6, -7, -8 -6, -7, -8
EP4CGX30 -6, -7, -8 -6, -7, -8 -6, -7, -8
EP4CGX50 -6, -7, -8 -6, -7, -8
EP4CGX75 -6, -7, -8 -6, -7, -8
EP4CGX110 -7, -8 -7, -8 -7, -8
EP4CGX150 -7, -8 -7, -8 -7, -8

Note:

  1. The -7 speed grade is under review, pending completion of device characterization.

Table 6. Commercial Temperature Speed Grades for the Extended Cyclone® IV FPGA Family

  144-Pin 164-Pin 256-Pin 256-Pin 256-Pin 484-Pin 484-Pin 780-Pin

Device/Package

(mm x mm)

22 x 22 mm 

0.5 mm

8 x 8 mm 

0.5 mm

9 x 9 mm 

0.5 mm

14 x 14 mm 

0.8 mm

17 x 17 mm 

1.0 mm

19 x 19 mm 

0.8 mm

23 x 23 mm 

1.0 mm

29 x 29 mm 

1.0 mm

EP4CE6 -6, -7, -8, -8L, -9L

-7 

-6, -7, -8, -8L, -9L
EP4CE10 -6, -7, -8, -8L, -9L -7  -6, -7, -8, -8L, -9L
EP4CE15 -6, -7, -8, -8L, -9L -7 -7 -7 -6, -7, -8, -8L, -9L -6, -7, -8, -8L, -9L
EP4CE22 -6, -7, -8, -8L, -9L -7 -6, -7, -8, -8L, -9L
EP4CE30 -6, -7, -8, -8L, -9L -6, -7, -8, -8L, -9L
EP4CE40 -7 -6, -7, -8, -8L, -9L -6, -7, -8, -8L, -9L
EP4CE55 -7 -6, -7, -8, -8L, -9L -6, -7, -8, -8L, -9L
EP4CE75 -7 -6, -7, -8, -8L, -9L -6, -7, -8, -8L, -9L
EP4CE115 -6, -7, -8, -8L, -9L -6, -7, -8, -8L, -9L

Notes:

  1. All packages are wire bond packages and come in both leaded and RoHS-compliant options.
  2. Final speed grade plan subject to change pending completion of device characterization.
  3. Only -8L and -9L speed grades support Vcc = 1.0-V operation.

Table 7. Industrial Temperature Support for Cyclone® IV GX Device

Device Package Speed Grade
EP4CGX15 169-pin FBGA -7
EP4CGX22

169-pin FBGA

324-pin FBGA

-7
EP4CGX30

169-pin FBGA

324-pin FBGA

484-pin FBGA

-7
EP4CGX50

484-pin FBGA

672-pin FBGA

-7
EP4CGX75

484-pin FBGA

672-pin FBGA

-7
EP4CGX110

484-pin FBGA

672-pin FBGA

896-pin FBGA

-7
EP4CGX150

484-pin FBGA

484-pin FBGA

896-pin FBGA

-7

Table 8. Industrial Temperature Support for Cyclone® IV E Device

Device Package Speed Grade
EP4CE6

144-pin EQFP 

256-pin UBGA (Available in RoHS-compliant package option, -7 speed grade)

256-pin FBGA

-7, -8L
EP4CE10

144-pin EQFP 

256-pin UBGA (Available in RoHS-compliant package option, -7 speed grade)

256-pin FBGA

-7, -8L
EP4CE15

144-pin EQFP 

164-pin MBGA (Available in RoHS-compliant package option, -7 speed grade)

256-pin UBGA (Available in RoHS-compliant package option, -7 speed grade)

256-pin FBGA 

484-pin FBGA

-7, -8L
EP4CE15 256-pin MBGA (Available in RoHS-compliant package option, -7 speed grade) -7
EP4CE22

144-pin EQFP 

256-pin UBGA (Available in RoHS-compliant package option, -7 speed grade)

256-pin FBGA

-7, -8L
EP4CE30

484-pin FBGA 

780-pin FBGA

-7, -8L
EP4CE40

484-pin FBGA 

484-pin UBGA (Available in RoHS-compliant package option, -7 speed grade)

780-pin FBGA

-7, -8L
EP4CE55

484-pin FBGA 

484-pin UBGA (Available in RoHS-compliant package option, -7 speed grade)

780-pin FBGA

-7, -8L
EP4CE75

484-pin FBGA 

484-pin UBGA (Available in RoHS-compliant package option, -7 speed grade)

780-pin FBGA

-7, -8L
EP4CE115

484-pin FBGA 

780-pin FBGA

-7, -8L

Note:

  1. Extended industrial temperature (-40°C to +125°C) is supported for Vcc = 1.2V devices. Order the -7 speed part numbers.

Table 9. Automotive Grade Support for Cyclone® IV E Device

Device Package Speed Grade
EP4CE6

144-pin EQFP 

256-pin FBGA

-A7
EP4CE10

144-pin EQFP 

256-pin FBGA

-A7
EP4CE15

256-pin FBGA 

484-pin FBGA

-A7
EP4CE22

144-pin EQFP 

256-pin FBGA

-A7
EP4CE30

324-pin FBGA 

484-pin FBGA

-A7
EP4CE40

324-pin FBGA 

484-pin FBGA

-A7

Complete Design Resources

For a smooth and successful design flow that quickly turn your ideas into revenue, Intel provides a complete Cyclone® IV FPGA design environment including:

Cyclone IV GX Transceivers, PMA & PCS Block Diagram

Cyclone IV GX FPGAs: Transceiver Overview

The Cyclone® IV FPGA family extends the Intel Cyclone FPGA series leadership in providing the market’s lowest cost, lowest power FPGAs, now with transceivers.

Not all low-cost transceivers are created equally. The Cyclone IV GX FPGA was specifically designed to allow the implementation of multiple protocols in a single quad and to allow independent receive and transmit frequencies. This flexibility helps you fully utilize all available transceiver resources and keep designs in a smaller and lower cost device.

Key Transceiver Features:

  • Up to eight transceivers with clock data recovery (CDR), supporting data rates from 600 Mbps to 3.125 Gbps.
  • Flexible and easy-to-configure transceiver datapath to implement industry-standard and proprietary protocols.
  • Programmable pre-emphasis settings and adjustable differential output voltage (VOD) for improved signal integrity.
  • User-controlled receiver equalization to compensate for frequency-dependent losses in the physical medium.
  • Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA.
  • Support for protocol features such as spread-spectrum clocking in PCI Express*, DisplayPort, V-by-One, and SATA configurations.
  • Dedicated circuitry compliant with the physical interface for PCI Express, XAUI, and Gbps Ethernet.
  • PIPE interface that connects directly to embedded PCI Express Gen1 (2.5 Gbps) hard intellectual property (IP) to support PCI-SIG* compliant x1, x2, or x4. endpoint or rootport applications.
  • Two phase-locked loop (PLL) inputs on each transmitter; the EP4CGX50 device and larger devices also have independent clock dividers to allow different clock rates for each channel.
  • Built-in byte ordering so that a frame or packet always starts in a known byte lane.
  • 8B/10B encoder and decoder that performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding.
  • On-die power supply regulators for transmitter and receiver PLL charge pump and voltage controlled oscillator (VCO) for superior noise immunity.
  • On-chip power supply decoupling to satisfy transient current requirements at higher frequencies, which reduces the need for on-board decoupling capacitors.
  • Diagnostic features such as serial loopback, parallel loopback, reverse serial loopback, and loopback master and slave capability in the PCI-SIG* compliant PCI Express hard IP block.

The following figure shows the block diagram of the Cyclone® IV GX FPGA transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements.

Cyclone IV GX Supported Protocols

Standards

148-pin QFN, 169-pin FBGA, and 324-pin FBGA Packages

(Data Rate in Gbps)

484-pin FBGA, 672-pin FBGA, and 896-pin FBGA Packages

(Data Rate in Gbps)

Basic Up to 2.5 Up to 3.125
PCI Express Gen1 2.5 2.5
GbE 1.25 1.25
SDI SD/HD 0.27, 1.488
3G-SDI 2.97
Serial RapidIO® 1.25, 2.5, 3.125
10GbE (XAUI) 3.125
CPRI 0.6144, 1.2288, 2.45, 3.072
OBSAI 0.75, 1.536, 3.072
Serial ATA (SATA) Gen1, Gen2 1.5, 3.0
3G Basic Up to 3.125
DisplayPort 1.62 2.7
V-by-One 3.0

Cyclone® IV FPGA Reference Links