The Cyclone® III architecture consists of up to 120K vertically arranged logic elements (LEs), 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 200 18x18 embedded multipliers. Cyclone® III LS FPGAs have a memory-rich and multiplier-rich floorplan consisting of up to 200K logic elements, 8.2 Mbits of embedded memory, and 396 embedded multipliers.

Both architectures include highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals. The logic and routing core fabric is surrounded by I/O elements (IOEs) and phase-locked loops (PLLs).

The low-power Cyclone® III FPGA family is the third generation in the Cyclone® FPGA series. With its unprecedented combination of low power, high functionality, and low cost, the Cyclone® III FPGA family broadens the number of high-volume, cost-sensitive applications that can benefit from an FPGA. The Cyclone® III LS variant extends the family with higher density, higher memory, smaller packages, and security features to protect your intellectual property (IP).

Key Features

Power

Optimized for low power to help you manage thermal requirements, reduce or eliminate system cooling costs, and extend battery life for handheld applications.

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Density

With up to 200,000 logic elements (LEs), 8.2 Mbits of on-chip memory, and 396 embedded 18x18 multipliers, Cyclone® III devices make up the highest-density low-cost FPGA family in the industry

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Embedded 18 x 18 Multipliers

In digital signal processing (DSP) applications, Cyclone® III FPGAs provide an unprecedented combination of low power consumption, impressive DSP functionality, and low cost.

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Embedded Memory

For memory intensive applications, on-chip memory on Cyclone® III FPGAs has been increased by up to 8 times compared to previous low-cost FPGA generations.

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Cost-Optimized Architecture

Intel introduces the 65-nm Cyclone® III family of FPGAs, the lowest-cost FPGAs ever.

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Clock Management

Includes an extensive global clocking structure and fully featured robust phase-locked loops (PLLs).

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Low-Cost 65 NM FPGAs

Intel's strategy for delivering the Cyclone® III family focuses on leveraging advanced technologies and methods to provide the most capable devices at the lowest cost, while minimizing risk and ensuring short time-to-market for customers.

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Architecture

Cyclone® III FPGAs offer an unprecedented combination of low power, high functionality, and low cost.

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Market Specific Features

Remote System Upgrades

The most comprehensive configuration and remote system upgrade solutions in the industry. These solutions are simple, easy to use, and low cost.

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SEU Mitigation

Offers on-chip circuitry to automatically check cyclic redundancy code. Some critical applications require periodic cyclic redundancy code checks to ensure continued data integrity in a high-reliability environment.

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Security

The first devices to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power, high-functionality FPGA platform.

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Differences

Cyclone® II and Cyclone® III Feature Comparison.

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Connectivity

I/O Flexibility

You have the flexibility to implement a wide variety of I/O standards on your board

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Interface and Protocol Support

Supports serial, bus, and network interfaces, as well as a wide range of communications protocols

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On-Chip Termination

Devices include on-chip series termination (OCT) or driver impedance matching (Rs) for single-ended I/O standards

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Cyclone® III FPGA Reference Links