Intel® Cyclone® 10 LP FPGAs continue the Intel Cyclone series tradition of offering a combination of low power, high functionality, and at a low cost.1

I/O Expansion

The increasing performance requirements of today's embedded systems is driving microprocessor selection. Processor performance, coupled with their fixed interfaces often influences selection of larger processor than required in order to support the I/O feature set that the system requires. An alternative option is to use an optimal processor with a companion FPGA for I/O expansion to enable more functions.

Intel® Cyclone® 10 LP FPGAs are ideally suited to this kind of application with a range of IP blocks, such as I2C, serial peripheral interface (SPI), UART, parallel I/O blocks, and packages supporting over 500 I/Os. Enabling the designer to scale his design to fit the applications needs, rather than limiting either his design to a fixed processor peripheral set or increasing system cost with a larger processor.

Chip to Chip Interfacing

Intel® Cyclone® 10 LP FPGAs are an ideal solution for interfacing between ASSPs. Examples such as between an image sensor and host processors or between the processor and and display. In both of these scenarios using an Intel Cyclone 10 LP FPGA enable designers to combine the interfacing with image pipeline processing for real-time applications that need high frame rates, low latency, and high-processing throughput.

One example application is where a CMOS image sensor captures raw images and output the data via several different type of interfaces: DVP, MIPI CSI, or HiSPi to the FPGA. The FPGA is used to process the image before passing data onto a host processor. A second example of chip to chip interfacing is where the FPGA is used to interface between a video source and LCD. Where video processing of the input image data may be required for various reasons and may be implmented using the Video IP suite from Intel for functions such as:

  • Demosaic & Bayer filtering
  • Converting from one data format to another, example: YUV à RGB
  • Scaling from one size to another: example: 1280x720 à 1920x1080
  • Encoding/decoding, filtering, blending, de/interlacing, cropping, and so on.

Motor Control

Intel® Cyclone® 10 LP FPGAs provides the flexibility for general-purpose interfacing with a maximum I/O count up to 525 user I/Os. It also provides the ability to not only support our customers' diverse drive needs, but also to differentiate their high-volume applications.

In addition to facilitating the implementation and support for a wide variety of industrial Ethernet protocols. The Intel Cyclone 10 LP FPGA fabric is also leveraged to implement pulse width modulator (PWM) and encoder interfaces, which when repeated multiple times in parallel, allows for multi-axis control.

Intel's Field Oriented Control (FOC) algorithm along with the Vibration Suppression IP Core implemented on the Intel Cyclone 10 LP FPGA fabric enables performance acceleration and latency reduction. It also gives the option to off-load and free up the Nios® II processor for other tasks

Additional End Markets

Intel® Cyclone® 10 LP FPGA Reference Links

Product and Performance Information

1

Cost reduction scenarios described are intended as examples of how a given Intel®-based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction.