Stratix® V FPGA Transceivers

Intel transceivers have a proven track record of meeting system bandwidth, power, and bit-error rate (BER) requirements. The technology leadership continues with the transceivers in our 28 nm Stratix V FPGAs.

Building on their predecessors, Stratix V FPGA transceivers come with many enhancements for flexibility and robustness:

  • Additional low-jitter LC transmit phase-locked loops (PLLs)
  • Robust analog receive clock data recovery (CDR)
  • Advanced equalization for 10GBASE-KR backplane support
  • Integration of on-die instrumentation
  • Transceiver data rates at 14.1 Gbps and 28.05 Gbps

Stratix V GX/GS FPGAs are designed for backplane applications. Stratix V GX/GS transceivers offer a number of programmable and adaptive equalization features designed to handle the challenges of backplane links including:

  • 4-tap transmit pre-emphasis
  • Continuous time-linear equalizers (CTLE)
  • Adaptive decision feedback equalizers (DFE)

These solutions are designed to provide the most amount of flexibility and performance at the lowest power in an FPGA transceiver to address the range of problems that are encountered in backplane applications, including 10GBASE-KR backplanes. For more information, please read our white paper on Backplane Applications with 28 nm FPGAs (PDF) as well as our application notes on designing high-speed PCBs for backplane applications.


Transceiver PMA

The flexible PMA is designed to be compliant across a wide range of protocols and mediums. Advanced equalization, on-die instrumentation, and partial reconfiguration are just some of the many PMA features offered on Stratix V FPGA transceivers. See Table 1 for more information on PMA features and capabilities.

Table 1. Transceiver PMA Features



Backplane, chip-to-chip, and chip-to-module support at up to 14.1 Gbps

Stratix V GX and GS FPGAs

Chip-to-chip and chip-to-module support at up to 28.05 Gbps

Stratix V GT FPGAs

Optical module support with electronic dispersion compensation (EDC)


Cable driving support

PCI Express* (PCIe*) cable and eSATA applications

Adaptive continuous-time linear equalization (AEQ)

4-stage linear equalization to support high-attenuation channels with high gain and low power

Adaptive DFE

Adaptive 5-tap digital equalizer to minimize losses and crosstalk

Analog PLL-based clock recovery

Superior jitter tolerance compared to phase-interpolation-based clock recovery

Programmable deserialization and word alignment

Flexible deserialization width and configurable word-alignment patterns

Transmit equalization (pre-emphasis)

Transmit driver with 4-tap FIR pre-emphasis and de-emphasis for protocol compliance under lossy conditions

Ring and LC oscillator transmit PLLs

Choice of transmit PLLs per channel, optimized for lowest power and wide tuning range

On-die instrumentation (Eye Viewer data-eye monitor)

Allows non-intrusive on-chip monitoring of both width and height of data eye

Dynamic and partial reconfiguration

Allows reconfiguration of single channels and the core on the fly, while other portions of the design are still running

Protocol support

Compliance with over 50 industry-standard protocols

Transceiver PCS and Hard Protocol Support

The Stratix V FPGA core logic connects to the PCS via an 8, 10, 16, 20, 32, 40, 64, or 66 bit interface, depending on the transceiver data rate and protocol. Stratix V FPGAs contain hard IP blocks to support PCIe Gen3, Gen2, and Gen1, as well as hardened PCS features to support 40G/100G Ethernet, Interlaken, 10 Gbps Ethernet (10GbE), RapidIO*, and CPRI. Figure 4 details some of the main building blocks in the PCS to support the broad range of protocols.

Figure 4. PCS Building Blocks