Stratix® V FPGA Transceivers

Table 1. Transceiver PMA Features



Backplane, chip-to-chip, and chip-to-module support at up to 14.1 Gbps

Stratix V GX and GS FPGAs

Chip-to-chip and chip-to-module support at up to 28.05 Gbps

Stratix V GT FPGAs

Optical module support with electronic dispersion compensation (EDC)


Cable driving support

PCI Express* (PCIe*) cable and eSATA applications

Adaptive continuous-time linear equalization (AEQ)

4-stage linear equalization to support high-attenuation channels with high gain and low power

Adaptive DFE

Adaptive 5-tap digital equalizer to minimize losses and crosstalk

Analog PLL-based clock recovery

Superior jitter tolerance compared to phase-interpolation-based clock recovery

Programmable deserialization and word alignment

Flexible deserialization width and configurable word-alignment patterns

Transmit equalization (pre-emphasis)

Transmit driver with 4-tap FIR pre-emphasis and de-emphasis for protocol compliance under lossy conditions

Ring and LC oscillator transmit PLLs

Choice of transmit PLLs per channel, optimized for lowest power and wide tuning range

On-die instrumentation (Eye Viewer data-eye monitor)

Allows non-intrusive on-chip monitoring of both width and height of data eye

Dynamic and partial reconfiguration

Allows reconfiguration of single channels and the core on the fly, while other portions of the design are still running

Protocol support

Compliance with over 50 industry-standard protocols