Stratix® IV FPGA TriMatrix Memory

Stratix IV FPGA TriMatrix on-chip memory offers maximum efficiency and flexibility and is based upon the Stratix® III FPGA TriMatrix memory architecture. Stratix IV FPGAs provide:

  • Up to 22.4 Mbits of total memory (in M9K and M144K blocks)
  • Clock rates of up to 600 MHz for total bandwidth in excess of 36 terabits per second
  • Logic array block (LAB)-based MLAB blocks for small grain distributed memory resources
  • Power-down modes based on Intel® FPGA’s Programmable Power Technology
  • Advanced features such as error code correction (ECC)

Each MLAB is implemented using one LAB containing 10 adaptive logic modules (ALMs). Half the LABs in a Stratix IV FPGA can be configured as MLABs. The M9K and M144K blocks are dedicated memory resources. The Stratix IV FPGA Family Overview page lists memory resources for each Stratix IV device.

Figure 1. TriMatrix Memory Structure

Maximum FPGA Memory Efficiency and Bandwidth

By offering three different memory block sizes, Stratix IV FPGAs allow you to select the best fit for your applications. TriMatrix memory significantly improves memory utilization and reduces the need for memory cascading. The MLAB and M9K blocks allow Stratix IV FPGAs to offer more data ports or memory bandwidth than other FPGAs. Table 1 shows how you can use TriMatrix memory to address a variety of memory applications.

Table 1. TriMatrix Memory Application Examples

Memory Block

Applications

MLAB

  • Shift registers
  • Small FIFO buffers
  • Filter delay lines

M9K

  • General-purpose memory
  • Packet header or cell buffers

M144K

  • Processor code storage
  • Packet buffers
  • Video frame buffers

Advanced FPGA Memory Features

TriMatrix memory incorporates many advanced features:

  • Simple and true dual-port modes
  • Packed mode allowing each M9K or M144K block to be split into two half-size memories
  • M144K blocks contain a dedicated ECC feature to detect and correct soft errors
  • ECC can be implemented using logic for the MLAB and M9K blocks
  • Unused memory blocks are automatically put into the low power mode, providing more power savings

Table 2 shows the advanced memory features of Stratix IV TriMatrix memory.

Table 2. TriMatrix Memory Features

Feature

MLAB
640 Bits

M9K
9,216 Bits

M144K
147,456 Bits

Performance

600 MHz

600 MHz

600 MHz

Depth x Maximum Width

32 x 20

256 x 36

2,048 x 72

Simple Dual-Port

Yes

Yes

Yes

True Dual-Port

No

Yes

Yes

Parity

Yes

Yes

Yes

ECC

Yes

Yes

Yes

Packed Mode

No

Yes

Yes

Low Power Mode

Yes

Yes

Yes

Shift Register

Yes

Yes

Yes

FIFO

Yes

Yes

Yes

Initialization

Yes

Yes

Yes

Mixed-Clock

Yes

Yes

Yes

Byte Enable

Yes

Yes

Yes

Address Clock Enable

Yes

Yes

Yes

The Stratix® IV FPGA Family Overview page lists memory resources for each Stratix® IV device.